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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_fifo.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.
//
// Revision 1.5  2003/01/14 17:25:09  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.4  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.3  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.2  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.1  2003/01/08 02:10:55  mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_fifo
(
  clk,
  rst,
 
  wr,
 
  data_in,
  addr,
  data_out,
 
  reset_mode,
  release_buffer,
  extended_mode
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         wr;
input   [7:0] data_in;
input   [7:0] addr;
input         reset_mode;
input         release_buffer;
input         extended_mode;
 
output  [7:0] data_out;
 
 
reg     [7:0] fifo [0:63];
reg     [5:0] rd_pointer;
reg     [5:0] wr_pointer;
reg     [5:0] read_address;
reg     [3:0] length_info[0:63];
reg     [5:0] wr_info_pointer;
reg     [5:0] rd_info_pointer;
reg           overrun_info[0:63];
reg           wr_q;
reg     [3:0] len_cnt;
reg     [6:0] fifo_cnt;
reg           latch_overrun;
 
wire          write_length_info;
wire          fifo_empty;
wire          fifo_full;
 
assign write_length_info = (~wr) & wr_q;
 
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_q <= 0;
  else if (reset_mode)
    wr_q <=#Tp 0;
  else
    wr_q <=#Tp wr;
end
 
 
// length counter
always @ (posedge clk or posedge rst)
begin
  if (rst)
    len_cnt <= 0;
  else if (reset_mode | write_length_info)
    len_cnt <=#Tp 1'b0;
  else if (wr & (~fifo_full))
    len_cnt <=#Tp len_cnt + 1'b1;
end
 
 
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_info_pointer <= 0;
  else if (reset_mode)
    wr_info_pointer <=#Tp 0;
  else if (write_length_info)
    wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
end
 
 
// length_info
always @ (posedge clk)
begin
  if (write_length_info)
    length_info[wr_info_pointer] <=#Tp len_cnt;
end
 
 
// overrun_info
always @ (posedge clk)
begin
  if (write_length_info)
    overrun_info[wr_info_pointer] <=#Tp latch_overrun | (wr & fifo_full);
end
 
 
 
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_info_pointer <= 0;
  else if (reset_mode)
    rd_info_pointer <=#Tp 0;
  else if (release_buffer & (~fifo_empty))
    rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
 
 
// rd_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_pointer <= 0;
  else if (release_buffer & (~fifo_empty))
    rd_pointer <=#Tp rd_pointer + length_info[rd_info_pointer];
  else if (reset_mode)
    rd_pointer <=#Tp 0;
end
 
 
// wr_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_pointer <= 0;
  else if (wr & (~fifo_full))
    wr_pointer <=#Tp wr_pointer + 1'b1;
  else if (reset_mode)
    wr_pointer <=#Tp 0;
end
 
 
// latch_overrun
always @ (posedge clk or posedge rst)
begin
  if (rst)
    latch_overrun <= 0;
  else if (reset_mode | write_length_info)
    latch_overrun <=#Tp 0;
  else if (wr & fifo_full)
    latch_overrun <=#Tp 1'b1;
end
 
 
// Counting data in fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    fifo_cnt <= 0;
  else if (wr & (~release_buffer) & (~fifo_full))
    fifo_cnt <=#Tp fifo_cnt + 1'b1;
  else if ((~wr) & release_buffer & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer];
  else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer] + 1'b1;
  else if (reset_mode)
    fifo_cnt <=#Tp 0;
end
 
assign fifo_full = fifo_cnt == 64;
assign fifo_empty = fifo_cnt == 0;
 
 
 
// writing data to fifo
always @ (posedge clk)
begin
  if (wr & (~fifo_full))
    fifo[wr_pointer] <=#Tp data_in;
end
 
 
 
// Selecting which address will be used for reading data from rx fifo
always @ (extended_mode or rd_pointer or addr)
begin
  if (extended_mode)      // extended mode
    begin
      read_address <= rd_pointer + (addr - 8'd16);
    end
  else                    // normal mode
    begin
      read_address <= rd_pointer + (addr - 8'd20);
    end
end
 
 
 
assign data_out = fifo[read_address];
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	11	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_fifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002, 2003 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	23	mohor	`// Revision 1.6 2003/01/15 13:16:47 mohor`
49			`// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.`
50			`//`
51	18	mohor	`// Revision 1.5 2003/01/14 17:25:09 mohor`
52			`// Addresses corrected to decimal values (previously hex).`
53			`//`
54	17	mohor	`// Revision 1.4 2003/01/14 12:19:35 mohor`
55			`// rx_fifo is now working.`
56			`//`
57	16	mohor	`// Revision 1.3 2003/01/09 21:54:45 mohor`
58			`// rx fifo added. Not 100 % verified, yet.`
59			`//`
60	14	mohor	`// Revision 1.2 2003/01/09 14:46:58 mohor`
61			`// Temporary files (backup).`
62			`//`
63	13	mohor	`// Revision 1.1 2003/01/08 02:10:55 mohor`
64			`// Acceptance filter added.`
65	11	mohor	`//`
66			`//`
67			`//`
68	13	mohor	`//`
69	11	mohor
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "can_defines.v"
74
75			`module can_fifo`
76			`(`
77			`clk,`
78			`rst,`
79
80			`wr,`
81
82			`data_in,`
83	14	mohor	`addr,`
84	11	mohor	`data_out,`
85
86			`reset_mode,`
87	14	mohor	`release_buffer,`
88			`extended_mode`
89	13	mohor
90	11	mohor	`);`
91
92			`parameter Tp = 1;`
93
94			`input clk;`
95			`input rst;`
96			`input wr;`
97			`input [7:0] data_in;`
98	14	mohor	`input [7:0] addr;`
99	11	mohor	`input reset_mode;`
100			`input release_buffer;`
101	14	mohor	`input extended_mode;`
102	11	mohor
103	13	mohor	`output [7:0] data_out;`
104	11	mohor
105
106			`reg [7:0] fifo [0:63];`
107			`reg [5:0] rd_pointer;`
108			`reg [5:0] wr_pointer;`
109	14	mohor	`reg [5:0] read_address;`
110	16	mohor	`reg [3:0] length_info[0:63];`
111			`reg [5:0] wr_info_pointer;`
112			`reg [5:0] rd_info_pointer;`
113			`reg overrun_info[0:63];`
114	13	mohor	`reg wr_q;`
115			`reg [3:0] len_cnt;`
116	16	mohor	`reg [6:0] fifo_cnt;`
117			`reg latch_overrun;`
118	11	mohor
119	13	mohor	`wire write_length_info;`
120	16	mohor	`wire fifo_empty;`
121			`wire fifo_full;`
122	11	mohor
123	13	mohor	`assign write_length_info = (~wr) & wr_q;`
124
125			`// Delayed write signal`
126			`always @ (posedge clk or posedge rst)`
127			`begin`
128			`if (rst)`
129			`wr_q <= 0;`
130			`else if (reset_mode)`
131			`wr_q <=#Tp 0;`
132			`else`
133			`wr_q <=#Tp wr;`
134			`end`
135
136
137			`// length counter`
138			`always @ (posedge clk or posedge rst)`
139			`begin`
140			`if (rst)`
141			`len_cnt <= 0;`
142			`else if (reset_mode \| write_length_info)`
143			`len_cnt <=#Tp 1'b0;`
144	16	mohor	`else if (wr & (~fifo_full))`
145	13	mohor	`len_cnt <=#Tp len_cnt + 1'b1;`
146			`end`
147
148
149			`// wr_info_pointer`
150			`always @ (posedge clk or posedge rst)`
151			`begin`
152			`if (rst)`
153			`wr_info_pointer <= 0;`
154			`else if (reset_mode)`
155			`wr_info_pointer <=#Tp 0;`
156			`else if (write_length_info)`
157			`wr_info_pointer <=#Tp wr_info_pointer + 1'b1;`
158			`end`
159
160
161	11	mohor	`// length_info`
162	13	mohor	`always @ (posedge clk)`
163			`begin`
164			`if (write_length_info)`
165			`length_info[wr_info_pointer] <=#Tp len_cnt;`
166			`end`
167
168
169	16	mohor	`// overrun_info`
170			`always @ (posedge clk)`
171			`begin`
172			`if (write_length_info)`
173			`overrun_info[wr_info_pointer] <=#Tp latch_overrun \| (wr & fifo_full);`
174			`end`
175
176
177
178	13	mohor	`// rd_info_pointer`
179	11	mohor	`always @ (posedge clk or posedge rst)`
180			`begin`
181			`if (rst)`
182	13	mohor	`rd_info_pointer <= 0;`
183	11	mohor	`else if (reset_mode)`
184	13	mohor	`rd_info_pointer <=#Tp 0;`
185	16	mohor	`else if (release_buffer & (~fifo_empty))`
186	13	mohor	`rd_info_pointer <=#Tp rd_info_pointer + 1'b1;`
187	11	mohor	`end`
188
189
190			`// rd_pointer`
191			`always @ (posedge clk or posedge rst)`
192			`begin`
193			`if (rst)`
194			`rd_pointer <= 0;`
195	16	mohor	`else if (release_buffer & (~fifo_empty))`
196	13	mohor	`rd_pointer <=#Tp rd_pointer + length_info[rd_info_pointer];`
197	11	mohor	`else if (reset_mode)`
198			`rd_pointer <=#Tp 0;`
199			`end`
200
201
202			`// wr_pointer`
203			`always @ (posedge clk or posedge rst)`
204			`begin`
205			`if (rst)`
206			`wr_pointer <= 0;`
207	16	mohor	`else if (wr & (~fifo_full))`
208	13	mohor	`wr_pointer <=#Tp wr_pointer + 1'b1;`
209	11	mohor	`else if (reset_mode)`
210			`wr_pointer <=#Tp 0;`
211			`end`
212
213
214	16	mohor	`// latch_overrun`
215			`always @ (posedge clk or posedge rst)`
216			`begin`
217			`if (rst)`
218			`latch_overrun <= 0;`
219			`else if (reset_mode \| write_length_info)`
220			`latch_overrun <=#Tp 0;`
221			`else if (wr & fifo_full)`
222			`latch_overrun <=#Tp 1'b1;`
223			`end`
224
225
226			`// Counting data in fifo`
227			`always @ (posedge clk or posedge rst)`
228			`begin`
229			`if (rst)`
230			`fifo_cnt <= 0;`
231			`else if (wr & (~release_buffer) & (~fifo_full))`
232			`fifo_cnt <=#Tp fifo_cnt + 1'b1;`
233			`else if ((~wr) & release_buffer & (~fifo_empty))`
234			`fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer];`
235			`else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))`
236			`fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer] + 1'b1;`
237			`else if (reset_mode)`
238			`fifo_cnt <=#Tp 0;`
239			`end`
240
241			`assign fifo_full = fifo_cnt == 64;`
242			`assign fifo_empty = fifo_cnt == 0;`
243
244
245
246	11	mohor	`// writing data to fifo`
247	23	mohor	`always @ (posedge clk)`
248	11	mohor	`begin`
249	16	mohor	`if (wr & (~fifo_full))`
250	11	mohor	`fifo[wr_pointer] <=#Tp data_in;`
251			`end`
252
253
254
255	14	mohor	`// Selecting which address will be used for reading data from rx fifo`
256			`always @ (extended_mode or rd_pointer or addr)`
257			`begin`
258			`if (extended_mode) // extended mode`
259			`begin`
260	17	mohor	`read_address <= rd_pointer + (addr - 8'd16);`
261	14	mohor	`end`
262			`else // normal mode`
263			`begin`
264	17	mohor	`read_address <= rd_pointer + (addr - 8'd20);`
265	14	mohor	`end`
266			`end`
267	11	mohor
268
269	14	mohor
270			`assign data_out = fifo[read_address];`
271
272
273
274
275	11	mohor	`endmodule`

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