URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [asyst_3/] [rtl/] [verilog/] [can_fifo.v] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_fifo.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2003/01/17 17:44:31  mohor
// Fifo corrected to be synthesizable.
//
// Revision 1.6  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.
//
// Revision 1.5  2003/01/14 17:25:09  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.4  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.3  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.2  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.1  2003/01/08 02:10:55  mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_fifo
(
  clk,
  rst,
 
  wr,
 
  data_in,
  addr,
  data_out,
 
  reset_mode,
  release_buffer,
  extended_mode
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         wr;
input   [7:0] data_in;
input   [7:0] addr;
input         reset_mode;
input         release_buffer;
input         extended_mode;
 
output  [7:0] data_out;
 
 
reg     [7:0] fifo [0:63];
reg     [5:0] rd_pointer;
reg     [5:0] wr_pointer;
reg     [5:0] read_address;
reg     [3:0] length_info[0:63];
reg     [5:0] wr_info_pointer;
reg     [5:0] rd_info_pointer;
reg           overrun_info[0:63];
reg           wr_q;
reg     [3:0] len_cnt;
reg     [6:0] fifo_cnt;
reg     [6:0] info_cnt;
reg           latch_overrun;
 
wire          write_length_info;
wire          fifo_empty;
wire          fifo_full;
wire          info_full;
wire          info_empty;
 
assign write_length_info = (~wr) & wr_q;
 
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_q <= 0;
  else if (reset_mode)
    wr_q <=#Tp 0;
  else
    wr_q <=#Tp wr;
end
 
 
// length counter
always @ (posedge clk or posedge rst)
begin
  if (rst)
    len_cnt <= 0;
  else if (reset_mode | write_length_info)
    len_cnt <=#Tp 1'b0;
  else if (wr & (~fifo_full))
    len_cnt <=#Tp len_cnt + 1'b1;
end
 
 
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_info_pointer <= 0;
  else if (reset_mode)
    wr_info_pointer <=#Tp 0;
  else if (write_length_info & (~info_full))
    wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
end
 
 
// length_info
always @ (posedge clk)
begin
  if (write_length_info & (~info_full))
    length_info[wr_info_pointer] <=#Tp len_cnt;
end
 
 
// overrun_info
always @ (posedge clk)
begin
  if (write_length_info & (~info_full))
    overrun_info[wr_info_pointer] <=#Tp latch_overrun | (wr & fifo_full);
end
 
 
 
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_info_pointer <= 0;
  else if (reset_mode)
    rd_info_pointer <=#Tp 0;
  else if (release_buffer & (~fifo_empty))
    rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
 
 
// rd_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_pointer <= 0;
  else if (release_buffer & (~fifo_empty))
    rd_pointer <=#Tp rd_pointer + length_info[rd_info_pointer];
  else if (reset_mode)
    rd_pointer <=#Tp 0;
end
 
 
// wr_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_pointer <= 0;
  else if (wr & (~fifo_full))
    wr_pointer <=#Tp wr_pointer + 1'b1;
  else if (reset_mode)
    wr_pointer <=#Tp 0;
end
 
 
// latch_overrun
always @ (posedge clk or posedge rst)
begin
  if (rst)
    latch_overrun <= 0;
  else if (reset_mode | write_length_info)
    latch_overrun <=#Tp 0;
  else if (wr & fifo_full)
    latch_overrun <=#Tp 1'b1;
end
 
 
// Counting data in fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    fifo_cnt <= 0;
  else if (wr & (~release_buffer) & (~fifo_full))
    fifo_cnt <=#Tp fifo_cnt + 1'b1;
  else if ((~wr) & release_buffer & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer];
  else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer] + 1'b1;
  else if (reset_mode)
    fifo_cnt <=#Tp 0;
end
 
assign fifo_full = fifo_cnt == 64;
assign fifo_empty = fifo_cnt == 0;
 
 
// Counting data in length_info and overrun_info fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    info_cnt <= 0;
  else if (write_length_info ^ release_buffer)
    begin
      if (release_buffer & (~info_empty))
        info_cnt <=#Tp info_cnt - 1'b1;
      else if (write_length_info & (~info_full))
        info_cnt <=#Tp info_cnt + 1'b1;
    end
end
 
assign info_full = info_cnt == 64;
assign info_empty = info_cnt == 0;
 
 
// writing data to fifo
always @ (posedge clk)
begin
  if (wr & (~fifo_full))
    fifo[wr_pointer] <=#Tp data_in;
end
 
 
 
// Selecting which address will be used for reading data from rx fifo
always @ (extended_mode or rd_pointer or addr)
begin
  if (extended_mode)      // extended mode
    begin
      read_address <= rd_pointer + (addr - 8'd16);
    end
  else                    // normal mode
    begin
      read_address <= rd_pointer + (addr - 8'd20);
    end
end
 
 
 
assign data_out = fifo[read_address];
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	11	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_fifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002, 2003 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	24	mohor	`// Revision 1.7 2003/01/17 17:44:31 mohor`
49			`// Fifo corrected to be synthesizable.`
50			`//`
51	23	mohor	`// Revision 1.6 2003/01/15 13:16:47 mohor`
52			`// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.`
53			`//`
54	18	mohor	`// Revision 1.5 2003/01/14 17:25:09 mohor`
55			`// Addresses corrected to decimal values (previously hex).`
56			`//`
57	17	mohor	`// Revision 1.4 2003/01/14 12:19:35 mohor`
58			`// rx_fifo is now working.`
59			`//`
60	16	mohor	`// Revision 1.3 2003/01/09 21:54:45 mohor`
61			`// rx fifo added. Not 100 % verified, yet.`
62			`//`
63	14	mohor	`// Revision 1.2 2003/01/09 14:46:58 mohor`
64			`// Temporary files (backup).`
65			`//`
66	13	mohor	`// Revision 1.1 2003/01/08 02:10:55 mohor`
67			`// Acceptance filter added.`
68	11	mohor	`//`
69			`//`
70			`//`
71	13	mohor	`//`
72	11	mohor
73			`// synopsys translate_off`
74			`include "timescale.v"
75			`// synopsys translate_on`
76			`include "can_defines.v"
77
78			`module can_fifo`
79			`(`
80			`clk,`
81			`rst,`
82
83			`wr,`
84
85			`data_in,`
86	14	mohor	`addr,`
87	11	mohor	`data_out,`
88
89			`reset_mode,`
90	14	mohor	`release_buffer,`
91			`extended_mode`
92	13	mohor
93	11	mohor	`);`
94
95			`parameter Tp = 1;`
96
97			`input clk;`
98			`input rst;`
99			`input wr;`
100			`input [7:0] data_in;`
101	14	mohor	`input [7:0] addr;`
102	11	mohor	`input reset_mode;`
103			`input release_buffer;`
104	14	mohor	`input extended_mode;`
105	11	mohor
106	13	mohor	`output [7:0] data_out;`
107	11	mohor
108
109			`reg [7:0] fifo [0:63];`
110			`reg [5:0] rd_pointer;`
111			`reg [5:0] wr_pointer;`
112	14	mohor	`reg [5:0] read_address;`
113	16	mohor	`reg [3:0] length_info[0:63];`
114			`reg [5:0] wr_info_pointer;`
115			`reg [5:0] rd_info_pointer;`
116			`reg overrun_info[0:63];`
117	13	mohor	`reg wr_q;`
118			`reg [3:0] len_cnt;`
119	16	mohor	`reg [6:0] fifo_cnt;`
120	24	mohor	`reg [6:0] info_cnt;`
121	16	mohor	`reg latch_overrun;`
122	11	mohor
123	13	mohor	`wire write_length_info;`
124	16	mohor	`wire fifo_empty;`
125			`wire fifo_full;`
126	24	mohor	`wire info_full;`
127			`wire info_empty;`
128	11	mohor
129	13	mohor	`assign write_length_info = (~wr) & wr_q;`
130
131			`// Delayed write signal`
132			`always @ (posedge clk or posedge rst)`
133			`begin`
134			`if (rst)`
135			`wr_q <= 0;`
136			`else if (reset_mode)`
137			`wr_q <=#Tp 0;`
138			`else`
139			`wr_q <=#Tp wr;`
140			`end`
141
142
143			`// length counter`
144			`always @ (posedge clk or posedge rst)`
145			`begin`
146			`if (rst)`
147			`len_cnt <= 0;`
148			`else if (reset_mode \| write_length_info)`
149			`len_cnt <=#Tp 1'b0;`
150	16	mohor	`else if (wr & (~fifo_full))`
151	13	mohor	`len_cnt <=#Tp len_cnt + 1'b1;`
152			`end`
153
154
155			`// wr_info_pointer`
156			`always @ (posedge clk or posedge rst)`
157			`begin`
158			`if (rst)`
159			`wr_info_pointer <= 0;`
160			`else if (reset_mode)`
161			`wr_info_pointer <=#Tp 0;`
162	24	mohor	`else if (write_length_info & (~info_full))`
163	13	mohor	`wr_info_pointer <=#Tp wr_info_pointer + 1'b1;`
164			`end`
165
166
167	11	mohor	`// length_info`
168	13	mohor	`always @ (posedge clk)`
169			`begin`
170	24	mohor	`if (write_length_info & (~info_full))`
171	13	mohor	`length_info[wr_info_pointer] <=#Tp len_cnt;`
172			`end`
173
174
175	16	mohor	`// overrun_info`
176			`always @ (posedge clk)`
177			`begin`
178	24	mohor	`if (write_length_info & (~info_full))`
179	16	mohor	`overrun_info[wr_info_pointer] <=#Tp latch_overrun \| (wr & fifo_full);`
180			`end`
181
182
183
184	13	mohor	`// rd_info_pointer`
185	11	mohor	`always @ (posedge clk or posedge rst)`
186			`begin`
187			`if (rst)`
188	13	mohor	`rd_info_pointer <= 0;`
189	11	mohor	`else if (reset_mode)`
190	13	mohor	`rd_info_pointer <=#Tp 0;`
191	16	mohor	`else if (release_buffer & (~fifo_empty))`
192	13	mohor	`rd_info_pointer <=#Tp rd_info_pointer + 1'b1;`
193	11	mohor	`end`
194
195
196			`// rd_pointer`
197			`always @ (posedge clk or posedge rst)`
198			`begin`
199			`if (rst)`
200			`rd_pointer <= 0;`
201	16	mohor	`else if (release_buffer & (~fifo_empty))`
202	13	mohor	`rd_pointer <=#Tp rd_pointer + length_info[rd_info_pointer];`
203	11	mohor	`else if (reset_mode)`
204			`rd_pointer <=#Tp 0;`
205			`end`
206
207
208			`// wr_pointer`
209			`always @ (posedge clk or posedge rst)`
210			`begin`
211			`if (rst)`
212			`wr_pointer <= 0;`
213	16	mohor	`else if (wr & (~fifo_full))`
214	13	mohor	`wr_pointer <=#Tp wr_pointer + 1'b1;`
215	11	mohor	`else if (reset_mode)`
216			`wr_pointer <=#Tp 0;`
217			`end`
218
219
220	16	mohor	`// latch_overrun`
221			`always @ (posedge clk or posedge rst)`
222			`begin`
223			`if (rst)`
224			`latch_overrun <= 0;`
225			`else if (reset_mode \| write_length_info)`
226			`latch_overrun <=#Tp 0;`
227			`else if (wr & fifo_full)`
228			`latch_overrun <=#Tp 1'b1;`
229			`end`
230
231
232			`// Counting data in fifo`
233			`always @ (posedge clk or posedge rst)`
234			`begin`
235			`if (rst)`
236			`fifo_cnt <= 0;`
237			`else if (wr & (~release_buffer) & (~fifo_full))`
238			`fifo_cnt <=#Tp fifo_cnt + 1'b1;`
239			`else if ((~wr) & release_buffer & (~fifo_empty))`
240			`fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer];`
241			`else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))`
242			`fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer] + 1'b1;`
243			`else if (reset_mode)`
244			`fifo_cnt <=#Tp 0;`
245			`end`
246
247			`assign fifo_full = fifo_cnt == 64;`
248			`assign fifo_empty = fifo_cnt == 0;`
249
250
251	24	mohor	`// Counting data in length_info and overrun_info fifo`
252			`always @ (posedge clk or posedge rst)`
253			`begin`
254			`if (rst)`
255			`info_cnt <= 0;`
256			`else if (write_length_info ^ release_buffer)`
257			`begin`
258			`if (release_buffer & (~info_empty))`
259			`info_cnt <=#Tp info_cnt - 1'b1;`
260			`else if (write_length_info & (~info_full))`
261			`info_cnt <=#Tp info_cnt + 1'b1;`
262			`end`
263			`end`
264
265			`assign info_full = info_cnt == 64;`
266			`assign info_empty = info_cnt == 0;`
267	16	mohor
268	24	mohor
269	11	mohor	`// writing data to fifo`
270	23	mohor	`always @ (posedge clk)`
271	11	mohor	`begin`
272	16	mohor	`if (wr & (~fifo_full))`
273	11	mohor	`fifo[wr_pointer] <=#Tp data_in;`
274			`end`
275
276
277
278	14	mohor	`// Selecting which address will be used for reading data from rx fifo`
279			`always @ (extended_mode or rd_pointer or addr)`
280			`begin`
281			`if (extended_mode) // extended mode`
282			`begin`
283	17	mohor	`read_address <= rd_pointer + (addr - 8'd16);`
284	14	mohor	`end`
285			`else // normal mode`
286			`begin`
287	17	mohor	`read_address <= rd_pointer + (addr - 8'd20);`
288	14	mohor	`end`
289			`end`
290	11	mohor
291
292	14	mohor
293			`assign data_out = fifo[read_address];`
294
295
296
297
298	11	mohor	`endmodule`

Browse

Tools

Subversion Repositories can

[/] [can/] [tags/] [asyst_3/] [rtl/] [verilog/] [can_fifo.v] - Blame information for rev 24