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1 68 mohor 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  can_testbench.v                                             ////
4 
////                                                              ////
5 
////                                                              ////
6 
////  This file is part of the CAN Protocol Controller            ////
7 
////  http://www.opencores.org/projects/can/                      ////
8 
////                                                              ////
9 
////                                                              ////
10 
////  Author(s):                                                  ////
11 
////       Igor Mohor                                             ////
12 
////       igorm@opencores.org                                    ////
13 
////                                                              ////
14 
////                                                              ////
15 
////  All additional information is available in the README.txt   ////
16 
////  file.                                                       ////
17 
////                                                              ////
18 
//////////////////////////////////////////////////////////////////////
19 
////                                                              ////
20 
//// Copyright (C) 2002, 2003 Authors                             ////
21 
////                                                              ////
22 
//// This source file may be used and distributed without         ////
23 
//// restriction provided that this copyright statement is not    ////
24 
//// removed from the file and that any derivative work contains  ////
25 
//// the original copyright notice and the associated disclaimer. ////
26 
////                                                              ////
27 
//// This source file is free software; you can redistribute it   ////
28 
//// and/or modify it under the terms of the GNU Lesser General   ////
29 
//// Public License as published by the Free Software Foundation; ////
30 
//// either version 2.1 of the License, or (at your option) any   ////
31 
//// later version.                                               ////
32 
////                                                              ////
33 
//// This source is distributed in the hope that it will be       ////
34 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37 
//// details.                                                     ////
38 
////                                                              ////
39 
//// You should have received a copy of the GNU Lesser General    ////
40 
//// Public License along with this source; if not, download it   ////
41 
//// from http://www.opencores.org/lgpl.shtml                     ////
42 
////                                                              ////
43 
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
44 
//// protected by patents. Anybody who wants to implement this    ////
45 
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
46 
//// from Bosch.                                                  ////
47 
////                                                              ////
48 
//////////////////////////////////////////////////////////////////////
49 
//
50 
// CVS Revision History
51 
//
52 
// $Log: not supported by cvs2svn $
53 
// Revision 1.33  2003/03/14 19:37:30  mohor
54 
// ALE changes on negedge of clk.
55 
//
56 
// Revision 1.32  2003/03/12 05:57:36  mohor
57 
// Bidirectional port_0_i changed to port_0_io.
58 
// input cs_can changed to cs_can_i.
59 
//
60 
// Revision 1.31  2003/03/12 04:40:00  mohor
61 
// rd_i and wr_i are active high signals. If 8051 is connected, these two signals
62 
// need to be negated one level higher.
63 
//
64 
// Revision 1.30  2003/03/12 04:16:40  mohor
65 
// 8051 interface added (besides WISHBONE interface). Selection is made in
66 
// can_defines.v file.
67 
//
68 
// Revision 1.29  2003/03/05 15:33:37  mohor
69 
// tx_o is now tristated signal. tx_oen and tx_o combined together.
70 
//
71 
// Revision 1.28  2003/03/05 15:00:49  mohor
72 
// Top level signal names changed.
73 
//
74 
// Revision 1.27  2003/03/01 22:48:26  mohor
75 
// Actel APA ram supported.
76 
//
77 
// Revision 1.26  2003/02/19 14:43:17  mohor
78 
// CAN core finished. Host interface added. Registers finished.
79 
// Synchronization to the wishbone finished.
80 
//
81 
// Revision 1.25  2003/02/18 00:19:39  mohor
82 
// Temporary backup version (still fully operable).
83 
//
84 
// Revision 1.24  2003/02/14 20:16:53  mohor
85 
// Several registers added. Not finished, yet.
86 
//
87 
// Revision 1.23  2003/02/12 14:28:30  mohor
88 
// Errors monitoring improved. arbitration_lost improved.
89 
//
90 
// Revision 1.22  2003/02/11 00:57:19  mohor
91 
// Wishbone interface added.
92 
//
93 
// Revision 1.21  2003/02/09 18:40:23  mohor
94 
// Overload fixed. Hard synchronization also enabled at the last bit of
95 
// interframe.
96 
//
97 
// Revision 1.20  2003/02/09 02:24:11  mohor
98 
// Bosch license warning added. Error counters finished. Overload frames
99 
// still need to be fixed.
100 
//
101 
// Revision 1.19  2003/02/04 17:24:33  mohor
102 
// Backup.
103 
//
104 
// Revision 1.18  2003/02/04 14:34:45  mohor
105 
// *** empty log message ***
106 
//
107 
// Revision 1.17  2003/01/31 01:13:31  mohor
108 
// backup.
109 
//
110 
// Revision 1.16  2003/01/16 13:36:14  mohor
111 
// Form error supported. When receiving messages, last bit of the end-of-frame
112 
// does not generate form error. Receiver goes to the idle mode one bit sooner.
113 
// (CAN specification ver 2.0, part B, page 57).
114 
//
115 
// Revision 1.15  2003/01/15 21:05:06  mohor
116 
// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
117 
//
118 
// Revision 1.14  2003/01/15 14:40:16  mohor
119 
// RX state machine fixed to receive "remote request" frames correctly. No
120 
// data bytes are written to fifo when such frames are received.
121 
//
122 
// Revision 1.13  2003/01/15 13:16:42  mohor
123 
// When a frame with "remote request" is received, no data is stored to
124 
// fifo, just the frame information (identifier, ...). Data length that
125 
// is stored is the received data length and not the actual data length
126 
// that is stored to fifo.
127 
//
128 
// Revision 1.12  2003/01/14 17:25:03  mohor
129 
// Addresses corrected to decimal values (previously hex).
130 
//
131 
// Revision 1.11  2003/01/14 12:19:29  mohor
132 
// rx_fifo is now working.
133 
//
134 
// Revision 1.10  2003/01/10 17:51:28  mohor
135 
// Temporary version (backup).
136 
//
137 
// Revision 1.9  2003/01/09 21:54:39  mohor
138 
// rx fifo added. Not 100 % verified, yet.
139 
//
140 
// Revision 1.8  2003/01/08 02:09:43  mohor
141 
// Acceptance filter added.
142 
//
143 
// Revision 1.7  2002/12/28 04:13:53  mohor
144 
// Backup version.
145 
//
146 
// Revision 1.6  2002/12/27 00:12:48  mohor
147 
// Header changed, testbench improved to send a frame (crc still missing).
148 
//
149 
// Revision 1.5  2002/12/26 16:00:29  mohor
150 
// Testbench define file added. Clock divider register added.
151 
//
152 
// Revision 1.4  2002/12/26 01:33:01  mohor
153 
// Tripple sampling supported.
154 
//
155 
// Revision 1.3  2002/12/25 23:44:12  mohor
156 
// Commented lines removed.
157 
//
158 
// Revision 1.2  2002/12/25 14:16:54  mohor
159 
// Synchronization working.
160 
//
161 
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
162 
// Initial
163 
//
164 
//
165 
//
166 
 
167 
// synopsys translate_off
168 
`include "timescale.v"
169 
// synopsys translate_on
170 
`include "can_defines.v"
171 
`include "can_testbench_defines.v"
172 
 
173 
module can_testbench();
174 
 
175 
 
176 
 
177 
parameter Tp = 1;
178 
parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
179 
 
180 
 
181 
`ifdef CAN_WISHBONE_IF
182 
  reg         wb_clk_i;
183 
  reg         wb_rst_i;
184 
  reg   [7:0] wb_dat_i;
185 
  wire  [7:0] wb_dat_o;
186 
  reg         wb_cyc_i;
187 
  reg         wb_stb_i;
188 
  reg         wb_we_i;
189 
  reg   [7:0] wb_adr_i;
190 
  wire        wb_ack_o;
191 
  reg         wb_free;
192 
`else
193 
  reg         rst_i;
194 
  reg         ale_i;
195 
  reg         rd_i;
196 
  reg         wr_i;
197 
  wire  [7:0] port_0;
198 
  wire  [7:0] port_0_i;
199 
  reg   [7:0] port_0_o;
200 
  reg         port_0_en;
201 
  reg         port_free;
202 
`endif
203 
 
204 
 
205 
reg         cs_can;
206 
reg         clk;
207 
reg         rx;
208 
wire        tx;
209 
wire        irq;
210 
wire        clkout;
211 
 
212 
wire        rx_and_tx;
213 
 
214 
integer     start_tb;
215 
reg   [7:0] tmp_data;
216 
reg         delayed_tx;
217 
reg         tx_bypassed;
218 
reg         extended_mode;
219 
 
220 
 
221 
 
222 
// Instantiate can_top module
223 
can_top i_can_top
224 
(
225 
`ifdef CAN_WISHBONE_IF
226 
  .wb_clk_i(wb_clk_i),
227 
  .wb_rst_i(wb_rst_i),
228 
  .wb_dat_i(wb_dat_i),
229 
  .wb_dat_o(wb_dat_o),
230 
  .wb_cyc_i(wb_cyc_i),
231 
  .wb_stb_i(wb_stb_i),
232 
  .wb_we_i(wb_we_i),
233 
  .wb_adr_i(wb_adr_i),
234 
  .wb_ack_o(wb_ack_o),
235 
`else
236 
  .rst_i(rst_i),
237 
  .ale_i(ale_i),
238 
  .rd_i(rd_i),
239 
  .wr_i(wr_i),
240 
  .port_0_io(port_0),
241 
`endif
242 
  .cs_can_i(cs_can),
243 
  .clk_i(clk),
244 
  .rx_i(rx_and_tx),
245 
  .tx_o(tx),
246 
  .irq_on(irq),
247 
  .clkout_o(clkout)
248 
);
249 
 
250 
 
251 
`ifdef CAN_WISHBONE_IF
252 
  // Generate wishbone clock signal 10 MHz
253 
  initial
254 
  begin
255 
    wb_clk_i=0;
256 
    forever #50 wb_clk_i = ~wb_clk_i;
257 
  end
258 
`endif
259 
 
260 
 
261 
`ifdef CAN_WISHBONE_IF
262 
`else
263 
  assign port_0_i = port_0;
264 
  assign port_0 = port_0_en? port_0_o : 8'hz;
265 
`endif
266 
 
267 
 
268 
// Generate clock signal 24 MHz
269 
initial
270 
begin
271 
  clk=0;
272 
  forever #21 clk = ~clk;
273 
end
274 
 
275 
 
276 
initial
277 
begin
278 
  start_tb = 0;
279 
  cs_can = 0;
280 
  rx = 1;
281 
  extended_mode = 0;
282 
  tx_bypassed = 0;
283 
 
284 
  `ifdef CAN_WISHBONE_IF
285 
    wb_dat_i = 'hz;
286 
    wb_cyc_i = 0;
287 
    wb_stb_i = 0;
288 
    wb_we_i = 'hz;
289 
    wb_adr_i = 'hz;
290 
    wb_free = 1;
291 
    wb_rst_i = 1;
292 
    #200 wb_rst_i = 0;
293 
    #200 start_tb = 1;
294 
  `else
295 
    rst_i = 1'b0;
296 
    ale_i = 1'b0;
297 
    rd_i  = 1'b0;
298 
    wr_i  = 1'b0;
299 
    port_0_o = 8'h0;
300 
    port_0_en = 0;
301 
    port_free = 1;
302 
    rst_i = 1;
303 
    #200 rst_i = 0;
304 
    #200 start_tb = 1;
305 
  `endif
306 
end
307 
 
308 
 
309 
 
310 
 
311 
// Generating delayed tx signal (CAN transciever delay)
312 
always
313 
begin
314 
  wait (tx);
315 
  repeat (4*BRP) @ (posedge clk);   // 4 time quants delay
316 
  #1 delayed_tx = tx;
317 
  wait (~tx);
318 
  repeat (4*BRP) @ (posedge clk);   // 4 time quants delay
319 
  #1 delayed_tx = tx;
320 
end
321 
 
322 
//assign rx_and_tx = rx & delayed_tx;   FIX ME !!!
323 
assign rx_and_tx = rx & (delayed_tx | tx_bypassed);   // When this signal is on, tx is not looped back to the rx.
324 
 
325 
 
326 
// Main testbench
327 
initial
328 
begin
329 
  wait(start_tb);
330 
 
331 
  // Set bus timing register 0
332 
  write_register(8'd6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
333 
 
334 
  // Set bus timing register 1
335 
  write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
336 
 
337 
 
338 
  // Set Clock Divider register
339 
  extended_mode = 1'b0;
340 
  write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0});   // Setting the normal mode (not extended)
341 
 
342 
 
343 
  // Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
344 
/*
345 
  // Set Acceptance Code and Acceptance Mask registers
346 
  write_register(8'd16, 8'ha6); // acceptance code 0
347 
  write_register(8'd17, 8'hb0); // acceptance code 1
348 
  write_register(8'd18, 8'h12); // acceptance code 2
349 
  write_register(8'd19, 8'h30); // acceptance code 3
350 
  write_register(8'd20, 8'h0); // acceptance mask 0
351 
  write_register(8'd21, 8'h0); // acceptance mask 1
352 
  write_register(8'd22, 8'h00); // acceptance mask 2
353 
  write_register(8'd23, 8'h00); // acceptance mask 3
354 
*/
355 
 
356 
  // Set Acceptance Code and Acceptance Mask registers
357 
  write_register(8'd4, 8'he8); // acceptance code
358 
  write_register(8'd5, 8'h0f); // acceptance mask
359 
 
360 
  #10;
361 
  repeat (1000) @ (posedge clk);
362 
 
363 
  // Switch-off reset mode
364 
  write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
365 
 
366 
  repeat (BRP) @ (posedge clk);   // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
367 
                                  // This difference is resynchronized later.
368 
 
369 
  // After exiting the reset mode sending bus free
370 
  repeat (11) send_bit(1);
371 
 
372 
//  test_synchronization;       // test currently switched off
373 
//  test_empty_fifo_ext;        // test currently switched off
374 
//  test_full_fifo_ext;         // test currently switched off
375 
//  send_frame_ext;             // test currently switched off
376 
//  test_empty_fifo;            // test currently switched off
377 
  test_full_fifo;             // test currently switched on
378 
//  send_frame;                 // test currently switched off
379 
//  bus_off_test;               // test currently switched off
380 
//  forced_bus_off;             // test currently switched off
381 
//  send_frame_basic;           // test currently switched off
382 
//  send_frame_extended;        // test currently switched off
383 
//  self_reception_request;       // test currently switched off
384 
//  manual_frame_basic;         // test currently switched off
385 
//  manual_frame_ext;           // test currently switched off
386 
 
387 
  $display("CAN Testbench finished !");
388 
  $stop;
389 
end
390 
 
391 
 
392 
task forced_bus_off;    // Forcing bus-off by writinf to tx_err_cnt register
393 
  begin
394 
 
395 
    // Switch-on reset mode
396 
    write_register(8'd0, {7'h0, `CAN_MODE_RESET});
397 
 
398 
    // Set Clock Divider register
399 
    write_register(8'd31, {1'b1, 7'h0});    // Setting the extended mode (not normal)
400 
 
401 
    // Write 255 to tx_err_cnt register - Forcing bus-off
402 
    write_register(8'd15, 255);
403 
 
404 
    // Switch-off reset mode
405 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
406 
 
407 
//    #1000000;
408 
    #2500000;
409 
 
410 
 
411 
    // Switch-on reset mode
412 
    write_register(8'd0, {7'h0, `CAN_MODE_RESET});
413 
 
414 
    // Write 245 to tx_err_cnt register
415 
    write_register(8'd15, 245);
416 
 
417 
    // Switch-off reset mode
418 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
419 
 
420 
    #1000000;
421 
 
422 
 
423 
  end
424 
endtask   // forced_bus_off
425 
 
426 
 
427 
task manual_frame_basic;    // Testbench sends a basic format frame
428 
  begin
429 
 
430 
 
431 
    // Switch-on reset mode
432 
    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
433 
 
434 
    // Set Acceptance Code and Acceptance Mask registers
435 
    write_register(8'd4, 8'h28); // acceptance code
436 
    write_register(8'd5, 8'hff); // acceptance mask
437 
 
438 
    repeat (100) @ (posedge clk);
439 
 
440 
    // Switch-off reset mode
441 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
442 
 
443 
    // After exiting the reset mode sending bus free
444 
    repeat (11) send_bit(1);
445 
 
446 
 
447 
    write_register(8'd10, 8'h55); // Writing ID[10:3] = 0x55
448 
    write_register(8'd11, 8'h57); // Writing ID[2:0] = 0x2, rtr = 1, length = 7
449 
    write_register(8'd12, 8'h00); // data byte 1
450 
    write_register(8'd13, 8'h00); // data byte 2
451 
    write_register(8'd14, 8'h00); // data byte 3
452 
    write_register(8'd15, 8'h00); // data byte 4
453 
    write_register(8'd16, 8'h00); // data byte 5
454 
    write_register(8'd17, 8'h00); // data byte 6
455 
    write_register(8'd18, 8'h00); // data byte 7
456 
    write_register(8'd19, 8'h00); // data byte 8
457 
 
458 
    tx_bypassed = 1;    // When this signal is on, tx is not looped back to the rx.
459 
 
460 
    fork
461 
      begin
462 
//        tx_request_command;
463 
        self_reception_request_command;
464 
      end
465 
 
466 
      begin
467 
        #2200;
468 
 
469 
 
470 
        repeat (1)
471 
        begin
472 
          send_bit(0);  // SOF
473 
          send_bit(0);  // ID
474 
          send_bit(1);  // ID
475 
          send_bit(0);  // ID
476 
          send_bit(1);  // ID
477 
          send_bit(0);  // ID
478 
          send_bit(1);  // ID
479 
          send_bit(0);  // ID
480 
          send_bit(1);  // ID
481 
          send_bit(0);  // ID
482 
          send_bit(1);  // ID
483 
          send_bit(0);  // ID
484 
          send_bit(1);  // RTR
485 
          send_bit(0);  // IDE
486 
          send_bit(0);  // r0
487 
          send_bit(0);  // DLC
488 
          send_bit(1);  // DLC
489 
          send_bit(1);  // DLC
490 
          send_bit(1);  // DLC
491 
          send_bit(1);  // CRC
492 
          send_bit(1);  // CRC
493 
          send_bit(0);  // CRC stuff
494 
          send_bit(0);  // CRC 6
495 
          send_bit(0);  // CRC
496 
          send_bit(0);  // CRC
497 
          send_bit(0);  // CRC
498 
          send_bit(1);  // CRC  stuff
499 
          send_bit(0);  // CRC 0
500 
          send_bit(0);  // CRC
501 
          send_bit(1);  // CRC
502 
          send_bit(0);  // CRC
503 
          send_bit(1);  // CRC 5
504 
          send_bit(1);  // CRC
505 
          send_bit(0);  // CRC
506 
          send_bit(1);  // CRC
507 
          send_bit(1);  // CRC b
508 
          send_bit(1);  // CRC DELIM
509 
          send_bit(0);  // ACK
510 
          send_bit(1);  // ACK DELIM
511 
          send_bit(1);  // EOF
512 
          send_bit(1);  // EOF
513 
          send_bit(1);  // EOF
514 
          send_bit(1);  // EOF
515 
          send_bit(1);  // EOF
516 
          send_bit(1);  // EOF
517 
          send_bit(1);  // EOF
518 
          send_bit(1);  // INTER
519 
          send_bit(1);  // INTER
520 
          send_bit(1);  // INTER
521 
        end // repeat
522 
 
523 
 
524 
 
525 
      end
526 
 
527 
 
528 
    join
529 
 
530 
 
531 
 
532 
    read_receive_buffer;
533 
    release_rx_buffer_command;
534 
 
535 
    read_receive_buffer;
536 
    release_rx_buffer_command;
537 
    read_receive_buffer;
538 
 
539 
    #4000000;
540 
 
541 
  end
542 
endtask   //  manual_frame_basic
543 
 
544 
 
545 
 
546 
task manual_frame_ext;    // Testbench sends an extended format frame
547 
  begin
548 
 
549 
 
550 
    // Switch-on reset mode
551 
    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
552 
 
553 
    // Set Clock Divider register
554 
    extended_mode = 1'b1;
555 
    write_register(8'd31, {extended_mode, 7'h0});    // Setting the extended mode
556 
 
557 
    // Set Acceptance Code and Acceptance Mask registers
558 
    write_register(8'd16, 8'ha6); // acceptance code 0
559 
    write_register(8'd17, 8'h00); // acceptance code 1
560 
    write_register(8'd18, 8'h5a); // acceptance code 2
561 
    write_register(8'd19, 8'hac); // acceptance code 3
562 
    write_register(8'd20, 8'h00); // acceptance mask 0
563 
    write_register(8'd21, 8'h00); // acceptance mask 1
564 
    write_register(8'd22, 8'h00); // acceptance mask 2
565 
    write_register(8'd23, 8'h00); // acceptance mask 3
566 
 
567 
    repeat (100) @ (posedge clk);
568 
 
569 
    // Switch-off reset mode
570 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
571 
 
572 
    // After exiting the reset mode sending bus free
573 
    repeat (11) send_bit(1);
574 
 
575 
 
576 
    // Extended frame format
577 
    // Writing TX frame information + identifier + data
578 
    write_register(8'd16, 8'hc5);   // Frame format = 1, Remote transmision request = 1, DLC = 5
579 
    write_register(8'd17, 8'ha6);   // ID[28:21] = a6
580 
    write_register(8'd18, 8'h00);   // ID[20:13] = 00
581 
    write_register(8'd19, 8'h5a);   // ID[12:5]  = 5a
582 
    write_register(8'd20, 8'ha8);   // ID[4:0]   = 15
583 
    // write_register(8'd21, 8'h78); RTR does not send any data
584 
    // write_register(8'd22, 8'h9a);
585 
    // write_register(8'd23, 8'hbc);
586 
    // write_register(8'd24, 8'hde);
587 
    // write_register(8'd25, 8'hf0);
588 
    // write_register(8'd26, 8'h0f);
589 
    // write_register(8'd27, 8'hed);
590 
    // write_register(8'd28, 8'hcb);
591 
 
592 
 
593 
    // Enabling IRQ's (extended mode)
594 
    write_register(8'd4, 8'hff);
595 
 
596 
    // tx_bypassed = 1;    // When this signal is on, tx is not looped back to the rx.
597 
 
598 
    fork
599 
      begin
600 
        tx_request_command;
601 
//        self_reception_request_command;
602 
      end
603 
 
604 
      begin
605 
        #2400;
606 
 
607 
        repeat (1)
608 
        begin
609 
          send_bit(0);  // SOF
610 
          send_bit(1);  // ID
611 
          send_bit(0);  // ID
612 
          send_bit(1);  // ID
613 
          send_bit(0);  // ID a
614 
          send_bit(0);  // ID
615 
          send_bit(1);  // ID
616 
          send_bit(1);  // ID
617 
          send_bit(0);  // ID 6
618 
          send_bit(0);  // ID
619 
          send_bit(0);  // ID
620 
          send_bit(0);  // ID
621 
          send_bit(1);  // RTR
622 
          send_bit(1);  // IDE
623 
          send_bit(0);  // ID 0
624 
          send_bit(0);  // ID
625 
          send_bit(0);  // ID
626 
          send_bit(0);  // ID
627 
          send_bit(0);  // ID 0
628 
          send_bit(1);  // ID stuff
629 
          send_bit(0);  // ID
630 
          send_bit(1);  // ID
631 
          send_bit(0);  // ID
632 
          send_bit(1);  // ID 6
633 
          send_bit(1);  // ID
634 
          send_bit(0);  // ID
635 
          send_bit(1);  // ID
636 
          send_bit(0);  // ID a
637 
          send_bit(1);  // ID 1
638 
          send_bit(0);  // ID
639 
          send_bit(1);  // ID
640 
          send_bit(0);  // ID
641 
          send_bit(1);  // ID 5
642 
          send_bit(1);  // RTR
643 
          send_bit(0);  // r1
644 
          send_bit(0);  // r0
645 
          send_bit(0);  // DLC
646 
          send_bit(1);  // DLC
647 
          send_bit(0);  // DLC
648 
          send_bit(1);  // DLC
649 
          send_bit(1);  // CRC
650 
          send_bit(0);  // CRC
651 
          send_bit(0);  // CRC 4
652 
          send_bit(1);  // CRC
653 
          send_bit(1);  // CRC
654 
          send_bit(0);  // CRC
655 
          send_bit(1);  // CRC d
656 
          send_bit(0);  // CRC
657 
          send_bit(0);  // CRC
658 
          send_bit(1);  // CRC
659 
          send_bit(1);  // CRC 3
660 
          send_bit(1);  // CRC
661 
          send_bit(0);  // CRC
662 
          send_bit(0);  // CRC
663 
          send_bit(1);  // CRC 9
664 
          send_bit(1);  // CRC DELIM
665 
          send_bit(0);  // ACK
666 
          send_bit(1);  // ACK DELIM
667 
          send_bit(1);  // EOF
668 
          send_bit(1);  // EOF
669 
          send_bit(1);  // EOF
670 
          send_bit(1);  // EOF
671 
          send_bit(1);  // EOF
672 
          send_bit(1);  // EOF
673 
          send_bit(1);  // EOF
674 
          send_bit(1);  // INTER
675 
          send_bit(1);  // INTER
676 
          send_bit(1);  // INTER
677 
        end // repeat
678 
 
679 
 
680 
      end
681 
 
682 
    join
683 
 
684 
 
685 
 
686 
    read_receive_buffer;
687 
    release_rx_buffer_command;
688 
 
689 
    read_receive_buffer;
690 
    release_rx_buffer_command;
691 
    read_receive_buffer;
692 
 
693 
    // Read irq register
694 
    #1 read_register(8'd3);
695 
 
696 
    // Read error code capture register
697 
    read_register(8'd12);
698 
 
699 
    // Read error capture code register
700 
//    read_register(8'd12);
701 
 
702 
    #4000000;
703 
 
704 
  end
705 
endtask   //  manual_frame_ext
706 
 
707 
 
708 
 
709 
task bus_off_test;    // Testbench sends a frame
710 
  begin
711 
 
712 
    write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8
713 
    write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7
714 
    write_register(8'd12, 8'h00); // data byte 1
715 
    write_register(8'd13, 8'h00); // data byte 2
716 
    write_register(8'd14, 8'h00); // data byte 3
717 
    write_register(8'd15, 8'h00); // data byte 4
718 
    write_register(8'd16, 8'h00); // data byte 5
719 
    write_register(8'd17, 8'h00); // data byte 6
720 
    write_register(8'd18, 8'h00); // data byte 7
721 
    write_register(8'd19, 8'h00); // data byte 8
722 
 
723 
    fork
724 
      begin
725 
        tx_request_command;
726 
      end
727 
 
728 
      begin
729 
        #2000;
730 
 
731 
        repeat (16)
732 
        begin
733 
          send_bit(0);  // SOF
734 
          send_bit(1);  // ID
735 
          send_bit(1);  // ID
736 
          send_bit(1);  // ID
737 
          send_bit(0);  // ID
738 
          send_bit(1);  // ID
739 
          send_bit(0);  // ID
740 
          send_bit(0);  // ID
741 
          send_bit(0);  // ID
742 
          send_bit(1);  // ID
743 
          send_bit(0);  // ID
744 
          send_bit(1);  // ID
745 
          send_bit(1);  // RTR
746 
          send_bit(0);  // IDE
747 
          send_bit(0);  // r0
748 
          send_bit(0);  // DLC
749 
          send_bit(1);  // DLC
750 
          send_bit(1);  // DLC
751 
          send_bit(1);  // DLC
752 
          send_bit(1);  // CRC
753 
          send_bit(0);  // CRC
754 
          send_bit(0);  // CRC
755 
          send_bit(1);  // CRC
756 
          send_bit(1);  // CRC
757 
          send_bit(1);  // CRC
758 
          send_bit(0);  // CRC
759 
          send_bit(1);  // CRC
760 
          send_bit(0);  // CRC
761 
          send_bit(0);  // CRC
762 
          send_bit(1);  // CRC
763 
          send_bit(1);  // CRC
764 
          send_bit(1);  // CRC
765 
          send_bit(1);  // CRC
766 
          send_bit(1);  // CRC
767 
          send_bit(1);  // CRC DELIM
768 
          send_bit(1);  // ACK            ack error
769 
          send_bit(0);  // ERROR
770 
          send_bit(0);  // ERROR
771 
          send_bit(0);  // ERROR
772 
          send_bit(0);  // ERROR
773 
          send_bit(0);  // ERROR
774 
          send_bit(0);  // ERROR
775 
          send_bit(1);  // ERROR DELIM
776 
          send_bit(1);  // ERROR DELIM
777 
          send_bit(1);  // ERROR DELIM
778 
          send_bit(1);  // ERROR DELIM
779 
          send_bit(1);  // ERROR DELIM
780 
          send_bit(1);  // ERROR DELIM
781 
          send_bit(1);  // ERROR DELIM
782 
          send_bit(1);  // ERROR DELIM
783 
          send_bit(1);  // INTER
784 
          send_bit(1);  // INTER
785 
          send_bit(1);  // INTER
786 
        end // repeat
787 
 
788 
        // Node is error passive now.
789 
 
790 
        // Read irq register (error interrupt should be cleared now.
791 
        read_register(8'd3);
792 
 
793 
        repeat (20)
794 
 
795 
        begin
796 
          send_bit(0);  // SOF
797 
          send_bit(1);  // ID
798 
          send_bit(1);  // ID
799 
          send_bit(1);  // ID
800 
          send_bit(0);  // ID
801 
          send_bit(1);  // ID
802 
          send_bit(0);  // ID
803 
          send_bit(0);  // ID
804 
          send_bit(0);  // ID
805 
          send_bit(1);  // ID
806 
          send_bit(0);  // ID
807 
          send_bit(1);  // ID
808 
          send_bit(1);  // RTR
809 
          send_bit(0);  // IDE
810 
          send_bit(0);  // r0
811 
          send_bit(0);  // DLC
812 
          send_bit(1);  // DLC
813 
          send_bit(1);  // DLC
814 
          send_bit(1);  // DLC
815 
          send_bit(1);  // CRC
816 
          send_bit(0);  // CRC
817 
          send_bit(0);  // CRC
818 
          send_bit(1);  // CRC
819 
          send_bit(1);  // CRC
820 
          send_bit(1);  // CRC
821 
          send_bit(0);  // CRC
822 
          send_bit(1);  // CRC
823 
          send_bit(0);  // CRC
824 
          send_bit(0);  // CRC
825 
          send_bit(1);  // CRC
826 
          send_bit(1);  // CRC
827 
          send_bit(1);  // CRC
828 
          send_bit(1);  // CRC
829 
          send_bit(1);  // CRC
830 
          send_bit(1);  // CRC DELIM
831 
          send_bit(1);  // ACK            ack error
832 
          send_bit(0);  // ERROR
833 
          send_bit(0);  // ERROR
834 
          send_bit(0);  // ERROR
835 
          send_bit(0);  // ERROR
836 
          send_bit(0);  // ERROR
837 
          send_bit(0);  // ERROR
838 
          send_bit(1);  // ERROR DELIM
839 
          send_bit(1);  // ERROR DELIM
840 
          send_bit(1);  // ERROR DELIM
841 
          send_bit(1);  // ERROR DELIM
842 
          send_bit(1);  // ERROR DELIM
843 
          send_bit(1);  // ERROR DELIM
844 
          send_bit(1);  // ERROR DELIM
845 
          send_bit(1);  // ERROR DELIM
846 
          send_bit(1);  // INTER
847 
          send_bit(1);  // INTER
848 
          send_bit(1);  // INTER
849 
          send_bit(1);  // SUSPEND
850 
          send_bit(1);  // SUSPEND
851 
          send_bit(1);  // SUSPEND
852 
          send_bit(1);  // SUSPEND
853 
          send_bit(1);  // SUSPEND
854 
          send_bit(1);  // SUSPEND
855 
          send_bit(1);  // SUSPEND
856 
          send_bit(1);  // SUSPEND
857 
        end // repeat
858 
 
859 
        // Node is bus-off now
860 
 
861 
 
862 
        // Read irq register (error interrupt should be cleared now.
863 
        read_register(8'd3);
864 
 
865 
 
866 
 
867 
        #100000;
868 
 
869 
        // Switch-off reset mode
870 
        write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
871 
 
872 
        repeat (64 * 11)
873 
        begin
874 
          send_bit(1);
875 
        end // repeat
876 
 
877 
        // Read irq register (error interrupt should be cleared now.
878 
        read_register(8'd3);
879 
 
880 
        repeat (64 * 11)
881 
        begin
882 
          send_bit(1);
883 
        end // repeat
884 
 
885 
 
886 
 
887 
        // Read irq register (error interrupt should be cleared now.
888 
        read_register(8'd3);
889 
 
890 
      end
891 
 
892 
 
893 
 
894 
    join
895 
 
896 
 
897 
 
898 
    fork
899 
      begin
900 
        tx_request_command;
901 
      end
902 
 
903 
      begin
904 
        #1100;
905 
 
906 
        send_bit(1);    // To spend some time before transmitter is ready.
907 
 
908 
        repeat (1)
909 
        begin
910 
          send_bit(0);  // SOF
911 
          send_bit(1);  // ID
912 
          send_bit(1);  // ID
913 
          send_bit(1);  // ID
914 
          send_bit(0);  // ID
915 
          send_bit(1);  // ID
916 
          send_bit(0);  // ID
917 
          send_bit(0);  // ID
918 
          send_bit(0);  // ID
919 
          send_bit(1);  // ID
920 
          send_bit(0);  // ID
921 
          send_bit(1);  // ID
922 
          send_bit(1);  // RTR
923 
          send_bit(0);  // IDE
924 
          send_bit(0);  // r0
925 
          send_bit(0);  // DLC
926 
          send_bit(1);  // DLC
927 
          send_bit(1);  // DLC
928 
          send_bit(1);  // DLC
929 
          send_bit(1);  // CRC
930 
          send_bit(0);  // CRC
931 
          send_bit(0);  // CRC
932 
          send_bit(1);  // CRC
933 
          send_bit(1);  // CRC
934 
          send_bit(1);  // CRC
935 
          send_bit(0);  // CRC
936 
          send_bit(1);  // CRC
937 
          send_bit(0);  // CRC
938 
          send_bit(0);  // CRC
939 
          send_bit(1);  // CRC
940 
          send_bit(1);  // CRC
941 
          send_bit(1);  // CRC
942 
          send_bit(1);  // CRC
943 
          send_bit(1);  // CRC
944 
          send_bit(1);  // CRC DELIM
945 
          send_bit(0);  // ACK
946 
          send_bit(1);  // ACK DELIM
947 
          send_bit(1);  // EOF
948 
          send_bit(1);  // EOF
949 
          send_bit(1);  // EOF
950 
          send_bit(1);  // EOF
951 
          send_bit(1);  // EOF
952 
          send_bit(1);  // EOF
953 
          send_bit(1);  // EOF
954 
          send_bit(1);  // INTER
955 
          send_bit(1);  // INTER
956 
          send_bit(1);  // INTER
957 
        end // repeat
958 
      end
959 
 
960 
    join
961 
 
962 
    read_receive_buffer;
963 
    release_rx_buffer_command;
964 
    read_receive_buffer;
965 
    release_rx_buffer_command;
966 
    read_receive_buffer;
967 
 
968 
    #4000000;
969 
 
970 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
971 
 
972 
    #1000000;
973 
 
974 
  end
975 
endtask   // bus_off_test
976 
 
977 
 
978 
 
979 
task send_frame_basic;    // CAN IP core sends frames
980 
  begin
981 
 
982 
    write_register(8'd10, 8'hea); // Writing ID[10:3] = 0xea
983 
    write_register(8'd11, 8'h28); // Writing ID[2:0] = 0x1, rtr = 0, length = 8
984 
    write_register(8'd12, 8'h56); // data byte 1
985 
    write_register(8'd13, 8'h78); // data byte 2
986 
    write_register(8'd14, 8'h9a); // data byte 3
987 
    write_register(8'd15, 8'hbc); // data byte 4
988 
    write_register(8'd16, 8'hde); // data byte 5
989 
    write_register(8'd17, 8'hf0); // data byte 6
990 
    write_register(8'd18, 8'h0f); // data byte 7
991 
    write_register(8'd19, 8'hed); // data byte 8
992 
 
993 
 
994 
    // Enable irqs (basic mode)
995 
    write_register(8'd0, 8'h1e);
996 
 
997 
 
998 
 
999 
    fork
1000 
 
1001 
      begin
1002 
        #1500;
1003 
        $display("\n\nStart receiving data from CAN bus");
1004 
        receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
1005 
        receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
1006 
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc
1007 
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc
1008 
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc
1009 
      end
1010 
 
1011 
      begin
1012 
        tx_request_command;
1013 
      end
1014 
 
1015 
      begin
1016 
        // Transmitting acknowledge
1017 
        wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
1018 
        #1 rx = 0;
1019 
        wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim);
1020 
        #1 rx = 1;
1021 
      end
1022 
 
1023 
 
1024 
    join
1025 
 
1026 
    read_receive_buffer;
1027 
    release_rx_buffer_command;
1028 
    release_rx_buffer_command;
1029 
    read_receive_buffer;
1030 
    release_rx_buffer_command;
1031 
    read_receive_buffer;
1032 
    release_rx_buffer_command;
1033 
    read_receive_buffer;
1034 
    release_rx_buffer_command;
1035 
    read_receive_buffer;
1036 
 
1037 
    #200000;
1038 
 
1039 
    read_receive_buffer;
1040 
 
1041 
    // Read irq register
1042 
    read_register(8'd3);
1043 
    #1000;
1044 
 
1045 
  end
1046 
endtask   // send_frame_basic
1047 
 
1048 
 
1049 
 
1050 
task send_frame_extended;    // CAN IP core sends basic or extended frames in extended mode
1051 
  begin
1052 
 
1053 
    // Switch-on reset mode
1054 
    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
1055 
 
1056 
    // Set Clock Divider register
1057 
    extended_mode = 1'b1;
1058 
    write_register(8'd31, {extended_mode, 7'h0});    // Setting the extended mode
1059 
 
1060 
    // Set Acceptance Code and Acceptance Mask registers
1061 
    write_register(8'd16, 8'ha6); // acceptance code 0
1062 
    write_register(8'd17, 8'hb0); // acceptance code 1
1063 
    write_register(8'd18, 8'h12); // acceptance code 2
1064 
    write_register(8'd19, 8'h30); // acceptance code 3
1065 
    write_register(8'd20, 8'h00); // acceptance mask 0
1066 
    write_register(8'd21, 8'h00); // acceptance mask 1
1067 
    write_register(8'd22, 8'h00); // acceptance mask 2
1068 
    write_register(8'd23, 8'h00); // acceptance mask 3
1069 
 
1070 
    // Switch-off reset mode
1071 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
1072 
 
1073 
    // After exiting the reset mode sending bus free
1074 
    repeat (11) send_bit(1);
1075 
 
1076 
 
1077 
/*  Basic frame format
1078 
    // Writing TX frame information + identifier + data
1079 
    write_register(8'd16, 8'h45);   // Frame format = 0, Remote transmision request = 1, DLC = 5
1080 
    write_register(8'd17, 8'ha6);   // ID[28:21] = a6
1081 
    write_register(8'd18, 8'ha0);   // ID[20:18] = 5
1082 
    // write_register(8'd19, 8'h78); RTR does not send any data
1083 
    // write_register(8'd20, 8'h9a);
1084 
    // write_register(8'd21, 8'hbc);
1085 
    // write_register(8'd22, 8'hde);
1086 
    // write_register(8'd23, 8'hf0);
1087 
    // write_register(8'd24, 8'h0f);
1088 
    // write_register(8'd25, 8'hed);
1089 
    // write_register(8'd26, 8'hcb);
1090 
    // write_register(8'd27, 8'ha9);
1091 
    // write_register(8'd28, 8'h87);
1092 
*/
1093 
 
1094 
    // Extended frame format
1095 
    // Writing TX frame information + identifier + data
1096 
    write_register(8'd16, 8'hc5);   // Frame format = 1, Remote transmision request = 1, DLC = 5
1097 
    write_register(8'd17, 8'ha6);   // ID[28:21] = a6
1098 
    write_register(8'd18, 8'h00);   // ID[20:13] = 00
1099 
    write_register(8'd19, 8'h5a);   // ID[12:5]  = 5a
1100 
    write_register(8'd20, 8'ha8);   // ID[4:0]   = 15
1101 
    // write_register(8'd21, 8'h78); RTR does not send any data
1102 
    // write_register(8'd22, 8'h9a);
1103 
    // write_register(8'd23, 8'hbc);
1104 
    // write_register(8'd24, 8'hde);
1105 
    // write_register(8'd25, 8'hf0);
1106 
    // write_register(8'd26, 8'h0f);
1107 
    // write_register(8'd27, 8'hed);
1108 
    // write_register(8'd28, 8'hcb);
1109 
 
1110 
 
1111 
    // Enabling IRQ's (extended mode)
1112 
    write_register(8'd4, 8'hff);
1113 
 
1114 
 
1115 
    fork
1116 
      begin
1117 
        #2700;
1118 
        $display("\n\nStart receiving data from CAN bus");
1119 
        /* Standard frame format
1120 
        receive_frame(0, 0, {26'h00000a0, 3'h1}, 4'h1, 15'h2d9c); // mode, rtr, id, length, crc
1121 
        receive_frame(0, 0, {26'h00000a0, 3'h1}, 4'h2, 15'h46b4); // mode, rtr, id, length, crc
1122 
        receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h0, 15'h42cd); // mode, rtr, id, length, crc
1123 
        receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h1, 15'h555f); // mode, rtr, id, length, crc
1124 
        receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h2, 15'h6742); // mode, rtr, id, length, crc
1125 
        */
1126 
 
1127 
        // Extended frame format
1128 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h1, 15'h2d22); // mode, rtr, id, length, crc
1129 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h2, 15'h3d2d); // mode, rtr, id, length, crc
1130 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h0, 15'h23aa); // mode, rtr, id, length, crc
1131 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h1, 15'h2d22); // mode, rtr, id, length, crc
1132 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h2, 15'h3d2d); // mode, rtr, id, length, crc
1133 
 
1134 
      end
1135 
 
1136 
      begin
1137 
        tx_request_command;
1138 
      end
1139 
 
1140 
      begin
1141 
        // Transmitting acknowledge
1142 
        wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
1143 
        #1 rx = 0;
1144 
        wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim);
1145 
        #1 rx = 1;
1146 
      end
1147 
 
1148 
      begin   // Reading irq and arbitration lost capture register
1149 
 
1150 
        repeat(1)
1151 
          begin
1152 
            while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
1153 
              begin
1154 
                @ (posedge clk);
1155 
              end
1156 
 
1157 
            // Read irq register
1158 
            #1 read_register(8'd3);
1159 
 
1160 
            // Read arbitration lost capture register
1161 
            read_register(8'd11);
1162 
          end
1163 
 
1164 
 
1165 
        repeat(1)
1166 
          begin
1167 
            while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
1168 
              begin
1169 
                @ (posedge clk);
1170 
              end
1171 
 
1172 
            // Read irq register
1173 
            #1 read_register(8'd3);
1174 
          end
1175 
 
1176 
        repeat(1)
1177 
          begin
1178 
            while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
1179 
              begin
1180 
                @ (posedge clk);
1181 
              end
1182 
 
1183 
            // Read arbitration lost capture register
1184 
            read_register(8'd11);
1185 
          end
1186 
 
1187 
      end
1188 
 
1189 
    join
1190 
 
1191 
    read_receive_buffer;
1192 
    release_rx_buffer_command;
1193 
    release_rx_buffer_command;
1194 
    read_receive_buffer;
1195 
    release_rx_buffer_command;
1196 
    read_receive_buffer;
1197 
    release_rx_buffer_command;
1198 
    read_receive_buffer;
1199 
    release_rx_buffer_command;
1200 
    read_receive_buffer;
1201 
 
1202 
    #200000;
1203 
 
1204 
    read_receive_buffer;
1205 
 
1206 
    // Read irq register
1207 
    read_register(8'd3);
1208 
    #1000;
1209 
 
1210 
  end
1211 
endtask   // send_frame_extended
1212 
 
1213 
 
1214 
 
1215 
task self_reception_request;    // CAN IP core sends sets self reception mode and transmits a msg. This test runs in EXTENDED mode
1216 
  begin
1217 
 
1218 
    // Switch-on reset mode
1219 
    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
1220 
 
1221 
    // Set Clock Divider register
1222 
    extended_mode = 1'b1;
1223 
    write_register(8'd31, {extended_mode, 7'h0});    // Setting the extended mode
1224 
 
1225 
    // Set Acceptance Code and Acceptance Mask registers
1226 
    write_register(8'd16, 8'ha6); // acceptance code 0
1227 
    write_register(8'd17, 8'hb0); // acceptance code 1
1228 
    write_register(8'd18, 8'h12); // acceptance code 2
1229 
    write_register(8'd19, 8'h30); // acceptance code 3
1230 
    write_register(8'd20, 8'h00); // acceptance mask 0
1231 
    write_register(8'd21, 8'h00); // acceptance mask 1
1232 
    write_register(8'd22, 8'h00); // acceptance mask 2
1233 
    write_register(8'd23, 8'h00); // acceptance mask 3
1234 
 
1235 
    // Setting the "self test mode"
1236 
    write_register(8'd0, 8'h4);
1237 
 
1238 
    // Switch-off reset mode
1239 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
1240 
 
1241 
    // After exiting the reset mode sending bus free
1242 
    repeat (11) send_bit(1);
1243 
 
1244 
 
1245 
    // Writing TX frame information + identifier + data
1246 
    write_register(8'd16, 8'h45);   // Frame format = 0, Remote transmision request = 1, DLC = 5
1247 
    write_register(8'd17, 8'ha6);   // ID[28:21] = a6
1248 
    write_register(8'd18, 8'ha0);   // ID[20:18] = 5
1249 
    // write_register(8'd19, 8'h78); RTR does not send any data
1250 
    // write_register(8'd20, 8'h9a);
1251 
    // write_register(8'd21, 8'hbc);
1252 
    // write_register(8'd22, 8'hde);
1253 
    // write_register(8'd23, 8'hf0);
1254 
    // write_register(8'd24, 8'h0f);
1255 
    // write_register(8'd25, 8'hed);
1256 
    // write_register(8'd26, 8'hcb);
1257 
    // write_register(8'd27, 8'ha9);
1258 
    // write_register(8'd28, 8'h87);
1259 
 
1260 
 
1261 
    // Enabling IRQ's (extended mode)
1262 
    write_register(8'd4, 8'hff);
1263 
 
1264 
    self_reception_request_command;
1265 
 
1266 
    #400000;
1267 
 
1268 
    read_receive_buffer;
1269 
    release_rx_buffer_command;
1270 
    release_rx_buffer_command;
1271 
    read_receive_buffer;
1272 
    release_rx_buffer_command;
1273 
    read_receive_buffer;
1274 
    release_rx_buffer_command;
1275 
    read_receive_buffer;
1276 
    release_rx_buffer_command;
1277 
    read_receive_buffer;
1278 
 
1279 
 
1280 
    read_receive_buffer;
1281 
 
1282 
    // Read irq register
1283 
    read_register(8'd3);
1284 
    #1000;
1285 
 
1286 
  end
1287 
endtask   // self_reception_request
1288 
 
1289 
 
1290 
 
1291 
task test_empty_fifo;
1292 
  begin
1293 
 
1294 
    // Enable irqs (basic mode)
1295 
    write_register(8'd0, 8'h1e);
1296 
 
1297 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h3, 15'h56a9); // mode, rtr, id, length, crc
1298 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h7, 15'h391d); // mode, rtr, id, length, crc
1299 
 
1300 
    read_receive_buffer;
1301 
    fifo_info;
1302 
 
1303 
    release_rx_buffer_command;
1304 
    $display("\n\n");
1305 
    read_receive_buffer;
1306 
    fifo_info;
1307 
 
1308 
    release_rx_buffer_command;
1309 
    $display("\n\n");
1310 
    read_receive_buffer;
1311 
    fifo_info;
1312 
 
1313 
    release_rx_buffer_command;
1314 
    $display("\n\n");
1315 
    read_receive_buffer;
1316 
    fifo_info;
1317 
 
1318 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1319 
 
1320 
    $display("\n\n");
1321 
    read_receive_buffer;
1322 
    fifo_info;
1323 
 
1324 
    release_rx_buffer_command;
1325 
    $display("\n\n");
1326 
    read_receive_buffer;
1327 
    fifo_info;
1328 
 
1329 
    release_rx_buffer_command;
1330 
    $display("\n\n");
1331 
    read_receive_buffer;
1332 
    fifo_info;
1333 
  end
1334 
endtask
1335 
 
1336 
 
1337 
 
1338 
task test_empty_fifo_ext;
1339 
  begin
1340 
    receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
1341 
    receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
1342 
 
1343 
    read_receive_buffer;
1344 
    fifo_info;
1345 
 
1346 
    release_rx_buffer_command;
1347 
    $display("\n\n");
1348 
    read_receive_buffer;
1349 
    fifo_info;
1350 
 
1351 
    release_rx_buffer_command;
1352 
    $display("\n\n");
1353 
    read_receive_buffer;
1354 
    fifo_info;
1355 
 
1356 
    release_rx_buffer_command;
1357 
    $display("\n\n");
1358 
    read_receive_buffer;
1359 
    fifo_info;
1360 
 
1361 
    receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
1362 
 
1363 
    $display("\n\n");
1364 
    read_receive_buffer;
1365 
    fifo_info;
1366 
 
1367 
    release_rx_buffer_command;
1368 
    $display("\n\n");
1369 
    read_receive_buffer;
1370 
    fifo_info;
1371 
 
1372 
    release_rx_buffer_command;
1373 
    $display("\n\n");
1374 
    read_receive_buffer;
1375 
    fifo_info;
1376 
  end
1377 
endtask
1378 
 
1379 
 
1380 
 
1381 
task test_full_fifo;
1382 
  begin
1383 
 
1384 
    // Enable irqs (basic mode)
1385 
    write_register(8'd0, 8'h1e);
1386 
 
1387 
    $display("\n\n");
1388 
 
1389 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
1390 
    fifo_info;
1391 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
1392 
    fifo_info;
1393 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
1394 
    fifo_info;
1395 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h3, 15'h56a9); // mode, rtr, id, length, crc
1396 
    fifo_info;
1397 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h4, 15'h3124); // mode, rtr, id, length, crc
1398 
    fifo_info;
1399 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h5, 15'h6944); // mode, rtr, id, length, crc
1400 
    fifo_info;
1401 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h6, 15'h5182); // mode, rtr, id, length, crc
1402 
    fifo_info;
1403 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h7, 15'h391d); // mode, rtr, id, length, crc
1404 
    fifo_info;
1405 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1406 
    fifo_info;
1407 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1408 
    fifo_info;
1409 
    $display("FIFO should be full now");
1410 
 
1411 
    // Following one is accepted with overrun
1412 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1413 
    fifo_info;
1414 
 
1415 
    release_rx_buffer_command;
1416 
    fifo_info;
1417 
 
1418 
    // Space just enough for the following frame.
1419 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
1420 
    fifo_info;
1421 
 
1422 
    // Following accepted with overrun
1423 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1424 
    fifo_info;
1425 
//    read_overrun_info(0, 15);
1426 
 
1427 
    release_rx_buffer_command;
1428 
    release_rx_buffer_command;
1429 
 
1430 
    release_rx_buffer_command;
1431 
    read_receive_buffer;
1432 
    fifo_info;
1433 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1434 
    fifo_info;
1435 
//    read_overrun_info(0, 15);
1436 
    $display("\n\n");
1437 
 
1438 
    release_rx_buffer_command;
1439 
    read_receive_buffer;
1440 
    fifo_info;
1441 
 
1442 
    release_rx_buffer_command;
1443 
    read_receive_buffer;
1444 
    fifo_info;
1445 
 
1446 
    release_rx_buffer_command;
1447 
    read_receive_buffer;
1448 
    fifo_info;
1449 
 
1450 
    release_rx_buffer_command;
1451 
    read_receive_buffer;
1452 
    fifo_info;
1453 
 
1454 
    release_rx_buffer_command;
1455 
    read_receive_buffer;
1456 
    fifo_info;
1457 
 
1458 
    release_rx_buffer_command;
1459 
    read_receive_buffer;
1460 
    fifo_info;
1461 
 
1462 
    clear_data_overrun_command;
1463 
 
1464 
    release_rx_buffer_command;
1465 
    read_receive_buffer;
1466 
    fifo_info;
1467 
 
1468 
    release_rx_buffer_command;
1469 
    read_receive_buffer;
1470 
    fifo_info;
1471 
 
1472 
    clear_data_overrun_command;
1473 
 
1474 
    release_rx_buffer_command;
1475 
    read_receive_buffer;
1476 
    fifo_info;
1477 
 
1478 
    release_rx_buffer_command;
1479 
    read_receive_buffer;
1480 
    fifo_info;
1481 
 
1482 
    release_rx_buffer_command;
1483 
    read_receive_buffer;
1484 
    fifo_info;
1485 
 
1486 
    release_rx_buffer_command;
1487 
    read_receive_buffer;
1488 
    fifo_info;
1489 
 
1490 
    release_rx_buffer_command;
1491 
    read_receive_buffer;
1492 
    fifo_info;
1493 
 
1494 
    // Read irq register
1495 
    read_register(8'd3);
1496 
 
1497 
    // Read irq register
1498 
    read_register(8'd3);
1499 
    #1000;
1500 
 
1501 
  end
1502 
endtask
1503 
 
1504 
 
1505 
 
1506 
task test_full_fifo_ext;
1507 
  begin
1508 
    release_rx_buffer_command;
1509 
    $display("\n\n");
1510 
    read_receive_buffer;
1511 
    fifo_info;
1512 
 
1513 
    receive_frame(1, 0, 29'h14d60246, 4'h0, 15'h6f54); // mode, rtr, id, length, crc
1514 
    read_receive_buffer;
1515 
    fifo_info;
1516 
    receive_frame(1, 0, 29'h14d60246, 4'h1, 15'h6d38); // mode, rtr, id, length, crc
1517 
    read_receive_buffer;
1518 
    fifo_info;
1519 
    receive_frame(1, 0, 29'h14d60246, 4'h2, 15'h053e); // mode, rtr, id, length, crc
1520 
    fifo_info;
1521 
    read_receive_buffer;
1522 
    receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
1523 
    fifo_info;
1524 
    receive_frame(1, 0, 29'h14d60246, 4'h4, 15'h4bba); // mode, rtr, id, length, crc
1525 
    fifo_info;
1526 
    receive_frame(1, 0, 29'h14d60246, 4'h5, 15'h4d7d); // mode, rtr, id, length, crc
1527 
    fifo_info;
1528 
    receive_frame(1, 0, 29'h14d60246, 4'h6, 15'h6f40); // mode, rtr, id, length, crc
1529 
    fifo_info;
1530 
    receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
1531 
    fifo_info;
1532 
//    read_overrun_info(0, 10);
1533 
 
1534 
    release_rx_buffer_command;
1535 
    release_rx_buffer_command;
1536 
    fifo_info;
1537 
    receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
1538 
    fifo_info;
1539 
//    read_overrun_info(0, 15);
1540 
    $display("\n\n");
1541 
 
1542 
    release_rx_buffer_command;
1543 
    read_receive_buffer;
1544 
    fifo_info;
1545 
 
1546 
    release_rx_buffer_command;
1547 
    read_receive_buffer;
1548 
    fifo_info;
1549 
 
1550 
    release_rx_buffer_command;
1551 
    read_receive_buffer;
1552 
    fifo_info;
1553 
 
1554 
    release_rx_buffer_command;
1555 
    read_receive_buffer;
1556 
    fifo_info;
1557 
 
1558 
    release_rx_buffer_command;
1559 
    read_receive_buffer;
1560 
    fifo_info;
1561 
 
1562 
    release_rx_buffer_command;
1563 
    read_receive_buffer;
1564 
    fifo_info;
1565 
 
1566 
    release_rx_buffer_command;
1567 
    read_receive_buffer;
1568 
    fifo_info;
1569 
 
1570 
  end
1571 
endtask
1572 
 
1573 
 
1574 
/*
1575 
task initialize_fifo;
1576 
  integer i;
1577 
  begin
1578 
    for (i=0; i<32; i=i+1)
1579 
      begin
1580 
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i] = 0;
1581 
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i] = 0;
1582 
      end
1583 
 
1584 
    for (i=0; i<64; i=i+1)
1585 
      begin
1586 
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo[i] = 0;
1587 
      end
1588 
 
1589 
    $display("(%0t) Fifo initialized", $time);
1590 
  end
1591 
endtask
1592 
*/
1593 
/*
1594 
task read_overrun_info;
1595 
  input [4:0] start_addr;
1596 
  input [4:0] end_addr;
1597 
  integer i;
1598 
  begin
1599 
    for (i=start_addr; i<=end_addr; i=i+1)
1600 
      begin
1601 
        $display("len[0x%0x]=0x%0x", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i]);
1602 
        $display("overrun[0x%0x]=0x%0x\n", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i]);
1603 
      end
1604 
  end
1605 
endtask
1606 
*/
1607 
 
1608 
task fifo_info;   // Displaying how many packets and how many bytes are in fifo. Not working when wr_info_pointer is smaller than rd_info_pointer.
1609 
  begin
1610 
      $display("(%0t) Currently %0d bytes in fifo (%0d packets)", $time, can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_cnt,
1611 
      (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_info_pointer - can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer));
1612 
end
1613 
endtask
1614 
 
1615 
 
1616 
task read_register;
1617 
  input [7:0] reg_addr;
1618 
 
1619 
  `ifdef CAN_WISHBONE_IF
1620 
    begin
1621 
      wait (wb_free);
1622 
      wb_free = 0;
1623 
      @ (posedge wb_clk_i);
1624 
      #1;
1625 
      cs_can = 1;
1626 
      wb_adr_i = reg_addr;
1627 
      wb_cyc_i = 1;
1628 
      wb_stb_i = 1;
1629 
      wb_we_i = 0;
1630 
      wait (wb_ack_o);
1631 
      $display("(%0t) Reading register [%0d] = 0x%0x", $time, wb_adr_i, wb_dat_o);
1632 
      @ (posedge wb_clk_i);
1633 
      #1;
1634 
      wb_adr_i = 'hz;
1635 
      wb_cyc_i = 0;
1636 
      wb_stb_i = 0;
1637 
      wb_we_i = 'hz;
1638 
      cs_can = 0;
1639 
      wb_free = 1;
1640 
    end
1641 
  `else
1642 
    begin
1643 
      wait (port_free);
1644 
      port_free = 0;
1645 
      @ (posedge clk);
1646 
      #1;
1647 
      cs_can = 1;
1648 
      @ (negedge clk);
1649 
      #1;
1650 
      ale_i = 1;
1651 
      port_0_en = 1;
1652 
      port_0_o = reg_addr;
1653 
      @ (negedge clk);
1654 
      #1;
1655 
      ale_i = 0;
1656 
      #90;            // 73 - 103 ns
1657 
      port_0_en = 0;
1658 
      rd_i = 1;
1659 
      #158;
1660 
      $display("(%0t) Reading register [%0d] = 0x%0x", $time, can_testbench.i_can_top.addr_latched, port_0_i);
1661 
      #1;
1662 
      rd_i = 0;
1663 
      cs_can = 0;
1664 
      port_free = 1;
1665 
    end
1666 
  `endif
1667 
endtask
1668 
 
1669 
 
1670 
task write_register;
1671 
  input [7:0] reg_addr;
1672 
  input [7:0] reg_data;
1673 
 
1674 
  `ifdef CAN_WISHBONE_IF
1675 
    begin
1676 
      wait (wb_free);
1677 
      wb_free = 0;
1678 
      @ (posedge wb_clk_i);
1679 
      #1;
1680 
      cs_can = 1;
1681 
      wb_adr_i = reg_addr;
1682 
      wb_dat_i = reg_data;
1683 
      wb_cyc_i = 1;
1684 
      wb_stb_i = 1;
1685 
      wb_we_i = 1;
1686 
      wait (wb_ack_o);
1687 
      @ (posedge wb_clk_i);
1688 
      #1;
1689 
      wb_adr_i = 'hz;
1690 
      wb_dat_i = 'hz;
1691 
      wb_cyc_i = 0;
1692 
      wb_stb_i = 0;
1693 
      wb_we_i = 'hz;
1694 
      cs_can = 0;
1695 
      wb_free = 1;
1696 
    end
1697 
  `else
1698 
    begin
1699 
      wait (port_free);
1700 
      port_free = 0;
1701 
      @ (posedge clk);
1702 
      #1;
1703 
      cs_can = 1;
1704 
      @ (negedge clk);
1705 
      #1;
1706 
      ale_i = 1;
1707 
      port_0_en = 1;
1708 
      port_0_o = reg_addr;
1709 
      @ (negedge clk);
1710 
      #1;
1711 
      ale_i = 0;
1712 
      #90;            // 73 - 103 ns
1713 
      port_0_o = reg_data;
1714 
      wr_i = 1;
1715 
      #158;
1716 
      wr_i = 0;
1717 
      port_0_en = 0;
1718 
      cs_can = 0;
1719 
      port_free = 1;
1720 
    end
1721 
  `endif
1722 
endtask
1723 
 
1724 
 
1725 
task read_receive_buffer;
1726 
  integer i;
1727 
  begin
1728 
    $display("\n\n(%0t)", $time);
1729 
    if(extended_mode)   // Extended mode
1730 
      begin
1731 
        for (i=8'd16; i<=8'd28; i=i+1)
1732 
          read_register(i);
1733 
        if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun)
1734 
          $display("\nWARNING: Above packet was received with overrun.");
1735 
      end
1736 
    else
1737 
      begin
1738 
        for (i=8'd20; i<=8'd29; i=i+1)
1739 
          read_register(i);
1740 
        if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun)
1741 
          $display("\nWARNING: Above packet was received with overrun.");
1742 
      end
1743 
  end
1744 
endtask
1745 
 
1746 
 
1747 
task release_rx_buffer_command;
1748 
  begin
1749 
    write_register(8'd1, 8'h4);
1750 
    $display("(%0t) Rx buffer released.", $time);
1751 
  end
1752 
endtask
1753 
 
1754 
 
1755 
task tx_request_command;
1756 
  begin
1757 
    write_register(8'd1, 8'h1);
1758 
    $display("(%0t) Tx requested.", $time);
1759 
  end
1760 
endtask
1761 
 
1762 
 
1763 
task tx_abort_command;
1764 
  begin
1765 
    write_register(8'd1, 8'h2);
1766 
    $display("(%0t) Tx abort requested.", $time);
1767 
  end
1768 
endtask
1769 
 
1770 
 
1771 
task clear_data_overrun_command;
1772 
  begin
1773 
    write_register(8'd1, 8'h8);
1774 
    $display("(%0t) Data overrun cleared.", $time);
1775 
  end
1776 
endtask
1777 
 
1778 
 
1779 
task self_reception_request_command;
1780 
  begin
1781 
    write_register(8'd1, 8'h10);
1782 
    $display("(%0t) Self reception requested.", $time);
1783 
  end
1784 
endtask
1785 
 
1786 
 
1787 
task test_synchronization;
1788 
  begin
1789 
    // Hard synchronization
1790 
    #1 rx=0;
1791 
    repeat (2*BRP) @ (posedge clk);
1792 
    repeat (8*BRP) @ (posedge clk);
1793 
    #1 rx=1;
1794 
    repeat (10*BRP) @ (posedge clk);
1795 
 
1796 
    // Resynchronization on time
1797 
    #1 rx=0;
1798 
    repeat (10*BRP) @ (posedge clk);
1799 
    #1 rx=1;
1800 
    repeat (10*BRP) @ (posedge clk);
1801 
 
1802 
    // Resynchronization late
1803 
    repeat (BRP) @ (posedge clk);
1804 
    repeat (BRP) @ (posedge clk);
1805 
    #1 rx=0;
1806 
    repeat (10*BRP) @ (posedge clk);
1807 
    #1 rx=1;
1808 
 
1809 
    // Resynchronization early
1810 
    repeat (8*BRP) @ (posedge clk);   // two frames too early
1811 
    #1 rx=0;
1812 
    repeat (10*BRP) @ (posedge clk);
1813 
    #1 rx=1;
1814 
    repeat (10*BRP) @ (posedge clk);
1815 
  end
1816 
endtask
1817 
 
1818 
 
1819 
task send_bit;
1820 
  input bit;
1821 
  integer cnt;
1822 
  begin
1823 
    #1 rx=bit;
1824 
    repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
1825 
  end
1826 
endtask
1827 
 
1828 
 
1829 
task receive_frame;           // CAN IP core receives frames
1830 
  input mode;
1831 
  input remote_trans_req;
1832 
  input [28:0] id;
1833 
  input  [3:0] length;
1834 
  input [14:0] crc;
1835 
 
1836 
  reg [117:0] data;
1837 
  reg         previous_bit;
1838 
  reg         stuff;
1839 
  reg         tmp;
1840 
  reg         arbitration_lost;
1841 
  integer     pointer;
1842 
  integer     cnt;
1843 
  integer     total_bits;
1844 
  integer     stuff_cnt;
1845 
 
1846 
  begin
1847 
 
1848 
    stuff_cnt = 1;
1849 
    stuff = 0;
1850 
 
1851 
    if(mode)          // Extended format
1852 
      data = {id[28:18], 1'b1, 1'b1, id[17:0], remote_trans_req, 2'h0, length};
1853 
    else              // Standard format
1854 
      data = {id[10:0], remote_trans_req, 1'b0, 1'b0, length};
1855 
 
1856 
    if (~remote_trans_req)
1857 
      begin
1858 
        if(length)    // Send data if length is > 0
1859 
          begin
1860 
            for (cnt=1; cnt<=(2*length); cnt=cnt+1)  // data   (we are sending nibbles)
1861 
              data = {data[113:0], cnt[3:0]};
1862 
          end
1863 
      end
1864 
 
1865 
    // Adding CRC
1866 
    data = {data[104:0], crc[14:0]};
1867 
 
1868 
 
1869 
    // Calculating pointer that points to the bit that will be send
1870 
    if (remote_trans_req)
1871 
      begin
1872 
        if(mode)          // Extended format
1873 
          pointer = 52;
1874 
        else              // Standard format
1875 
          pointer = 32;
1876 
      end
1877 
    else
1878 
      begin
1879 
        if(mode)          // Extended format
1880 
          pointer = 52 + 8 * length;
1881 
        else              // Standard format
1882 
          pointer = 32 + 8 * length;
1883 
      end
1884 
 
1885 
    // This is how many bits we need to shift
1886 
    total_bits = pointer;
1887 
 
1888 
    // Waiting until previous msg is finished before sending another one
1889 
    if (arbitration_lost)           //  Arbitration lost. Another node is transmitting. We have to wait until it is finished.
1890 
      wait ( (~can_testbench.i_can_top.i_can_bsp.error_frame) &
1891 
             (~can_testbench.i_can_top.i_can_bsp.rx_inter   ) &
1892 
             (~can_testbench.i_can_top.i_can_bsp.tx_state   )
1893 
           );
1894 
    else                            // We were transmitter of the previous frame. No need to wait for another node to finish transmission.
1895 
      wait ( (~can_testbench.i_can_top.i_can_bsp.error_frame) &
1896 
             (~can_testbench.i_can_top.i_can_bsp.rx_inter   )
1897 
           );
1898 
    arbitration_lost = 0;
1899 
 
1900 
    send_bit(0);                        // SOF
1901 
    previous_bit = 0;
1902 
 
1903 
    fork
1904 
 
1905 
    begin
1906 
      for (cnt=0; cnt<=total_bits; cnt=cnt+1)
1907 
        begin
1908 
          if (stuff_cnt == 5)
1909 
            begin
1910 
              stuff_cnt = 1;
1911 
              total_bits = total_bits + 1;
1912 
              stuff = 1;
1913 
              tmp = ~data[pointer+1];
1914 
              send_bit(~data[pointer+1]);
1915 
              previous_bit = ~data[pointer+1];
1916 
            end
1917 
          else
1918 
            begin
1919 
              if (data[pointer] == previous_bit)
1920 
                stuff_cnt <= stuff_cnt + 1;
1921 
              else
1922 
                stuff_cnt <= 1;
1923 
 
1924 
              stuff = 0;
1925 
              tmp = data[pointer];
1926 
              send_bit(data[pointer]);
1927 
              previous_bit = data[pointer];
1928 
              pointer = pointer - 1;
1929 
            end
1930 
          if (arbitration_lost)
1931 
            cnt=total_bits+1;         // Exit the for loop
1932 
        end
1933 
 
1934 
        // Nothing send after the data (just recessive bit)
1935 
        repeat (13) send_bit(1);         // CRC delimiter + ack + ack delimiter + EOF + intermission= 1 + 1 + 1 + 7 + 3
1936 
    end
1937 
 
1938 
    begin
1939 
      while (mode ? (cnt<32) : (cnt<12))
1940 
        begin
1941 
          #1 wait (can_testbench.i_can_top.sample_point);
1942 
          if (mode)
1943 
            begin
1944 
              if (cnt<32 & tmp & (~rx_and_tx))
1945 
                begin
1946 
                  arbitration_lost = 1;
1947 
                  rx = 1;       // Only recessive is send from now on.
1948 
                end
1949 
            end
1950 
          else
1951 
            begin
1952 
              if (cnt<12 & tmp & (~rx_and_tx))
1953 
                begin
1954 
                  arbitration_lost = 1;
1955 
                  rx = 1;       // Only recessive is send from now on.
1956 
                end
1957 
            end
1958 
        end
1959 
    end
1960 
 
1961 
    join
1962 
 
1963 
  end
1964 
endtask
1965 
 
1966 
 
1967 
 
1968 
// State machine monitor (btl)
1969 
always @ (posedge clk)
1970 
begin
1971 
  if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
1972 
     can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
1973 
    begin
1974 
      $display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);
1975 
      #1000;
1976 
      $stop;
1977 
    end
1978 
 
1979 
  if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
1980 
     can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
1981 
    begin
1982 
      $display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);
1983 
      #1000;
1984 
      $stop;
1985 
    end
1986 
end
1987 
 
1988 
/* stuff_error monitor (bsp)
1989 
always @ (posedge clk)
1990 
begin
1991 
  if(can_testbench.i_can_top.i_can_bsp.stuff_error)
1992 
    begin
1993 
      $display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);
1994 
      $stop;                                      After everything is finished add another condition (something like & (~idle)) and enable stop
1995 
    end
1996 
end
1997 
*/
1998 
 
1999 
//
2000 
// CRC monitor (used until proper CRC generation is used in testbench
2001 
always @ (posedge clk)
2002 
begin
2003 
  if (can_testbench.i_can_top.i_can_bsp.rx_ack       &
2004 
      can_testbench.i_can_top.i_can_bsp.sample_point &
2005 
      can_testbench.i_can_top.i_can_bsp.crc_err
2006 
     )
2007 
    $display("*E (%0t) ERROR: CRC error (Calculated crc = 0x%0x, crc_in = 0x%0x)", $time, can_testbench.i_can_top.i_can_bsp.calculated_crc, can_testbench.i_can_top.i_can_bsp.crc_in);
2008 
end
2009 
 
2010 
 
2011 
 
2012 
 
2013 
 
2014 
/*
2015 
// overrun monitor
2016 
always @ (posedge clk)
2017 
begin
2018 
  if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr & can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_full)
2019 
    $display("(%0t)overrun", $time);
2020 
end
2021 
*/
2022 
 
2023 
 
2024 
// form error monitor
2025 
always @ (posedge clk)
2026 
begin
2027 
  if (can_testbench.i_can_top.i_can_bsp.form_err)
2028 
    $display("*E (%0t) ERROR: form_error", $time);
2029 
end
2030 
 
2031 
 
2032 
 
2033 
// acknowledge error monitor
2034 
always @ (posedge clk)
2035 
begin
2036 
  if (can_testbench.i_can_top.i_can_bsp.ack_err)
2037 
    $display("*E (%0t) ERROR: acknowledge_error", $time);
2038 
end
2039 
 
2040 
/*
2041 
// bit error monitor
2042 
always @ (posedge clk)
2043 
begin
2044 
  if (can_testbench.i_can_top.i_can_bsp.bit_err)
2045 
    $display("*E (%0t) ERROR: bit_error", $time);
2046 
end
2047 
*/
2048 
 
2049 
endmodule
2050 
 

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