URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [initial/] [rtl/] [verilog/] [can_bitstuff.v] - Blame information for rev 163

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_bitstuff.v                                              ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocal Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_bitstuff
( clk,
  rst,
  enable,
  data_in,
  data_out
);
 
parameter Tp = 1;
 
input  clk;
input  rst;
input  enable;
input  [30:0]arbitration;
 
output data_out;
 
 
reg [2:0] bit_cnt;
reg       data_in_q;
 
always @ (posedge clk or posedge rst)
begin
  if(rst)
    data_in_q <= 0;
  else if (enable)
    data_in_q <= data_in;
  else
    data_in_q <= ~data_in;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if(rst)
    bit_cnt <= 0;
  else if (enable)
    begin
      if(data_in ^ data_in_q)
        bit_cnt <= 0;
      else
        bit_cnt <= bit_cnt + 1'b1;
    end
  else
    bit_cnt <= 0;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if(rst)
    data_out <= 0;
  else if (enable)
    data_in_q <= data_in;
  else
    data_in_q <= ~data_in;
end
 
 
 
wire go_idle;
 
 
always @ (posedge clk or posedge rst)
begin
  if(rst)
    cnt <= 0;
  else if(data_in)
    cnt <= cnt + 1'b1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if(rst)
    idle <= 1'b0;
  else if(go_idle)
    idle <= 1'b1;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_bitstuff.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocal Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`//`
49			`//`
50
51			`// synopsys translate_off`
52			`include "timescale.v"
53			`// synopsys translate_on`
54			`include "can_defines.v"
55
56			`module can_bitstuff`
57			`( clk,`
58			`rst,`
59			`enable,`
60			`data_in,`
61			`data_out`
62			`);`
63
64			`parameter Tp = 1;`
65
66			`input clk;`
67			`input rst;`
68			`input enable;`
69			`input [30:0]arbitration;`
70
71			`output data_out;`
72
73
74			`reg [2:0] bit_cnt;`
75			`reg data_in_q;`
76
77			`always @ (posedge clk or posedge rst)`
78			`begin`
79			`if(rst)`
80			`data_in_q <= 0;`
81			`else if (enable)`
82			`data_in_q <= data_in;`
83			`else`
84			`data_in_q <= ~data_in;`
85			`end`
86
87
88			`always @ (posedge clk or posedge rst)`
89			`begin`
90			`if(rst)`
91			`bit_cnt <= 0;`
92			`else if (enable)`
93			`begin`
94			`if(data_in ^ data_in_q)`
95			`bit_cnt <= 0;`
96			`else`
97			`bit_cnt <= bit_cnt + 1'b1;`
98			`end`
99			`else`
100			`bit_cnt <= 0;`
101			`end`
102
103
104			`always @ (posedge clk or posedge rst)`
105			`begin`
106			`if(rst)`
107			`data_out <= 0;`
108			`else if (enable)`
109			`data_in_q <= data_in;`
110			`else`
111			`data_in_q <= ~data_in;`
112			`end`
113
114
115
116			`wire go_idle;`
117
118
119			`always @ (posedge clk or posedge rst)`
120			`begin`
121			`if(rst)`
122			`cnt <= 0;`
123			`else if(data_in)`
124			`cnt <= cnt + 1'b1;`
125			`end`
126
127
128			`always @ (posedge clk or posedge rst)`
129			`begin`
130			`if(rst)`
131			`idle <= 1'b0;`
132			`else if(go_idle)`
133			`idle <= 1'b1;`
134			`end`
135
136
137			`endmodule`

Browse

Tools

Subversion Repositories can

[/] [can/] [tags/] [initial/] [rtl/] [verilog/] [can_bitstuff.v] - Blame information for rev 163