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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocal Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
 
  /* Mode register */
  reset_mode,           // Not used !!!
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  take_sample,
  clk_en,
 
  /* States */
  idle,
 
  /* bit stream processor (can_bsp.v) */
  sync_mode
 
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
 
/* Mode register */
input         reset_mode;
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output signals from this module */
output        take_sample;
output        clk_en;
 
input         idle;
 
/* bit stream processor (can_bsp.v) */
input         sync_mode;        // NOT USED, YET
 
 
reg     [8:0] clk_cnt;
reg           clk_en;
 
 
reg           hard_sync_blocked;
reg           resync_blocked;
reg           monitored_bit;
 
 
/* Needed for edge detection */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    monitored_bit <= 1'b0;
  else if(clk_en)
    monitored_bit <=#Tp rx;
end
 
 
reg           sampled_bit;
reg     [7:0] quant_cnt;
 
 
/* Generating general enable signal that defines baud rate.
   Hard synchronization is done here.                       */
wire [8:0]    preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
wire          hard_sync =   idle  & (~monitored_bit) & sampled_bit & (~hard_sync_blocked);
wire          resync    = (~idle) & (~monitored_bit) & sampled_bit & (~resync_blocked);
 
 
 
/* Generating enable signal (can clock) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      clk_cnt <= 0;
      clk_en  <= 1'b0;
    end
  else if (clk_cnt == (preset_cnt-1))
    begin
      clk_cnt <=#Tp 0;
      clk_en  <=#Tp 1'b1;
    end
  else
    begin
      clk_cnt <=#Tp clk_cnt + 1;
      clk_en  <=#Tp 1'b0;
    end
end
 
 
/* Hard Synchronization */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      quant_cnt <=#Tp 0;
      hard_sync_blocked <=#Tp 1'b0;
    end
  else if (clk_en)
    begin
      if (hard_sync || (quant_cnt == (time_segment1 + time_segment2 + 2)))  // Hard synchronization
        begin
          quant_cnt <=#Tp 0;
          hard_sync_blocked <=#Tp hard_sync;
        end
      else
        begin
          quant_cnt <=#Tp quant_cnt + 1;
        end
    end
end
 
 
/* Resynchronization */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      resync_blocked <=#Tp 1'b0;
    end
  else if (clk_en)
    begin
      if (resync)
        begin
          if (quant_cnt == (time_segment1 + time_segment2 + 2))     // Right on time
            dodatek = 0;
          else if (sample_point_passed)                             // Too late
            dodatek = quant_cnt;  // Take smaller (SJW : quant_cnt)
          else                                                      // Too early
            reseti clock to 0 so we start with new bit sooner
 
 
 
 
/* sample_point_passed is needed for phase error detection. Signal is set only when resynchronization is possible (high to low transition) */
reg sample_point_passed;
always @ (posedge clk)
begin
  if (clk_en & (quant_cnt == (time_segment1 + time_segment2 + 2)))
    begin
      if(rx)
        sample_point_passed <=#Tp 1'b0;
      else
        sample_point_passed <=#Tp 1'b1;
    end
end
 
 
/* Sampling data */
wire sample_time =
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1;
    end
  else if (clk_en & (quant_cnt == time_segment1))
    begin
      sampled_bit <=#Tp rx;
    end
end
 
 
 
Detect phase error and change the above flip-flop
 
 
 
 
endmodule

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[/] [can/] [tags/] [initial/] [rtl/] [verilog/] [can_btl.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocal Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`//`
49			`//`
50
51			`// synopsys translate_off`
52			`include "timescale.v"
53			`// synopsys translate_on`
54			`include "can_defines.v"
55
56			`module can_btl`
57			`(`
58			`clk,`
59			`rst,`
60			`rx,`
61
62			`/* Mode register */`
63			`reset_mode, // Not used !!!`
64
65			`/* Bus Timing 0 register */`
66			`baud_r_presc,`
67			`sync_jump_width,`
68
69			`/* Bus Timing 1 register */`
70			`time_segment1,`
71			`time_segment2,`
72			`triple_sampling,`
73
74			`/* Output signals from this module */`
75			`take_sample,`
76			`clk_en,`
77
78			`/* States */`
79			`idle,`
80
81			`/* bit stream processor (can_bsp.v) */`
82			`sync_mode`
83
84
85			`);`
86
87			`parameter Tp = 1;`
88
89			`input clk;`
90			`input rst;`
91			`input rx;`
92
93			`/* Mode register */`
94			`input reset_mode;`
95
96			`/* Bus Timing 0 register */`
97			`input [5:0] baud_r_presc;`
98			`input [1:0] sync_jump_width;`
99
100			`/* Bus Timing 1 register */`
101			`input [3:0] time_segment1;`
102			`input [2:0] time_segment2;`
103			`input triple_sampling;`
104
105			`/* Output signals from this module */`
106			`output take_sample;`
107			`output clk_en;`
108
109			`input idle;`
110
111			`/* bit stream processor (can_bsp.v) */`
112			`input sync_mode; // NOT USED, YET`
113
114
115			`reg [8:0] clk_cnt;`
116			`reg clk_en;`
117
118
119			`reg hard_sync_blocked;`
120			`reg resync_blocked;`
121			`reg monitored_bit;`
122
123
124			`/* Needed for edge detection */`
125			`always @ (posedge clk or posedge rst)`
126			`begin`
127			`if (rst)`
128			`monitored_bit <= 1'b0;`
129			`else if(clk_en)`
130			`monitored_bit <=#Tp rx;`
131			`end`
132
133
134			`reg sampled_bit;`
135			`reg [7:0] quant_cnt;`
136
137
138			`/* Generating general enable signal that defines baud rate.`
139			`Hard synchronization is done here. */`
140			`wire [8:0] preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
141			`wire hard_sync = idle & (~monitored_bit) & sampled_bit & (~hard_sync_blocked);`
142			`wire resync = (~idle) & (~monitored_bit) & sampled_bit & (~resync_blocked);`
143
144
145
146			`/* Generating enable signal (can clock) */`
147			`always @ (posedge clk or posedge rst)`
148			`begin`
149			`if (rst)`
150			`begin`
151			`clk_cnt <= 0;`
152			`clk_en <= 1'b0;`
153			`end`
154			`else if (clk_cnt == (preset_cnt-1))`
155			`begin`
156			`clk_cnt <=#Tp 0;`
157			`clk_en <=#Tp 1'b1;`
158			`end`
159			`else`
160			`begin`
161			`clk_cnt <=#Tp clk_cnt + 1;`
162			`clk_en <=#Tp 1'b0;`
163			`end`
164			`end`
165
166
167			`/* Hard Synchronization */`
168			`always @ (posedge clk or posedge rst)`
169			`begin`
170			`if (rst)`
171			`begin`
172			`quant_cnt <=#Tp 0;`
173			`hard_sync_blocked <=#Tp 1'b0;`
174			`end`
175			`else if (clk_en)`
176			`begin`
177			`if (hard_sync \|\| (quant_cnt == (time_segment1 + time_segment2 + 2))) // Hard synchronization`
178			`begin`
179			`quant_cnt <=#Tp 0;`
180			`hard_sync_blocked <=#Tp hard_sync;`
181			`end`
182			`else`
183			`begin`
184			`quant_cnt <=#Tp quant_cnt + 1;`
185			`end`
186			`end`
187			`end`
188
189
190			`/* Resynchronization */`
191			`always @ (posedge clk or posedge rst)`
192			`begin`
193			`if (rst)`
194			`begin`
195			`resync_blocked <=#Tp 1'b0;`
196			`end`
197			`else if (clk_en)`
198			`begin`
199			`if (resync)`
200			`begin`
201			`if (quant_cnt == (time_segment1 + time_segment2 + 2)) // Right on time`
202			`dodatek = 0;`
203			`else if (sample_point_passed) // Too late`
204			`dodatek = quant_cnt; // Take smaller (SJW : quant_cnt)`
205			`else // Too early`
206			`reseti clock to 0 so we start with new bit sooner`
207
208
209
210
211			`/* sample_point_passed is needed for phase error detection. Signal is set only when resynchronization is possible (high to low transition) */`
212			`reg sample_point_passed;`
213			`always @ (posedge clk)`
214			`begin`
215			`if (clk_en & (quant_cnt == (time_segment1 + time_segment2 + 2)))`
216			`begin`
217			`if(rx)`
218			`sample_point_passed <=#Tp 1'b0;`
219			`else`
220			`sample_point_passed <=#Tp 1'b1;`
221			`end`
222			`end`
223
224
225			`/* Sampling data */`
226			`wire sample_time =`
227
228			`always @ (posedge clk or posedge rst)`
229			`begin`
230			`if (rst)`
231			`begin`
232			`sampled_bit <= 1;`
233			`end`
234			`else if (clk_en & (quant_cnt == time_segment1))`
235			`begin`
236			`sampled_bit <=#Tp rx;`
237			`end`
238			`end`
239
240
241
242			`Detect phase error and change the above flip-flop`
243
244
245
246
247			`endmodule`