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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.6  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.5  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.4  2002/12/26 01:33:05  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:16  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:17:00  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
 
  /* Mode register */
  reset_mode,
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  clk_en,
  sample_point,
  sampled_bit,
  sampled_bit_q,
  hard_sync,
  resync,
 
  /* Output from can_bsp module */
  rx_idle
 
 
 
 
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
 
  /* Mode register */
input         reset_mode;
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output from can_bsp module */
input         rx_idle;
 
/* Output signals from this module */
output        clk_en;
output        sample_point;
output        sampled_bit;
output        sampled_bit_q;
output        hard_sync;
output        resync;
 
 
 
reg     [8:0] clk_cnt;
reg           clk_en;
reg           sync_blocked;
reg           sampled_bit;
reg           sampled_bit_q;
reg     [7:0] quant_cnt;
reg     [3:0] delay;
reg           sync;
reg           seg1;
reg           seg2;
reg           resync_latched;
reg           sample_point;
reg     [1:0] sample;
 
wire          go_sync;
wire          go_seg1;
wire          go_seg2;
wire [8:0]    preset_cnt;
wire          sync_window;
 
 
 
assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
assign hard_sync  =   rx_idle  & (~rx) & sampled_bit & (~sync_blocked);  // Hard synchronization
assign resync     = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked);  // Re-synchronization
 
 
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_cnt <= 0;
  else if (clk_cnt == (preset_cnt-1) | reset_mode)
    clk_cnt <=#Tp 0;
  else
    clk_cnt <=#Tp clk_cnt + 1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en  <= 1'b0;
  else if (clk_cnt == (preset_cnt-1))
    clk_en  <=#Tp 1'b1;
  else
    clk_en  <=#Tp 1'b0;
end
 
 
 
/* Changing states */
 assign go_sync = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt == time_segment2)));
 assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
 assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
 
 
 
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
   SJW is reached */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_latched <= 1'b0;
  else if (resync & seg2 & (~sync_window))
    resync_latched <=#Tp 1'b1;
  else if (go_seg1)
    resync_latched <= 1'b0;
end
 
 
 
/* Synchronization stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync <= 0;
  else if (go_sync)
    sync <=#Tp 1'b1;
  else if (go_seg1)
    sync <=#Tp 1'b0;
end
 
 
/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg1 <= 1;
  else if (go_seg1)
    seg1 <=#Tp 1'b1;
  else if (go_seg2)
    seg1 <=#Tp 1'b0;
end
 
 
/* Seg2 stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg2 <= 0;
  else if (go_seg2)
    seg2 <=#Tp 1'b1;
  else if (go_sync | go_seg1)
    seg2 <=#Tp 1'b0;
end
 
 
/* Quant counter */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    quant_cnt <= 0;
  else if (go_sync || go_seg1 || go_seg2)
    quant_cnt <=#Tp 0;
  else if (clk_en)
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
 
 
/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    delay <= 0;
  else if (clk_en & resync & seg1)
    delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);
  else if (go_sync | go_seg1)
    delay <=#Tp 0;
end
 
 
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));
 
 
// Sampling data (memorizing two samples all the time).
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sample <= 2'b11;
  else if (clk_en)
    sample <= {sample[0], rx};
end
 
 
// When enabled, tripple sampling is done here.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1;
      sampled_bit_q <= 1;
      sample_point <= 0;
    end
  else if (clk_en & (~hard_sync))
    begin
      if (seg1 & (quant_cnt == (time_segment1 + delay)))
        begin
          sample_point <=#Tp 1;
          sampled_bit_q <=#Tp sampled_bit;
          if (triple_sampling)
            sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
          else
            sampled_bit <=#Tp rx;
        end
    end
  else
    sample_point <=#Tp 0;
end
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync_blocked <=#Tp 1'b0;
  else if (clk_en)
    begin
      if (hard_sync || resync)
        sync_blocked <=#Tp 1'b1;
      else if (seg2 & quant_cnt == time_segment2)
        sync_blocked <=#Tp 1'b0;
    end
end
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	15	mohor	`// Revision 1.7 2003/01/08 02:10:53 mohor`
49			`// Acceptance filter added.`
50			`//`
51	11	mohor	`// Revision 1.6 2002/12/28 04:13:23 mohor`
52			`// Backup version.`
53			`//`
54	10	mohor	`// Revision 1.5 2002/12/27 00:12:52 mohor`
55			`// Header changed, testbench improved to send a frame (crc still missing).`
56			`//`
57	9	mohor	`// Revision 1.4 2002/12/26 01:33:05 mohor`
58			`// Tripple sampling supported.`
59			`//`
60	7	mohor	`// Revision 1.3 2002/12/25 23:44:16 mohor`
61			`// Commented lines removed.`
62			`//`
63	6	mohor	`// Revision 1.2 2002/12/25 14:17:00 mohor`
64			`// Synchronization working.`
65			`//`
66	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
67			`// Initial`
68	2	mohor	`//`
69			`//`
70	5	mohor	`//`
71	2	mohor
72			`// synopsys translate_off`
73			`include "timescale.v"
74			`// synopsys translate_on`
75			`include "can_defines.v"
76
77			`module can_btl`
78			`(`
79			`clk,`
80			`rst,`
81			`rx,`
82
83			`/* Mode register */`
84	10	mohor	`reset_mode,`
85	2	mohor
86			`/* Bus Timing 0 register */`
87			`baud_r_presc,`
88			`sync_jump_width,`
89
90			`/* Bus Timing 1 register */`
91			`time_segment1,`
92			`time_segment2,`
93			`triple_sampling,`
94
95			`/* Output signals from this module */`
96			`clk_en,`
97	10	mohor	`sample_point,`
98			`sampled_bit,`
99			`sampled_bit_q,`
100	11	mohor	`hard_sync,`
101			`resync,`
102	2	mohor
103	10	mohor	`/* Output from can_bsp module */`
104			`rx_idle`
105	2	mohor
106	10	mohor
107	11	mohor
108	2	mohor
109
110			`);`
111
112			`parameter Tp = 1;`
113
114			`input clk;`
115			`input rst;`
116			`input rx;`
117
118	10	mohor	`/* Mode register */`
119	2	mohor	`input reset_mode;`
120
121			`/* Bus Timing 0 register */`
122			`input [5:0] baud_r_presc;`
123			`input [1:0] sync_jump_width;`
124
125			`/* Bus Timing 1 register */`
126			`input [3:0] time_segment1;`
127			`input [2:0] time_segment2;`
128			`input triple_sampling;`
129
130	10	mohor	`/* Output from can_bsp module */`
131			`input rx_idle;`
132
133	2	mohor	`/* Output signals from this module */`
134			`output clk_en;`
135	10	mohor	`output sample_point;`
136			`output sampled_bit;`
137			`output sampled_bit_q;`
138	11	mohor	`output hard_sync;`
139			`output resync;`
140	2	mohor
141
142
143			`reg [8:0] clk_cnt;`
144			`reg clk_en;`
145	5	mohor	`reg sync_blocked;`
146	2	mohor	`reg sampled_bit;`
147	10	mohor	`reg sampled_bit_q;`
148	2	mohor	`reg [7:0] quant_cnt;`
149	6	mohor	`reg [3:0] delay;`
150			`reg sync;`
151			`reg seg1;`
152			`reg seg2;`
153			`reg resync_latched;`
154	10	mohor	`reg sample_point;`
155	7	mohor	`reg [1:0] sample;`
156	2	mohor
157	6	mohor	`wire go_sync;`
158			`wire go_seg1;`
159			`wire go_seg2;`
160			`wire [8:0] preset_cnt;`
161			`wire sync_window;`
162	2	mohor
163	5	mohor
164
165	6	mohor	`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
166	11	mohor	`assign hard_sync = rx_idle & (~rx) & sampled_bit & (~sync_blocked); // Hard synchronization`
167	10	mohor	`assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization`
168	5	mohor
169
170	6	mohor	`/* Generating general enable signal that defines baud rate. */`
171	2	mohor	`always @ (posedge clk or posedge rst)`
172			`begin`
173			`if (rst)`
174	10	mohor	`clk_cnt <= 0;`
175			`else if (clk_cnt == (preset_cnt-1) \| reset_mode)`
176			`clk_cnt <=#Tp 0;`
177			`else`
178			`clk_cnt <=#Tp clk_cnt + 1;`
179			`end`
180
181
182			`always @ (posedge clk or posedge rst)`
183			`begin`
184			`if (rst)`
185			`clk_en <= 1'b0;`
186	2	mohor	`else if (clk_cnt == (preset_cnt-1))`
187	10	mohor	`clk_en <=#Tp 1'b1;`
188	2	mohor	`else`
189	10	mohor	`clk_en <=#Tp 1'b0;`
190	2	mohor	`end`
191
192
193	5	mohor
194	6	mohor	`/* Changing states */`
195	10	mohor	`assign go_sync = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt == time_segment2)));`
196			`assign go_seg1 = clk_en & (sync \| hard_sync \| (resync & seg2 & sync_window) \| (resync_latched & sync_window));`
197			`assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));`
198	5	mohor
199
200	10	mohor
201	6	mohor	`/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when`
202			`SJW is reached */`
203	2	mohor	`always @ (posedge clk or posedge rst)`
204			`begin`
205			`if (rst)`
206	5	mohor	`resync_latched <= 1'b0;`
207	6	mohor	`else if (resync & seg2 & (~sync_window))`
208	5	mohor	`resync_latched <=#Tp 1'b1;`
209			`else if (go_seg1)`
210			`resync_latched <= 1'b0;`
211			`end`
212
213
214
215	6	mohor	`/* Synchronization stage/segment */`
216	5	mohor	`always @ (posedge clk or posedge rst)`
217			`begin`
218			`if (rst)`
219	10	mohor	`sync <= 0;`
220	5	mohor	`else if (go_sync)`
221			`sync <=#Tp 1'b1;`
222			`else if (go_seg1)`
223			`sync <=#Tp 1'b0;`
224			`end`
225
226
227	6	mohor	`/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */`
228	5	mohor	`always @ (posedge clk or posedge rst)`
229			`begin`
230			`if (rst)`
231	10	mohor	`seg1 <= 1;`
232	5	mohor	`else if (go_seg1)`
233			`seg1 <=#Tp 1'b1;`
234			`else if (go_seg2)`
235			`seg1 <=#Tp 1'b0;`
236			`end`
237
238
239	6	mohor	`/* Seg2 stage/segment */`
240	5	mohor	`always @ (posedge clk or posedge rst)`
241			`begin`
242			`if (rst)`
243			`seg2 <= 0;`
244			`else if (go_seg2)`
245			`seg2 <=#Tp 1'b1;`
246			`else if (go_sync \| go_seg1)`
247			`seg2 <=#Tp 1'b0;`
248			`end`
249
250
251	6	mohor	`/* Quant counter */`
252	5	mohor	`always @ (posedge clk or posedge rst)`
253			`begin`
254			`if (rst)`
255			`quant_cnt <= 0;`
256			`else if (go_sync \|\| go_seg1 \|\| go_seg2)`
257			`quant_cnt <=#Tp 0;`
258			`else if (clk_en)`
259			`quant_cnt <=#Tp quant_cnt + 1'b1;`
260			`end`
261
262
263	6	mohor	`/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */`
264	5	mohor	`always @ (posedge clk or posedge rst)`
265			`begin`
266			`if (rst)`
267	6	mohor	`delay <= 0;`
268	5	mohor	`else if (clk_en & resync & seg1)`
269	6	mohor	`delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);`
270	5	mohor	`else if (go_sync \| go_seg1)`
271	6	mohor	`delay <=#Tp 0;`
272	5	mohor	`end`
273
274
275	6	mohor	`// If early edge appears within this window (in seg2 stage), phase error is fully compensated`
276			`assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));`
277	5	mohor
278
279	7	mohor	`// Sampling data (memorizing two samples all the time).`
280	5	mohor	`always @ (posedge clk or posedge rst)`
281			`begin`
282			`if (rst)`
283	7	mohor	`sample <= 2'b11;`
284			`else if (clk_en)`
285			`sample <= {sample[0], rx};`
286			`end`
287
288
289			`// When enabled, tripple sampling is done here.`
290			`always @ (posedge clk or posedge rst)`
291			`begin`
292			`if (rst)`
293	2	mohor	`begin`
294			`sampled_bit <= 1;`
295	10	mohor	`sampled_bit_q <= 1;`
296			`sample_point <= 0;`
297	2	mohor	`end`
298	15	mohor	`else if (clk_en & (~hard_sync))`
299	2	mohor	`begin`
300	7	mohor	`if (seg1 & (quant_cnt == (time_segment1 + delay)))`
301			`begin`
302	10	mohor	`sample_point <=#Tp 1;`
303			`sampled_bit_q <=#Tp sampled_bit;`
304	7	mohor	`if (triple_sampling)`
305			`sampled_bit <=#Tp (sample[0] & sample[1]) \| ( sample[0] & rx) \| (sample[1] & rx);`
306			`else`
307			`sampled_bit <=#Tp rx;`
308			`end`
309	2	mohor	`end`
310	5	mohor	`else`
311	10	mohor	`sample_point <=#Tp 0;`
312	2	mohor	`end`
313
314
315
316	5	mohor	`/* Blocking synchronization (can occur only once in a bit time) */`
317			`always @ (posedge clk or posedge rst)`
318			`begin`
319			`if (rst)`
320			`sync_blocked <=#Tp 1'b0;`
321			`else if (clk_en)`
322			`begin`
323			`if (hard_sync \|\| resync)`
324			`sync_blocked <=#Tp 1'b1;`
325			`else if (seg2 & quant_cnt == time_segment2)`
326			`sync_blocked <=#Tp 1'b0;`
327			`end`
328			`end`
329	2	mohor
330
331
332
333	5	mohor
334	2	mohor	`endmodule`

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[/] [can/] [tags/] [rel_10/] [rtl/] [verilog/] [can_btl.v] - Blame information for rev 15