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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2003/01/10 17:51:34  mohor
// Temporary version (backup).
//
// Revision 1.7  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.6  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.5  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.4  2002/12/26 01:33:05  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:16  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:17:00  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
 
  /* Mode register */
  reset_mode,
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  clk_en,
  sample_point,
  sampled_bit,
  sampled_bit_q,
  tx_point,
  hard_sync,
  resync,
 
  /* Output from can_bsp module */
  rx_idle,
  transmitting
 
 
 
 
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
 
  /* Mode register */
input         reset_mode;
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output from can_bsp module */
input         rx_idle;
input         transmitting;
 
/* Output signals from this module */
output        clk_en;
output        sample_point;
output        sampled_bit;
output        sampled_bit_q;
output        tx_point;
output        hard_sync;
output        resync;
 
 
 
reg     [8:0] clk_cnt;
reg           clk_en;
reg           sync_blocked;
reg           resync_blocked;
reg           sampled_bit;
reg           sampled_bit_q;
reg     [7:0] quant_cnt;
reg     [3:0] delay;
reg           sync;
reg           seg1;
reg           seg2;
reg           resync_latched;
reg           sample_point;
reg     [1:0] sample;
 
wire          go_sync;
wire          go_seg1;
wire          go_seg2;
wire [8:0]    preset_cnt;
wire          sync_window;
 
 
 
assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
assign hard_sync  =   rx_idle  & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting);  // Hard synchronization
assign resync     = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting);  // Re-synchronization
//assign resync     = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting);  // Re-synchronization
 
 
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_cnt <= 0;
  else if (clk_cnt == (preset_cnt-1) | reset_mode)
    clk_cnt <=#Tp 0;
  else
    clk_cnt <=#Tp clk_cnt + 1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en  <= 1'b0;
  else if (clk_cnt == (preset_cnt-1))
    clk_en  <=#Tp 1'b1;
  else
    clk_en  <=#Tp 1'b0;
end
 
 
 
/* Changing states */
 assign go_sync = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt == time_segment2)));
 assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
 assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
 
 
 
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
   SJW is reached */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_latched <= 1'b0;
  else if (resync & seg2 & (~sync_window))
    resync_latched <=#Tp 1'b1;
  else if (go_seg1)
    resync_latched <= 1'b0;
end
 
 
 
/* Synchronization stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync <= 0;
  else if (go_sync)
    sync <=#Tp 1'b1;
  else if (go_seg1)
    sync <=#Tp 1'b0;
end
 
 
assign tx_point = go_sync;
 
/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg1 <= 1;
  else if (go_seg1)
    seg1 <=#Tp 1'b1;
  else if (go_seg2)
    seg1 <=#Tp 1'b0;
end
 
 
/* Seg2 stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg2 <= 0;
  else if (go_seg2)
    seg2 <=#Tp 1'b1;
  else if (go_sync | go_seg1)
    seg2 <=#Tp 1'b0;
end
 
 
/* Quant counter */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    quant_cnt <= 0;
  else if (go_sync | go_seg1 | go_seg2 | reset_mode)
    quant_cnt <=#Tp 0;
  else if (clk_en)
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
 
 
/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    delay <= 0;
  else if (clk_en & resync & seg1)
    delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);
  else if (go_sync | go_seg1)
    delay <=#Tp 0;
end
 
 
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));
 
 
// Sampling data (memorizing two samples all the time).
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sample <= 2'b11;
  else if (clk_en)
    sample <= {sample[0], rx};
end
 
 
// When enabled, tripple sampling is done here.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1;
      sampled_bit_q <= 1;
      sample_point <= 0;
    end
  else if (clk_en & (~hard_sync))
    begin
      if (seg1 & (quant_cnt == (time_segment1 + delay)))
        begin
          sample_point <=#Tp 1;
          sampled_bit_q <=#Tp sampled_bit;
          if (triple_sampling)
            sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
          else
            sampled_bit <=#Tp rx;
        end
    end
  else
    sample_point <=#Tp 0;
end
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync_blocked <=#Tp 1'b0;
  else if (clk_en)
    begin
      if (hard_sync || resync)
        sync_blocked <=#Tp 1'b1;
      else if (seg2 & quant_cnt == time_segment2)
        sync_blocked <=#Tp 1'b0;
    end
end
 
 
/* Blocking resynchronization until reception starts (needed because after reset mode exits we are waiting for
   end-of-frame and interframe. No resynchronization is needed meanwhile). */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_blocked <=#Tp 1'b1;
  else if (reset_mode)
    resync_blocked <=#Tp 1'b1;
  else if (hard_sync)
    resync_blocked <=#Tp 1'b0;
end
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	24	mohor	`// Revision 1.8 2003/01/10 17:51:34 mohor`
49			`// Temporary version (backup).`
50			`//`
51	15	mohor	`// Revision 1.7 2003/01/08 02:10:53 mohor`
52			`// Acceptance filter added.`
53			`//`
54	11	mohor	`// Revision 1.6 2002/12/28 04:13:23 mohor`
55			`// Backup version.`
56			`//`
57	10	mohor	`// Revision 1.5 2002/12/27 00:12:52 mohor`
58			`// Header changed, testbench improved to send a frame (crc still missing).`
59			`//`
60	9	mohor	`// Revision 1.4 2002/12/26 01:33:05 mohor`
61			`// Tripple sampling supported.`
62			`//`
63	7	mohor	`// Revision 1.3 2002/12/25 23:44:16 mohor`
64			`// Commented lines removed.`
65			`//`
66	6	mohor	`// Revision 1.2 2002/12/25 14:17:00 mohor`
67			`// Synchronization working.`
68			`//`
69	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
70			`// Initial`
71	2	mohor	`//`
72			`//`
73	5	mohor	`//`
74	2	mohor
75			`// synopsys translate_off`
76			`include "timescale.v"
77			`// synopsys translate_on`
78			`include "can_defines.v"
79
80			`module can_btl`
81			`(`
82			`clk,`
83			`rst,`
84			`rx,`
85
86			`/* Mode register */`
87	10	mohor	`reset_mode,`
88	2	mohor
89			`/* Bus Timing 0 register */`
90			`baud_r_presc,`
91			`sync_jump_width,`
92
93			`/* Bus Timing 1 register */`
94			`time_segment1,`
95			`time_segment2,`
96			`triple_sampling,`
97
98			`/* Output signals from this module */`
99			`clk_en,`
100	10	mohor	`sample_point,`
101			`sampled_bit,`
102			`sampled_bit_q,`
103	24	mohor	`tx_point,`
104	11	mohor	`hard_sync,`
105			`resync,`
106	2	mohor
107	10	mohor	`/* Output from can_bsp module */`
108	24	mohor	`rx_idle,`
109			`transmitting`
110	2	mohor
111	10	mohor
112	11	mohor
113	2	mohor
114
115			`);`
116
117			`parameter Tp = 1;`
118
119			`input clk;`
120			`input rst;`
121			`input rx;`
122
123	10	mohor	`/* Mode register */`
124	2	mohor	`input reset_mode;`
125
126			`/* Bus Timing 0 register */`
127			`input [5:0] baud_r_presc;`
128			`input [1:0] sync_jump_width;`
129
130			`/* Bus Timing 1 register */`
131			`input [3:0] time_segment1;`
132			`input [2:0] time_segment2;`
133			`input triple_sampling;`
134
135	10	mohor	`/* Output from can_bsp module */`
136			`input rx_idle;`
137	24	mohor	`input transmitting;`
138	10	mohor
139	2	mohor	`/* Output signals from this module */`
140			`output clk_en;`
141	10	mohor	`output sample_point;`
142			`output sampled_bit;`
143			`output sampled_bit_q;`
144	24	mohor	`output tx_point;`
145	11	mohor	`output hard_sync;`
146			`output resync;`
147	2	mohor
148
149
150			`reg [8:0] clk_cnt;`
151			`reg clk_en;`
152	5	mohor	`reg sync_blocked;`
153	24	mohor	`reg resync_blocked;`
154	2	mohor	`reg sampled_bit;`
155	10	mohor	`reg sampled_bit_q;`
156	2	mohor	`reg [7:0] quant_cnt;`
157	6	mohor	`reg [3:0] delay;`
158			`reg sync;`
159			`reg seg1;`
160			`reg seg2;`
161			`reg resync_latched;`
162	10	mohor	`reg sample_point;`
163	7	mohor	`reg [1:0] sample;`
164	2	mohor
165	6	mohor	`wire go_sync;`
166			`wire go_seg1;`
167			`wire go_seg2;`
168			`wire [8:0] preset_cnt;`
169			`wire sync_window;`
170	2	mohor
171	5	mohor
172
173	6	mohor	`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
174	24	mohor	`assign hard_sync = rx_idle & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting); // Hard synchronization`
175			`assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting); // Re-synchronization`
176			`//assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting); // Re-synchronization`
177	5	mohor
178
179	6	mohor	`/* Generating general enable signal that defines baud rate. */`
180	2	mohor	`always @ (posedge clk or posedge rst)`
181			`begin`
182			`if (rst)`
183	10	mohor	`clk_cnt <= 0;`
184			`else if (clk_cnt == (preset_cnt-1) \| reset_mode)`
185			`clk_cnt <=#Tp 0;`
186			`else`
187			`clk_cnt <=#Tp clk_cnt + 1;`
188			`end`
189
190
191			`always @ (posedge clk or posedge rst)`
192			`begin`
193			`if (rst)`
194			`clk_en <= 1'b0;`
195	2	mohor	`else if (clk_cnt == (preset_cnt-1))`
196	10	mohor	`clk_en <=#Tp 1'b1;`
197	2	mohor	`else`
198	10	mohor	`clk_en <=#Tp 1'b0;`
199	2	mohor	`end`
200
201
202	5	mohor
203	6	mohor	`/* Changing states */`
204	10	mohor	`assign go_sync = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt == time_segment2)));`
205			`assign go_seg1 = clk_en & (sync \| hard_sync \| (resync & seg2 & sync_window) \| (resync_latched & sync_window));`
206			`assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));`
207	5	mohor
208
209	10	mohor
210	6	mohor	`/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when`
211			`SJW is reached */`
212	2	mohor	`always @ (posedge clk or posedge rst)`
213			`begin`
214			`if (rst)`
215	5	mohor	`resync_latched <= 1'b0;`
216	6	mohor	`else if (resync & seg2 & (~sync_window))`
217	5	mohor	`resync_latched <=#Tp 1'b1;`
218			`else if (go_seg1)`
219			`resync_latched <= 1'b0;`
220			`end`
221
222
223
224	6	mohor	`/* Synchronization stage/segment */`
225	5	mohor	`always @ (posedge clk or posedge rst)`
226			`begin`
227			`if (rst)`
228	10	mohor	`sync <= 0;`
229	5	mohor	`else if (go_sync)`
230			`sync <=#Tp 1'b1;`
231			`else if (go_seg1)`
232			`sync <=#Tp 1'b0;`
233			`end`
234
235
236	24	mohor	`assign tx_point = go_sync;`
237
238	6	mohor	`/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */`
239	5	mohor	`always @ (posedge clk or posedge rst)`
240			`begin`
241			`if (rst)`
242	10	mohor	`seg1 <= 1;`
243	5	mohor	`else if (go_seg1)`
244			`seg1 <=#Tp 1'b1;`
245			`else if (go_seg2)`
246			`seg1 <=#Tp 1'b0;`
247			`end`
248
249
250	6	mohor	`/* Seg2 stage/segment */`
251	5	mohor	`always @ (posedge clk or posedge rst)`
252			`begin`
253			`if (rst)`
254			`seg2 <= 0;`
255			`else if (go_seg2)`
256			`seg2 <=#Tp 1'b1;`
257			`else if (go_sync \| go_seg1)`
258			`seg2 <=#Tp 1'b0;`
259			`end`
260
261
262	6	mohor	`/* Quant counter */`
263	5	mohor	`always @ (posedge clk or posedge rst)`
264			`begin`
265			`if (rst)`
266			`quant_cnt <= 0;`
267	24	mohor	`else if (go_sync \| go_seg1 \| go_seg2 \| reset_mode)`
268	5	mohor	`quant_cnt <=#Tp 0;`
269			`else if (clk_en)`
270			`quant_cnt <=#Tp quant_cnt + 1'b1;`
271			`end`
272
273
274	6	mohor	`/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */`
275	5	mohor	`always @ (posedge clk or posedge rst)`
276			`begin`
277			`if (rst)`
278	6	mohor	`delay <= 0;`
279	5	mohor	`else if (clk_en & resync & seg1)`
280	6	mohor	`delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);`
281	5	mohor	`else if (go_sync \| go_seg1)`
282	6	mohor	`delay <=#Tp 0;`
283	5	mohor	`end`
284
285
286	6	mohor	`// If early edge appears within this window (in seg2 stage), phase error is fully compensated`
287			`assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));`
288	5	mohor
289
290	7	mohor	`// Sampling data (memorizing two samples all the time).`
291	5	mohor	`always @ (posedge clk or posedge rst)`
292			`begin`
293			`if (rst)`
294	7	mohor	`sample <= 2'b11;`
295			`else if (clk_en)`
296			`sample <= {sample[0], rx};`
297			`end`
298
299
300			`// When enabled, tripple sampling is done here.`
301			`always @ (posedge clk or posedge rst)`
302			`begin`
303			`if (rst)`
304	2	mohor	`begin`
305			`sampled_bit <= 1;`
306	10	mohor	`sampled_bit_q <= 1;`
307			`sample_point <= 0;`
308	2	mohor	`end`
309	15	mohor	`else if (clk_en & (~hard_sync))`
310	2	mohor	`begin`
311	7	mohor	`if (seg1 & (quant_cnt == (time_segment1 + delay)))`
312			`begin`
313	10	mohor	`sample_point <=#Tp 1;`
314			`sampled_bit_q <=#Tp sampled_bit;`
315	7	mohor	`if (triple_sampling)`
316			`sampled_bit <=#Tp (sample[0] & sample[1]) \| ( sample[0] & rx) \| (sample[1] & rx);`
317			`else`
318			`sampled_bit <=#Tp rx;`
319			`end`
320	2	mohor	`end`
321	5	mohor	`else`
322	10	mohor	`sample_point <=#Tp 0;`
323	2	mohor	`end`
324
325
326
327	5	mohor	`/* Blocking synchronization (can occur only once in a bit time) */`
328			`always @ (posedge clk or posedge rst)`
329			`begin`
330			`if (rst)`
331			`sync_blocked <=#Tp 1'b0;`
332			`else if (clk_en)`
333			`begin`
334			`if (hard_sync \|\| resync)`
335			`sync_blocked <=#Tp 1'b1;`
336			`else if (seg2 & quant_cnt == time_segment2)`
337			`sync_blocked <=#Tp 1'b0;`
338			`end`
339			`end`
340	2	mohor
341
342	24	mohor	`/* Blocking resynchronization until reception starts (needed because after reset mode exits we are waiting for`
343			`end-of-frame and interframe. No resynchronization is needed meanwhile). */`
344			`always @ (posedge clk or posedge rst)`
345			`begin`
346			`if (rst)`
347			`resync_blocked <=#Tp 1'b1;`
348			`else if (reset_mode)`
349			`resync_blocked <=#Tp 1'b1;`
350			`else if (hard_sync)`
351			`resync_blocked <=#Tp 1'b0;`
352			`end`
353	2	mohor
354
355	5	mohor
356	24	mohor
357
358	2	mohor	`endmodule`

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[/] [can/] [tags/] [rel_10/] [rtl/] [verilog/] [can_btl.v] - Blame information for rev 24