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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocal Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
 
  /* Mode register */
  reset_mode,           // Not used !!!
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  take_sample,
  clk_en,
 
  /* States */
  idle,
 
  /* bit stream processor (can_bsp.v) */
  sync_mode
 
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
 
/* Mode register */
input         reset_mode;
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output signals from this module */
output        take_sample;
output        clk_en;
 
input         idle;
 
/* bit stream processor (can_bsp.v) */
input         sync_mode;        // NOT USED, YET
 
 
reg     [8:0] clk_cnt;
reg           clk_en;
 
 
reg           sync_blocked;
reg           monitored_bit;
 
 
/* Needed for edge detection */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    monitored_bit <= 1'b1;
  else if(clk_en)
    monitored_bit <=#Tp rx;
end
 
 
reg           sampled_bit;
reg     [7:0] quant_cnt;
reg     [3:0] dodatek;
wire          odstevek;
 
wire    [7:0] difference;
 
 
reg           rx_early;
 
 
 
/* Generating general enable signal that defines baud rate.
   Hard synchronization is done here.                       */
wire [8:0]    preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
wire          hard_sync =   idle  & (~rx) & sampled_bit & (~sync_blocked);
wire          resync    = (~idle) & (~rx) & sampled_bit & (~sync_blocked);
 
 
 
/* Generating enable signal (can clock) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      clk_cnt <= 0;
      clk_en  <= 1'b0;
    end
  else if (clk_cnt == (preset_cnt-1))
    begin
      clk_cnt <=#Tp 0;
      clk_en  <=#Tp 1'b1;
    end
  else
    begin
      clk_cnt <=#Tp clk_cnt + 1;
      clk_en  <=#Tp 1'b0;
    end
end
 
 
 
assign difference = time_segment1 + time_segment2 + 3 - quant_cnt;
 
 
 
/* Synchronization */
/*
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      quant_cnt <=#Tp 0;
      sync_blocked <=#Tp 1'b0;
      dodatek <=#Tp 0;
      odstevek <=#Tp 0;
    end
  else if (clk_en)
    begin
      if (hard_sync)        // Hard synchronization
        begin
          quant_cnt <=#Tp 1;
          sync_blocked <=#Tp 1'b1;
        end
      else if (resync)      // resynchronization
        begin
          sync_blocked <=#Tp 1'b1;
          if (quant_cnt == 0)     // Right on time
            quant_cnt <=#Tp quant_cnt + 1;
          else if (rx_early)                             // Too early
            begin
                quant_cnt <=#Tp 1;
              odstevek <=#Tp (difference > (sync_jump_width + 1))? (sync_jump_width + 1) : difference;
            end
          else                                                // Too late         // Take smaller (SJW : quant_cnt)
            begin
              dodatek <=#Tp (quant_cnt > (sync_jump_width + 1))? (sync_jump_width + 1) : quant_cnt;
              quant_cnt <=#Tp quant_cnt + 1;
            end
        end
      else if (quant_cnt == (time_segment1 + time_segment2 + 2 + dodatek))
//      else if (quant_cnt == (time_segment1 + time_segment2 + 2 + dodatek - odstevek))
        begin
          quant_cnt <=#Tp 0;
          sync_blocked <=#Tp 1'b0;
          dodatek <=#Tp 0;
          odstevek <=#Tp 0;
        end
      else
        quant_cnt <=#Tp quant_cnt + 1;
    end
end
 
 
 
 
 
reg sample_pulse;
// Sampling data
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1;
      sample_pulse <= 0;
    end
  else if (clk_en & (quant_cnt == (time_segment1 + 1 + dodatek)) & (~idle))   // (~idle) blocks sampling so hard sync works in all cases
    begin
      sampled_bit <=#Tp rx;
      sample_pulse <=#Tp 1;
    end
  else
    sample_pulse <=#Tp 0;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      rx_early <= 1'b0;
    end
  else if (clk_en & rx & (quant_cnt == (time_segment1 + 1)))
    begin
      rx_early <=#Tp 1'b1;
    end
  else if (clk_en & (quant_cnt == 0))
    rx_early <=#Tp 1'b0;
end
 
 
*/
 
 
reg sync;
reg seg1;
reg seg2;
reg resync_latched;
 
 
wire go_sync = clk_en & (seg2 & (~resync) & ((quant_cnt == time_segment2)));
wire go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & odstevek) | (resync_latched & odstevek));
wire go_seg2 = clk_en & (seg1 & (quant_cnt == (time_segment1 + dodatek)));
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_latched <= 1'b0;
  else if (resync & seg2 & (~odstevek))
    resync_latched <=#Tp 1'b1;
  else if (go_seg1)
    resync_latched <= 1'b0;
end
 
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync <= 1;
  else if (go_sync)
    sync <=#Tp 1'b1;
  else if (go_seg1)
    sync <=#Tp 1'b0;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg1 <= 0;
  else if (go_seg1)
    seg1 <=#Tp 1'b1;
  else if (go_seg2)
    seg1 <=#Tp 1'b0;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg2 <= 0;
  else if (go_seg2)
    seg2 <=#Tp 1'b1;
  else if (go_sync | go_seg1)
    seg2 <=#Tp 1'b0;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    quant_cnt <= 0;
  else if (go_sync || go_seg1 || go_seg2)
    quant_cnt <=#Tp 0;
  else if (clk_en)
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    dodatek <= 0;
  else if (clk_en & resync & seg1)
    dodatek <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);
  else if (go_sync | go_seg1)
    dodatek <=#Tp 0;
end
 
/*
always @ (posedge clk or posedge rst)
begin
  if (rst)
    odstevek <= 0;
  else if (clk_en & resync & seg2)
    odstevek <=#Tp ((time_segment2 + 1 - quant_cnt) > sync_jump_width)? (sync_jump_width + 1) : (time_segment2 + 1 - quant_cnt);
  else if (go_sync | go_seg1)
    odstevek <=#Tp 0;
end
*/
 
assign odstevek = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));
 
 
 
reg sample_pulse;
// Sampling data 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1;
      sample_pulse <= 0;
    end
  else if (go_seg2)
    begin
      sampled_bit <=#Tp rx;
      sample_pulse <=#Tp 1;
    end
  else
    sample_pulse <=#Tp 0;
end
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync_blocked <=#Tp 1'b0;
  else if (clk_en)
    begin
      if (hard_sync || resync)
        sync_blocked <=#Tp 1'b1;
      else if (seg2 & quant_cnt == time_segment2)
        sync_blocked <=#Tp 1'b0;
    end
end
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocal Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
49			`// Initial`
50	2	mohor	`//`
51			`//`
52	5	mohor	`//`
53	2	mohor
54			`// synopsys translate_off`
55			`include "timescale.v"
56			`// synopsys translate_on`
57			`include "can_defines.v"
58
59			`module can_btl`
60			`(`
61			`clk,`
62			`rst,`
63			`rx,`
64
65			`/* Mode register */`
66			`reset_mode, // Not used !!!`
67
68			`/* Bus Timing 0 register */`
69			`baud_r_presc,`
70			`sync_jump_width,`
71
72			`/* Bus Timing 1 register */`
73			`time_segment1,`
74			`time_segment2,`
75			`triple_sampling,`
76
77			`/* Output signals from this module */`
78			`take_sample,`
79			`clk_en,`
80
81			`/* States */`
82			`idle,`
83
84			`/* bit stream processor (can_bsp.v) */`
85			`sync_mode`
86
87
88			`);`
89
90			`parameter Tp = 1;`
91
92			`input clk;`
93			`input rst;`
94			`input rx;`
95
96			`/* Mode register */`
97			`input reset_mode;`
98
99			`/* Bus Timing 0 register */`
100			`input [5:0] baud_r_presc;`
101			`input [1:0] sync_jump_width;`
102
103			`/* Bus Timing 1 register */`
104			`input [3:0] time_segment1;`
105			`input [2:0] time_segment2;`
106			`input triple_sampling;`
107
108			`/* Output signals from this module */`
109			`output take_sample;`
110			`output clk_en;`
111
112			`input idle;`
113
114			`/* bit stream processor (can_bsp.v) */`
115			`input sync_mode; // NOT USED, YET`
116
117
118			`reg [8:0] clk_cnt;`
119			`reg clk_en;`
120
121
122	5	mohor	`reg sync_blocked;`
123	2	mohor	`reg monitored_bit;`
124
125
126			`/* Needed for edge detection */`
127			`always @ (posedge clk or posedge rst)`
128			`begin`
129			`if (rst)`
130	5	mohor	`monitored_bit <= 1'b1;`
131	2	mohor	`else if(clk_en)`
132			`monitored_bit <=#Tp rx;`
133			`end`
134
135
136			`reg sampled_bit;`
137			`reg [7:0] quant_cnt;`
138	5	mohor	`reg [3:0] dodatek;`
139			`wire odstevek;`
140	2	mohor
141	5	mohor	`wire [7:0] difference;`
142	2	mohor
143	5	mohor
144			`reg rx_early;`
145
146
147
148	2	mohor	`/* Generating general enable signal that defines baud rate.`
149			`Hard synchronization is done here. */`
150			`wire [8:0] preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
151	5	mohor	`wire hard_sync = idle & (~rx) & sampled_bit & (~sync_blocked);`
152			`wire resync = (~idle) & (~rx) & sampled_bit & (~sync_blocked);`
153	2	mohor
154
155
156			`/* Generating enable signal (can clock) */`
157			`always @ (posedge clk or posedge rst)`
158			`begin`
159			`if (rst)`
160			`begin`
161			`clk_cnt <= 0;`
162			`clk_en <= 1'b0;`
163			`end`
164			`else if (clk_cnt == (preset_cnt-1))`
165			`begin`
166			`clk_cnt <=#Tp 0;`
167			`clk_en <=#Tp 1'b1;`
168			`end`
169			`else`
170			`begin`
171			`clk_cnt <=#Tp clk_cnt + 1;`
172			`clk_en <=#Tp 1'b0;`
173			`end`
174			`end`
175
176
177	5	mohor
178			`assign difference = time_segment1 + time_segment2 + 3 - quant_cnt;`
179
180
181
182			`/* Synchronization */`
183			`/*`
184	2	mohor	`always @ (posedge clk or posedge rst)`
185			`begin`
186			`if (rst)`
187			`begin`
188			`quant_cnt <=#Tp 0;`
189	5	mohor	`sync_blocked <=#Tp 1'b0;`
190			`dodatek <=#Tp 0;`
191			`odstevek <=#Tp 0;`
192	2	mohor	`end`
193			`else if (clk_en)`
194			`begin`
195	5	mohor	`if (hard_sync) // Hard synchronization`
196	2	mohor	`begin`
197	5	mohor	`quant_cnt <=#Tp 1;`
198			`sync_blocked <=#Tp 1'b1;`
199			`end`
200			`else if (resync) // resynchronization`
201			`begin`
202			`sync_blocked <=#Tp 1'b1;`
203			`if (quant_cnt == 0) // Right on time`
204			`quant_cnt <=#Tp quant_cnt + 1;`
205			`else if (rx_early) // Too early`
206			`begin`
207			`quant_cnt <=#Tp 1;`
208			`odstevek <=#Tp (difference > (sync_jump_width + 1))? (sync_jump_width + 1) : difference;`
209			`end`
210			`else // Too late // Take smaller (SJW : quant_cnt)`
211			`begin`
212			`dodatek <=#Tp (quant_cnt > (sync_jump_width + 1))? (sync_jump_width + 1) : quant_cnt;`
213			`quant_cnt <=#Tp quant_cnt + 1;`
214			`end`
215			`end`
216			`else if (quant_cnt == (time_segment1 + time_segment2 + 2 + dodatek))`
217			`// else if (quant_cnt == (time_segment1 + time_segment2 + 2 + dodatek - odstevek))`
218			`begin`
219	2	mohor	`quant_cnt <=#Tp 0;`
220	5	mohor	`sync_blocked <=#Tp 1'b0;`
221			`dodatek <=#Tp 0;`
222			`odstevek <=#Tp 0;`
223	2	mohor	`end`
224			`else`
225	5	mohor	`quant_cnt <=#Tp quant_cnt + 1;`
226	2	mohor	`end`
227			`end`
228
229
230	5	mohor
231
232
233			`reg sample_pulse;`
234			`// Sampling data`
235	2	mohor	`always @ (posedge clk or posedge rst)`
236			`begin`
237			`if (rst)`
238			`begin`
239	5	mohor	`sampled_bit <= 1;`
240			`sample_pulse <= 0;`
241	2	mohor	`end`
242	5	mohor	`else if (clk_en & (quant_cnt == (time_segment1 + 1 + dodatek)) & (~idle)) // (~idle) blocks sampling so hard sync works in all cases`
243	2	mohor	`begin`
244	5	mohor	`sampled_bit <=#Tp rx;`
245			`sample_pulse <=#Tp 1;`
246			`end`
247			`else`
248			`sample_pulse <=#Tp 0;`
249			`end`
250	2	mohor
251	5	mohor
252
253			`always @ (posedge clk or posedge rst)`
254	2	mohor	`begin`
255	5	mohor	`if (rst)`
256	2	mohor	`begin`
257	5	mohor	`rx_early <= 1'b0;`
258	2	mohor	`end`
259	5	mohor	`else if (clk_en & rx & (quant_cnt == (time_segment1 + 1)))`
260			`begin`
261			`rx_early <=#Tp 1'b1;`
262			`end`
263			`else if (clk_en & (quant_cnt == 0))`
264			`rx_early <=#Tp 1'b0;`
265	2	mohor	`end`
266
267
268	5	mohor	`*/`
269	2	mohor
270	5	mohor
271			`reg sync;`
272			`reg seg1;`
273			`reg seg2;`
274			`reg resync_latched;`
275
276
277			`wire go_sync = clk_en & (seg2 & (~resync) & ((quant_cnt == time_segment2)));`
278			`wire go_seg1 = clk_en & (sync \| hard_sync \| (resync & seg2 & odstevek) \| (resync_latched & odstevek));`
279			`wire go_seg2 = clk_en & (seg1 & (quant_cnt == (time_segment1 + dodatek)));`
280
281
282	2	mohor	`always @ (posedge clk or posedge rst)`
283			`begin`
284			`if (rst)`
285	5	mohor	`resync_latched <= 1'b0;`
286			`else if (resync & seg2 & (~odstevek))`
287			`resync_latched <=#Tp 1'b1;`
288			`else if (go_seg1)`
289			`resync_latched <= 1'b0;`
290			`end`
291
292
293
294
295			`always @ (posedge clk or posedge rst)`
296			`begin`
297			`if (rst)`
298			`sync <= 1;`
299			`else if (go_sync)`
300			`sync <=#Tp 1'b1;`
301			`else if (go_seg1)`
302			`sync <=#Tp 1'b0;`
303			`end`
304
305
306			`always @ (posedge clk or posedge rst)`
307			`begin`
308			`if (rst)`
309			`seg1 <= 0;`
310			`else if (go_seg1)`
311			`seg1 <=#Tp 1'b1;`
312			`else if (go_seg2)`
313			`seg1 <=#Tp 1'b0;`
314			`end`
315
316
317			`always @ (posedge clk or posedge rst)`
318			`begin`
319			`if (rst)`
320			`seg2 <= 0;`
321			`else if (go_seg2)`
322			`seg2 <=#Tp 1'b1;`
323			`else if (go_sync \| go_seg1)`
324			`seg2 <=#Tp 1'b0;`
325			`end`
326
327
328			`always @ (posedge clk or posedge rst)`
329			`begin`
330			`if (rst)`
331			`quant_cnt <= 0;`
332			`else if (go_sync \|\| go_seg1 \|\| go_seg2)`
333			`quant_cnt <=#Tp 0;`
334			`else if (clk_en)`
335			`quant_cnt <=#Tp quant_cnt + 1'b1;`
336			`end`
337
338
339			`always @ (posedge clk or posedge rst)`
340			`begin`
341			`if (rst)`
342			`dodatek <= 0;`
343			`else if (clk_en & resync & seg1)`
344			`dodatek <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);`
345			`else if (go_sync \| go_seg1)`
346			`dodatek <=#Tp 0;`
347			`end`
348
349			`/*`
350			`always @ (posedge clk or posedge rst)`
351			`begin`
352			`if (rst)`
353			`odstevek <= 0;`
354			`else if (clk_en & resync & seg2)`
355			`odstevek <=#Tp ((time_segment2 + 1 - quant_cnt) > sync_jump_width)? (sync_jump_width + 1) : (time_segment2 + 1 - quant_cnt);`
356			`else if (go_sync \| go_seg1)`
357			`odstevek <=#Tp 0;`
358			`end`
359			`*/`
360
361			`assign odstevek = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));`
362
363
364
365			`reg sample_pulse;`
366			`// Sampling data`
367			`always @ (posedge clk or posedge rst)`
368			`begin`
369			`if (rst)`
370	2	mohor	`begin`
371			`sampled_bit <= 1;`
372	5	mohor	`sample_pulse <= 0;`
373	2	mohor	`end`
374	5	mohor	`else if (go_seg2)`
375	2	mohor	`begin`
376			`sampled_bit <=#Tp rx;`
377	5	mohor	`sample_pulse <=#Tp 1;`
378	2	mohor	`end`
379	5	mohor	`else`
380			`sample_pulse <=#Tp 0;`
381	2	mohor	`end`
382
383
384
385	5	mohor	`/* Blocking synchronization (can occur only once in a bit time) */`
386			`always @ (posedge clk or posedge rst)`
387			`begin`
388			`if (rst)`
389			`sync_blocked <=#Tp 1'b0;`
390			`else if (clk_en)`
391			`begin`
392			`if (hard_sync \|\| resync)`
393			`sync_blocked <=#Tp 1'b1;`
394			`else if (seg2 & quant_cnt == time_segment2)`
395			`sync_blocked <=#Tp 1'b0;`
396			`end`
397			`end`
398	2	mohor
399
400
401
402	5	mohor
403	2	mohor	`endmodule`

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