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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13  2003/06/11 14:21:35  mohor
// When switching to tx, sync stage is overjumped.
//
// Revision 1.12  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.11  2003/02/09 18:40:29  mohor
// Overload fixed. Hard synchronization also enabled at the last bit of
// interframe.
//
// Revision 1.10  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.9  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.8  2003/01/10 17:51:34  mohor
// Temporary version (backup).
//
// Revision 1.7  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.6  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.5  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.4  2002/12/26 01:33:05  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:16  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:17:00  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
 
  /* Mode register */
  reset_mode,
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  clk_en,
  sample_point,
  sampled_bit,
  sampled_bit_q,
  tx_point,
  hard_sync,
  go_seg1,
 
  /* Output from can_bsp module */
  rx_idle,
  transmitting,
  overjump_sync_seg,
  last_bit_of_inter
 
 
 
 
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
 
  /* Mode register */
input         reset_mode;
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output from can_bsp module */
input         rx_idle;
input         transmitting;
input         overjump_sync_seg;
input         last_bit_of_inter;
 
/* Output signals from this module */
output        clk_en;
output        sample_point;
output        sampled_bit;
output        sampled_bit_q;
output        tx_point;
output        hard_sync;
output        go_seg1;
 
 
 
reg     [8:0] clk_cnt;
reg           clk_en;
reg           sync_blocked;
reg           resync_blocked;
reg           sampled_bit;
reg           sampled_bit_q;
reg     [4:0] quant_cnt;
reg     [3:0] delay;
reg           sync;
reg           seg1;
reg           seg2;
reg           resync_latched;
reg           sample_point;
reg     [1:0] sample;
reg           go_sync;
 
wire          go_sync_unregistered;
wire          go_seg1;
wire          go_seg2;
wire [8:0]    preset_cnt;
wire          sync_window;
wire          resync;
wire          quant_cnt_rst1;
wire          quant_cnt_rst2;
 
 
 
assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
assign hard_sync  =   (rx_idle | last_bit_of_inter)  & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting);  // Hard synchronization
assign resync     =  (~rx_idle)                      & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting);  // Re-synchronization
 
 
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_cnt <= 0;
  else if (clk_cnt == (preset_cnt-1'b1))
    clk_cnt <=#Tp 0;
  else
    clk_cnt <=#Tp clk_cnt + 1'b1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en  <= 1'b0;
  else if (clk_cnt == (preset_cnt-1'b1))
    clk_en  <=#Tp 1'b1;
  else
    clk_en  <=#Tp 1'b0;
end
 
 
 
/* Changing states */
 assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));
 assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
 assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    go_sync <= 1'b0;
  else
    go_sync <=#Tp go_sync_unregistered;
end
 
 
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
   SJW is reached */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_latched <= 1'b0;
  else if (resync & seg2 & (~sync_window))
    resync_latched <=#Tp 1'b1;
  else if (go_seg1)
    resync_latched <= 1'b0;
end
 
 
 
/* Synchronization stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync <= 0;
  else if (go_sync)
    sync <=#Tp 1'b1;
  else
    sync <=#Tp 1'b0;
end
 
 
assign tx_point = go_sync;
 
/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg1 <= 1;
  else if (go_seg1)
    seg1 <=#Tp 1'b1;
  else if (go_seg2)
    seg1 <=#Tp 1'b0;
end
 
 
/* Seg2 stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg2 <= 0;
  else if (go_seg2)
    seg2 <=#Tp 1'b1;
  else if (go_sync | go_seg1)
    seg2 <=#Tp 1'b0;
end
 
 
/* Quant counter */
 
assign quant_cnt_rst1 = go_sync | go_seg1 & (~overjump_sync_seg) | go_seg2;
assign quant_cnt_rst2 = go_seg1 & overjump_sync_seg;
always @ (posedge clk or posedge rst)
begin
  if (rst)
    quant_cnt <= 0;
  else if (quant_cnt_rst1)
    quant_cnt <=#Tp 0;
  else if (quant_cnt_rst2)
    quant_cnt <=#Tp 1;
  else if (clk_en)
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
 
 
/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    delay <= 0;
  else if (clk_en & resync & seg1)
    delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);
  else if (go_sync | go_seg1)
    delay <=#Tp 0;
end
 
 
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
 
 
// Sampling data (memorizing two samples all the time).
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sample <= 2'b11;
  else if (clk_en)
    sample <= {sample[0], rx};
end
 
 
// When enabled, tripple sampling is done here.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1;
      sampled_bit_q <= 1;
      sample_point <= 0;
    end
  else if (clk_en & (~hard_sync))
    begin
      if (seg1 & (quant_cnt == (time_segment1 + delay)))
        begin
          sample_point <=#Tp 1;
          sampled_bit_q <=#Tp sampled_bit;
          if (triple_sampling)
            sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
          else
            sampled_bit <=#Tp rx;
        end
    end
  else
    sample_point <=#Tp 0;
end
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync_blocked <=#Tp 1'b0;
  else if (clk_en)
    begin
      if (hard_sync | resync)
        sync_blocked <=#Tp 1'b1;
      else if (seg2 & (quant_cnt[2:0] == time_segment2))
        sync_blocked <=#Tp 1'b0;
    end
end
 
 
/* Blocking resynchronization until reception starts (needed because after reset mode exits we are waiting for
   end-of-frame and interframe. No resynchronization is needed meanwhile). */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_blocked <=#Tp 1'b1;
  else if (reset_mode)
    resync_blocked <=#Tp 1'b1;
  else if (hard_sync)
    resync_blocked <=#Tp 1'b0;
end
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	2	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	76	mohor	`// Revision 1.13 2003/06/11 14:21:35 mohor`
54			`// When switching to tx, sync stage is overjumped.`
55			`//`
56	75	mohor	`// Revision 1.12 2003/02/14 20:17:01 mohor`
57			`// Several registers added. Not finished, yet.`
58			`//`
59	35	mohor	`// Revision 1.11 2003/02/09 18:40:29 mohor`
60			`// Overload fixed. Hard synchronization also enabled at the last bit of`
61			`// interframe.`
62			`//`
63	29	mohor	`// Revision 1.10 2003/02/09 02:24:33 mohor`
64			`// Bosch license warning added. Error counters finished. Overload frames`
65			`// still need to be fixed.`
66			`//`
67	28	mohor	`// Revision 1.9 2003/01/31 01:13:38 mohor`
68			`// backup.`
69			`//`
70	24	mohor	`// Revision 1.8 2003/01/10 17:51:34 mohor`
71			`// Temporary version (backup).`
72			`//`
73	15	mohor	`// Revision 1.7 2003/01/08 02:10:53 mohor`
74			`// Acceptance filter added.`
75			`//`
76	11	mohor	`// Revision 1.6 2002/12/28 04:13:23 mohor`
77			`// Backup version.`
78			`//`
79	10	mohor	`// Revision 1.5 2002/12/27 00:12:52 mohor`
80			`// Header changed, testbench improved to send a frame (crc still missing).`
81			`//`
82	9	mohor	`// Revision 1.4 2002/12/26 01:33:05 mohor`
83			`// Tripple sampling supported.`
84			`//`
85	7	mohor	`// Revision 1.3 2002/12/25 23:44:16 mohor`
86			`// Commented lines removed.`
87			`//`
88	6	mohor	`// Revision 1.2 2002/12/25 14:17:00 mohor`
89			`// Synchronization working.`
90			`//`
91	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
92			`// Initial`
93	2	mohor	`//`
94			`//`
95	5	mohor	`//`
96	2	mohor
97			`// synopsys translate_off`
98			`include "timescale.v"
99			`// synopsys translate_on`
100			`include "can_defines.v"
101
102			`module can_btl`
103			`(`
104			`clk,`
105			`rst,`
106			`rx,`
107
108			`/* Mode register */`
109	10	mohor	`reset_mode,`
110	2	mohor
111			`/* Bus Timing 0 register */`
112			`baud_r_presc,`
113			`sync_jump_width,`
114
115			`/* Bus Timing 1 register */`
116			`time_segment1,`
117			`time_segment2,`
118			`triple_sampling,`
119
120			`/* Output signals from this module */`
121			`clk_en,`
122	10	mohor	`sample_point,`
123			`sampled_bit,`
124			`sampled_bit_q,`
125	24	mohor	`tx_point,`
126	11	mohor	`hard_sync,`
127	75	mohor	`go_seg1,`
128	2	mohor
129	10	mohor	`/* Output from can_bsp module */`
130	24	mohor	`rx_idle,`
131	29	mohor	`transmitting,`
132	75	mohor	`overjump_sync_seg,`
133	29	mohor	`last_bit_of_inter`
134	2	mohor
135	10	mohor
136	11	mohor
137	2	mohor
138
139			`);`
140
141			`parameter Tp = 1;`
142
143			`input clk;`
144			`input rst;`
145			`input rx;`
146
147	10	mohor	`/* Mode register */`
148	2	mohor	`input reset_mode;`
149
150			`/* Bus Timing 0 register */`
151			`input [5:0] baud_r_presc;`
152			`input [1:0] sync_jump_width;`
153
154			`/* Bus Timing 1 register */`
155			`input [3:0] time_segment1;`
156			`input [2:0] time_segment2;`
157			`input triple_sampling;`
158
159	10	mohor	`/* Output from can_bsp module */`
160			`input rx_idle;`
161	24	mohor	`input transmitting;`
162	75	mohor	`input overjump_sync_seg;`
163	29	mohor	`input last_bit_of_inter;`
164	10	mohor
165	2	mohor	`/* Output signals from this module */`
166			`output clk_en;`
167	10	mohor	`output sample_point;`
168			`output sampled_bit;`
169			`output sampled_bit_q;`
170	24	mohor	`output tx_point;`
171	11	mohor	`output hard_sync;`
172	75	mohor	`output go_seg1;`
173	2	mohor
174
175
176			`reg [8:0] clk_cnt;`
177			`reg clk_en;`
178	5	mohor	`reg sync_blocked;`
179	24	mohor	`reg resync_blocked;`
180	2	mohor	`reg sampled_bit;`
181	10	mohor	`reg sampled_bit_q;`
182	76	mohor	`reg [4:0] quant_cnt;`
183	6	mohor	`reg [3:0] delay;`
184			`reg sync;`
185			`reg seg1;`
186			`reg seg2;`
187			`reg resync_latched;`
188	10	mohor	`reg sample_point;`
189	7	mohor	`reg [1:0] sample;`
190	76	mohor	`reg go_sync;`
191	2	mohor
192	76	mohor	`wire go_sync_unregistered;`
193	6	mohor	`wire go_seg1;`
194			`wire go_seg2;`
195			`wire [8:0] preset_cnt;`
196			`wire sync_window;`
197	75	mohor	`wire resync;`
198	76	mohor	`wire quant_cnt_rst1;`
199			`wire quant_cnt_rst2;`
200	2	mohor
201	5	mohor
202	76	mohor
203	6	mohor	`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
204	29	mohor	`assign hard_sync = (rx_idle \| last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting); // Hard synchronization`
205			`assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting); // Re-synchronization`
206	5	mohor
207
208	6	mohor	`/* Generating general enable signal that defines baud rate. */`
209	2	mohor	`always @ (posedge clk or posedge rst)`
210			`begin`
211			`if (rst)`
212	10	mohor	`clk_cnt <= 0;`
213	76	mohor	`else if (clk_cnt == (preset_cnt-1'b1))`
214	10	mohor	`clk_cnt <=#Tp 0;`
215			`else`
216	76	mohor	`clk_cnt <=#Tp clk_cnt + 1'b1;`
217	10	mohor	`end`
218
219
220			`always @ (posedge clk or posedge rst)`
221			`begin`
222			`if (rst)`
223			`clk_en <= 1'b0;`
224	76	mohor	`else if (clk_cnt == (preset_cnt-1'b1))`
225	10	mohor	`clk_en <=#Tp 1'b1;`
226	2	mohor	`else`
227	10	mohor	`clk_en <=#Tp 1'b0;`
228	2	mohor	`end`
229
230
231	5	mohor
232	6	mohor	`/* Changing states */`
233	76	mohor	`assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));`
234	10	mohor	`assign go_seg1 = clk_en & (sync \| hard_sync \| (resync & seg2 & sync_window) \| (resync_latched & sync_window));`
235			`assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));`
236	5	mohor
237
238	10	mohor
239	76	mohor	`always @ (posedge clk or posedge rst)`
240			`begin`
241			`if (rst)`
242			`go_sync <= 1'b0;`
243			`else`
244			`go_sync <=#Tp go_sync_unregistered;`
245			`end`
246
247
248	6	mohor	`/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when`
249			`SJW is reached */`
250	2	mohor	`always @ (posedge clk or posedge rst)`
251			`begin`
252			`if (rst)`
253	5	mohor	`resync_latched <= 1'b0;`
254	6	mohor	`else if (resync & seg2 & (~sync_window))`
255	5	mohor	`resync_latched <=#Tp 1'b1;`
256			`else if (go_seg1)`
257			`resync_latched <= 1'b0;`
258			`end`
259
260
261
262	6	mohor	`/* Synchronization stage/segment */`
263	5	mohor	`always @ (posedge clk or posedge rst)`
264			`begin`
265			`if (rst)`
266	10	mohor	`sync <= 0;`
267	5	mohor	`else if (go_sync)`
268			`sync <=#Tp 1'b1;`
269	76	mohor	`else`
270	5	mohor	`sync <=#Tp 1'b0;`
271			`end`
272
273
274	24	mohor	`assign tx_point = go_sync;`
275
276	6	mohor	`/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */`
277	5	mohor	`always @ (posedge clk or posedge rst)`
278			`begin`
279			`if (rst)`
280	10	mohor	`seg1 <= 1;`
281	5	mohor	`else if (go_seg1)`
282			`seg1 <=#Tp 1'b1;`
283			`else if (go_seg2)`
284			`seg1 <=#Tp 1'b0;`
285			`end`
286
287
288	6	mohor	`/* Seg2 stage/segment */`
289	5	mohor	`always @ (posedge clk or posedge rst)`
290			`begin`
291			`if (rst)`
292			`seg2 <= 0;`
293			`else if (go_seg2)`
294			`seg2 <=#Tp 1'b1;`
295			`else if (go_sync \| go_seg1)`
296			`seg2 <=#Tp 1'b0;`
297			`end`
298
299
300	6	mohor	`/* Quant counter */`
301	76	mohor
302			`assign quant_cnt_rst1 = go_sync \| go_seg1 & (~overjump_sync_seg) \| go_seg2;`
303			`assign quant_cnt_rst2 = go_seg1 & overjump_sync_seg;`
304	5	mohor	`always @ (posedge clk or posedge rst)`
305			`begin`
306			`if (rst)`
307			`quant_cnt <= 0;`
308	76	mohor	`else if (quant_cnt_rst1)`
309	5	mohor	`quant_cnt <=#Tp 0;`
310	76	mohor	`else if (quant_cnt_rst2)`
311	75	mohor	`quant_cnt <=#Tp 1;`
312	5	mohor	`else if (clk_en)`
313			`quant_cnt <=#Tp quant_cnt + 1'b1;`
314			`end`
315
316
317	6	mohor	`/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */`
318	5	mohor	`always @ (posedge clk or posedge rst)`
319			`begin`
320			`if (rst)`
321	6	mohor	`delay <= 0;`
322	5	mohor	`else if (clk_en & resync & seg1)`
323	76	mohor	`delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);`
324	5	mohor	`else if (go_sync \| go_seg1)`
325	6	mohor	`delay <=#Tp 0;`
326	5	mohor	`end`
327
328
329	6	mohor	`// If early edge appears within this window (in seg2 stage), phase error is fully compensated`
330	76	mohor	`assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));`
331	5	mohor
332
333	7	mohor	`// Sampling data (memorizing two samples all the time).`
334	5	mohor	`always @ (posedge clk or posedge rst)`
335			`begin`
336			`if (rst)`
337	7	mohor	`sample <= 2'b11;`
338			`else if (clk_en)`
339			`sample <= {sample[0], rx};`
340			`end`
341
342
343			`// When enabled, tripple sampling is done here.`
344			`always @ (posedge clk or posedge rst)`
345			`begin`
346			`if (rst)`
347	2	mohor	`begin`
348			`sampled_bit <= 1;`
349	10	mohor	`sampled_bit_q <= 1;`
350			`sample_point <= 0;`
351	2	mohor	`end`
352	15	mohor	`else if (clk_en & (~hard_sync))`
353	2	mohor	`begin`
354	7	mohor	`if (seg1 & (quant_cnt == (time_segment1 + delay)))`
355			`begin`
356	10	mohor	`sample_point <=#Tp 1;`
357			`sampled_bit_q <=#Tp sampled_bit;`
358	7	mohor	`if (triple_sampling)`
359			`sampled_bit <=#Tp (sample[0] & sample[1]) \| ( sample[0] & rx) \| (sample[1] & rx);`
360			`else`
361			`sampled_bit <=#Tp rx;`
362			`end`
363	2	mohor	`end`
364	5	mohor	`else`
365	10	mohor	`sample_point <=#Tp 0;`
366	2	mohor	`end`
367
368
369
370	5	mohor	`/* Blocking synchronization (can occur only once in a bit time) */`
371	35	mohor
372	5	mohor	`always @ (posedge clk or posedge rst)`
373			`begin`
374			`if (rst)`
375			`sync_blocked <=#Tp 1'b0;`
376			`else if (clk_en)`
377			`begin`
378	35	mohor	`if (hard_sync \| resync)`
379	5	mohor	`sync_blocked <=#Tp 1'b1;`
380	76	mohor	`else if (seg2 & (quant_cnt[2:0] == time_segment2))`
381	5	mohor	`sync_blocked <=#Tp 1'b0;`
382			`end`
383			`end`
384	2	mohor
385
386	24	mohor	`/* Blocking resynchronization until reception starts (needed because after reset mode exits we are waiting for`
387			`end-of-frame and interframe. No resynchronization is needed meanwhile). */`
388			`always @ (posedge clk or posedge rst)`
389			`begin`
390			`if (rst)`
391			`resync_blocked <=#Tp 1'b1;`
392			`else if (reset_mode)`
393			`resync_blocked <=#Tp 1'b1;`
394			`else if (hard_sync)`
395			`resync_blocked <=#Tp 1'b0;`
396			`end`
397	2	mohor
398
399	5	mohor
400	24	mohor
401
402	2	mohor	`endmodule`

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