URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_btl.v] - Blame information for rev 102

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.21  2003/07/03 09:32:20  mohor
// Synchronization changed.
//
// Revision 1.20  2003/06/20 14:51:11  mohor
// Previous change removed. When resynchronization occurs we go to seg1
// stage. sync stage does not cause another start of seg1 stage.
//
// Revision 1.19  2003/06/20 14:28:20  mohor
// When hard_sync or resync occure we need to go to seg1 segment. Going to
// sync segment is in that case blocked.
//
// Revision 1.18  2003/06/17 15:53:33  mohor
// clk_cnt reduced from [8:0] to [6:0].
//
// Revision 1.17  2003/06/17 14:32:17  mohor
// Removed few signals.
//
// Revision 1.16  2003/06/16 13:57:58  mohor
// tx_point generated one clk earlier. rx_i registered. Data corrected when
// using extended mode.
//
// Revision 1.15  2003/06/13 15:02:24  mohor
// Synchronization is also needed when transmitting a message.
//
// Revision 1.14  2003/06/13 14:55:11  mohor
// Counters width changed.
//
// Revision 1.13  2003/06/11 14:21:35  mohor
// When switching to tx, sync stage is overjumped.
//
// Revision 1.12  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.11  2003/02/09 18:40:29  mohor
// Overload fixed. Hard synchronization also enabled at the last bit of
// interframe.
//
// Revision 1.10  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.9  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.8  2003/01/10 17:51:34  mohor
// Temporary version (backup).
//
// Revision 1.7  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.6  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.5  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.4  2002/12/26 01:33:05  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:16  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:17:00  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  sample_point,
  sampled_bit,
  sampled_bit_q,
  tx_point,
  hard_sync,
 
  /* Output from can_bsp module */
  rx_idle,
  last_bit_of_inter,
  transmitting,
  go_rx_inter
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
 
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output from can_bsp module */
input         rx_idle;
input         last_bit_of_inter;
input         transmitting;
input         go_rx_inter;
 
/* Output signals from this module */
output        sample_point;
output        sampled_bit;
output        sampled_bit_q;
output        tx_point;
output        hard_sync;
 
 
 
reg     [6:0] clk_cnt;
reg           clk_en;
reg           clk_en_q;
reg           sync_blocked;
reg           hard_sync_blocked;
reg           sampled_bit;
reg           sampled_bit_q;
reg     [4:0] quant_cnt;
reg     [3:0] delay;
reg           sync;
reg           seg1;
reg           seg2;
reg           resync_latched;
reg           sample_point;
reg     [1:0] sample;
reg           go_sync;
reg           go_seg1;
reg           go_seg2;
reg           tx_point;
 
wire          go_sync_unregistered;
wire          go_seg1_unregistered;
wire          go_seg2_unregistered;
wire [8:0]    preset_cnt;
wire          sync_window;
wire          resync;
wire          quant_cnt_rst;
 
 
 
assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
assign hard_sync  =   (rx_idle | last_bit_of_inter)    & (~rx) & sampled_bit & (~hard_sync_blocked);  // Hard synchronization
assign resync     =  (~rx_idle) & (~last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~(transmitting & seg1));       // Re-synchronization
 
 
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_cnt <= 0;
  else if (clk_cnt >= (preset_cnt-1'b1))
    clk_cnt <=#Tp 0;
  else
    clk_cnt <=#Tp clk_cnt + 1'b1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en  <= 1'b0;
  else if (clk_cnt == (preset_cnt-1'b1))
    clk_en  <=#Tp 1'b1;
  else
    clk_en  <=#Tp 1'b0;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en_q  <= 1'b0;
  else
    clk_en_q  <=#Tp clk_en;
end
 
 
 
/* Changing states */
 assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));
 assign go_seg1_unregistered = clk_en & (((sync | hard_sync) & (~seg1)) | (resync & seg2 & sync_window) | (resync_latched & sync_window));
 assign go_seg2_unregistered = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    go_sync <= 1'b0;
  else
    go_sync <=#Tp go_sync_unregistered;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    go_seg1 <= 1'b0;
  else
    go_seg1 <=#Tp go_seg1_unregistered;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    go_seg2 <= 1'b0;
  else
    go_seg2 <=#Tp go_seg2_unregistered;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    tx_point <= 1'b0;
  else
    tx_point <=#Tp go_sync_unregistered | (go_seg1_unregistered & (~(sync | hard_sync)));
end
 
 
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
   SJW is reached */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_latched <= 1'b0;
  else if (resync & seg2 & (~sync_window))
    resync_latched <=#Tp 1'b1;
  else if (go_seg1)
    resync_latched <= 1'b0;
end
 
 
 
/* Synchronization stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync <= 0;
  else if (go_sync)
    sync <=#Tp 1'b1;
  else if (clk_en_q)
    sync <=#Tp 1'b0;
end
 
 
/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg1 <= 1;
  else if (go_seg1)
    seg1 <=#Tp 1'b1;
  else if (go_seg2)
    seg1 <=#Tp 1'b0;
end
 
 
/* Seg2 stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg2 <= 0;
  else if (go_seg2)
    seg2 <=#Tp 1'b1;
  else if (go_sync | go_seg1)
    seg2 <=#Tp 1'b0;
end
 
 
/* Quant counter */
assign quant_cnt_rst = go_sync | go_seg1 | go_seg2;
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    quant_cnt <= 0;
  else if (quant_cnt_rst)
    quant_cnt <=#Tp 0;
  else if (clk_en_q)
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
 
 
/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    delay <= 0;
  else if (clk_en_q & resync & seg1)
    delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);
  else if (go_sync | go_seg1)
    delay <=#Tp 0;
end
 
 
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
 
 
// Sampling data (memorizing two samples all the time).
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sample <= 2'b11;
  else if (clk_en_q)
    sample <= {sample[0], rx};
end
 
 
// When enabled, tripple sampling is done here.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1;
      sampled_bit_q <= 1;
      sample_point <= 0;
    end
  else if (clk_en_q & (~hard_sync))
    begin
      if (seg1 & (quant_cnt == (time_segment1 + delay)))
        begin
          sample_point <=#Tp 1;
          sampled_bit_q <=#Tp sampled_bit;
          if (triple_sampling)
            sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
          else
            sampled_bit <=#Tp rx;
        end
    end
  else
    sample_point <=#Tp 0;
end
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync_blocked <=#Tp 1'b0;
  else if (clk_en_q)
    begin
      if (resync)
        sync_blocked <=#Tp 1'b1;
      else if (seg2 & (quant_cnt[2:0] == time_segment2))
        sync_blocked <=#Tp 1'b0;
    end
end
 
 
/* Blocking hard synchronization when occurs once or when we are transmitting a msg */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    hard_sync_blocked <=#Tp 1'b0;
  else if (hard_sync | transmitting & tx_point)
    hard_sync_blocked <=#Tp 1'b1;
  else if (go_rx_inter)
    hard_sync_blocked <=#Tp 1'b0;
end
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	2	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	102	mohor	`// Revision 1.21 2003/07/03 09:32:20 mohor`
54			`// Synchronization changed.`
55			`//`
56	100	mohor	`// Revision 1.20 2003/06/20 14:51:11 mohor`
57			`// Previous change removed. When resynchronization occurs we go to seg1`
58			`// stage. sync stage does not cause another start of seg1 stage.`
59			`//`
60	88	mohor	`// Revision 1.19 2003/06/20 14:28:20 mohor`
61			`// When hard_sync or resync occure we need to go to seg1 segment. Going to`
62			`// sync segment is in that case blocked.`
63			`//`
64	87	mohor	`// Revision 1.18 2003/06/17 15:53:33 mohor`
65			`// clk_cnt reduced from [8:0] to [6:0].`
66			`//`
67	84	mohor	`// Revision 1.17 2003/06/17 14:32:17 mohor`
68			`// Removed few signals.`
69			`//`
70	82	mohor	`// Revision 1.16 2003/06/16 13:57:58 mohor`
71			`// tx_point generated one clk earlier. rx_i registered. Data corrected when`
72			`// using extended mode.`
73			`//`
74	78	mohor	`// Revision 1.15 2003/06/13 15:02:24 mohor`
75			`// Synchronization is also needed when transmitting a message.`
76			`//`
77	77	mohor	`// Revision 1.14 2003/06/13 14:55:11 mohor`
78			`// Counters width changed.`
79			`//`
80	76	mohor	`// Revision 1.13 2003/06/11 14:21:35 mohor`
81			`// When switching to tx, sync stage is overjumped.`
82			`//`
83	75	mohor	`// Revision 1.12 2003/02/14 20:17:01 mohor`
84			`// Several registers added. Not finished, yet.`
85			`//`
86	35	mohor	`// Revision 1.11 2003/02/09 18:40:29 mohor`
87			`// Overload fixed. Hard synchronization also enabled at the last bit of`
88			`// interframe.`
89			`//`
90	29	mohor	`// Revision 1.10 2003/02/09 02:24:33 mohor`
91			`// Bosch license warning added. Error counters finished. Overload frames`
92			`// still need to be fixed.`
93			`//`
94	28	mohor	`// Revision 1.9 2003/01/31 01:13:38 mohor`
95			`// backup.`
96			`//`
97	24	mohor	`// Revision 1.8 2003/01/10 17:51:34 mohor`
98			`// Temporary version (backup).`
99			`//`
100	15	mohor	`// Revision 1.7 2003/01/08 02:10:53 mohor`
101			`// Acceptance filter added.`
102			`//`
103	11	mohor	`// Revision 1.6 2002/12/28 04:13:23 mohor`
104			`// Backup version.`
105			`//`
106	10	mohor	`// Revision 1.5 2002/12/27 00:12:52 mohor`
107			`// Header changed, testbench improved to send a frame (crc still missing).`
108			`//`
109	9	mohor	`// Revision 1.4 2002/12/26 01:33:05 mohor`
110			`// Tripple sampling supported.`
111			`//`
112	7	mohor	`// Revision 1.3 2002/12/25 23:44:16 mohor`
113			`// Commented lines removed.`
114			`//`
115	6	mohor	`// Revision 1.2 2002/12/25 14:17:00 mohor`
116			`// Synchronization working.`
117			`//`
118	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
119			`// Initial`
120	2	mohor	`//`
121			`//`
122	5	mohor	`//`
123	2	mohor
124			`// synopsys translate_off`
125			`include "timescale.v"
126			`// synopsys translate_on`
127			`include "can_defines.v"
128
129			`module can_btl`
130			`(`
131			`clk,`
132			`rst,`
133			`rx,`
134
135			`/* Bus Timing 0 register */`
136			`baud_r_presc,`
137			`sync_jump_width,`
138
139			`/* Bus Timing 1 register */`
140			`time_segment1,`
141			`time_segment2,`
142			`triple_sampling,`
143
144			`/* Output signals from this module */`
145	10	mohor	`sample_point,`
146			`sampled_bit,`
147			`sampled_bit_q,`
148	24	mohor	`tx_point,`
149	11	mohor	`hard_sync,`
150	2	mohor
151	10	mohor	`/* Output from can_bsp module */`
152	24	mohor	`rx_idle,`
153	100	mohor	`last_bit_of_inter,`
154			`transmitting,`
155			`go_rx_inter`
156	2	mohor
157			`);`
158
159			`parameter Tp = 1;`
160
161			`input clk;`
162			`input rst;`
163			`input rx;`
164
165
166			`/* Bus Timing 0 register */`
167			`input [5:0] baud_r_presc;`
168			`input [1:0] sync_jump_width;`
169
170			`/* Bus Timing 1 register */`
171			`input [3:0] time_segment1;`
172			`input [2:0] time_segment2;`
173			`input triple_sampling;`
174
175	10	mohor	`/* Output from can_bsp module */`
176			`input rx_idle;`
177	29	mohor	`input last_bit_of_inter;`
178	100	mohor	`input transmitting;`
179			`input go_rx_inter;`
180	10	mohor
181	2	mohor	`/* Output signals from this module */`
182	10	mohor	`output sample_point;`
183			`output sampled_bit;`
184			`output sampled_bit_q;`
185	24	mohor	`output tx_point;`
186	11	mohor	`output hard_sync;`
187	2	mohor
188
189
190	84	mohor	`reg [6:0] clk_cnt;`
191	2	mohor	`reg clk_en;`
192	78	mohor	`reg clk_en_q;`
193	5	mohor	`reg sync_blocked;`
194	100	mohor	`reg hard_sync_blocked;`
195	2	mohor	`reg sampled_bit;`
196	10	mohor	`reg sampled_bit_q;`
197	76	mohor	`reg [4:0] quant_cnt;`
198	6	mohor	`reg [3:0] delay;`
199			`reg sync;`
200			`reg seg1;`
201			`reg seg2;`
202			`reg resync_latched;`
203	10	mohor	`reg sample_point;`
204	7	mohor	`reg [1:0] sample;`
205	76	mohor	`reg go_sync;`
206	100	mohor	`reg go_seg1;`
207			`reg go_seg2;`
208			`reg tx_point;`
209	2	mohor
210	76	mohor	`wire go_sync_unregistered;`
211	100	mohor	`wire go_seg1_unregistered;`
212			`wire go_seg2_unregistered;`
213	6	mohor	`wire [8:0] preset_cnt;`
214			`wire sync_window;`
215	75	mohor	`wire resync;`
216	82	mohor	`wire quant_cnt_rst;`
217	2	mohor
218	5	mohor
219	76	mohor
220	6	mohor	`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
221	100	mohor	`assign hard_sync = (rx_idle \| last_bit_of_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization`
222			`assign resync = (~rx_idle) & (~last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~(transmitting & seg1)); // Re-synchronization`
223	5	mohor
224
225	6	mohor	`/* Generating general enable signal that defines baud rate. */`
226	2	mohor	`always @ (posedge clk or posedge rst)`
227			`begin`
228			`if (rst)`
229	10	mohor	`clk_cnt <= 0;`
230	78	mohor	`else if (clk_cnt >= (preset_cnt-1'b1))`
231	10	mohor	`clk_cnt <=#Tp 0;`
232			`else`
233	76	mohor	`clk_cnt <=#Tp clk_cnt + 1'b1;`
234	10	mohor	`end`
235
236
237			`always @ (posedge clk or posedge rst)`
238			`begin`
239			`if (rst)`
240			`clk_en <= 1'b0;`
241	76	mohor	`else if (clk_cnt == (preset_cnt-1'b1))`
242	10	mohor	`clk_en <=#Tp 1'b1;`
243	2	mohor	`else`
244	10	mohor	`clk_en <=#Tp 1'b0;`
245	2	mohor	`end`
246
247
248	5	mohor
249	78	mohor	`always @ (posedge clk or posedge rst)`
250			`begin`
251			`if (rst)`
252			`clk_en_q <= 1'b0;`
253			`else`
254			`clk_en_q <=#Tp clk_en;`
255			`end`
256
257
258
259	6	mohor	`/* Changing states */`
260	76	mohor	`assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));`
261	100	mohor	`assign go_seg1_unregistered = clk_en & (((sync \| hard_sync) & (~seg1)) \| (resync & seg2 & sync_window) \| (resync_latched & sync_window));`
262			`assign go_seg2_unregistered = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));`
263	5	mohor
264
265	76	mohor	`always @ (posedge clk or posedge rst)`
266			`begin`
267			`if (rst)`
268			`go_sync <= 1'b0;`
269			`else`
270	88	mohor	`go_sync <=#Tp go_sync_unregistered;`
271	76	mohor	`end`
272
273
274	100	mohor	`always @ (posedge clk or posedge rst)`
275			`begin`
276			`if (rst)`
277			`go_seg1 <= 1'b0;`
278			`else`
279			`go_seg1 <=#Tp go_seg1_unregistered;`
280			`end`
281
282
283			`always @ (posedge clk or posedge rst)`
284			`begin`
285			`if (rst)`
286			`go_seg2 <= 1'b0;`
287			`else`
288			`go_seg2 <=#Tp go_seg2_unregistered;`
289			`end`
290
291
292			`always @ (posedge clk or posedge rst)`
293			`begin`
294			`if (rst)`
295			`tx_point <= 1'b0;`
296			`else`
297			`tx_point <=#Tp go_sync_unregistered \| (go_seg1_unregistered & (~(sync \| hard_sync)));`
298			`end`
299
300
301	6	mohor	`/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when`
302			`SJW is reached */`
303	2	mohor	`always @ (posedge clk or posedge rst)`
304			`begin`
305			`if (rst)`
306	5	mohor	`resync_latched <= 1'b0;`
307	6	mohor	`else if (resync & seg2 & (~sync_window))`
308	5	mohor	`resync_latched <=#Tp 1'b1;`
309			`else if (go_seg1)`
310			`resync_latched <= 1'b0;`
311			`end`
312
313
314
315	6	mohor	`/* Synchronization stage/segment */`
316	5	mohor	`always @ (posedge clk or posedge rst)`
317			`begin`
318			`if (rst)`
319	10	mohor	`sync <= 0;`
320	5	mohor	`else if (go_sync)`
321			`sync <=#Tp 1'b1;`
322	78	mohor	`else if (clk_en_q)`
323	5	mohor	`sync <=#Tp 1'b0;`
324			`end`
325
326
327	6	mohor	`/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */`
328	5	mohor	`always @ (posedge clk or posedge rst)`
329			`begin`
330			`if (rst)`
331	10	mohor	`seg1 <= 1;`
332	5	mohor	`else if (go_seg1)`
333			`seg1 <=#Tp 1'b1;`
334			`else if (go_seg2)`
335			`seg1 <=#Tp 1'b0;`
336			`end`
337
338
339	6	mohor	`/* Seg2 stage/segment */`
340	5	mohor	`always @ (posedge clk or posedge rst)`
341			`begin`
342			`if (rst)`
343			`seg2 <= 0;`
344			`else if (go_seg2)`
345			`seg2 <=#Tp 1'b1;`
346			`else if (go_sync \| go_seg1)`
347			`seg2 <=#Tp 1'b0;`
348			`end`
349
350
351	6	mohor	`/* Quant counter */`
352	82	mohor	`assign quant_cnt_rst = go_sync \| go_seg1 \| go_seg2;`
353	76	mohor
354	5	mohor	`always @ (posedge clk or posedge rst)`
355			`begin`
356			`if (rst)`
357			`quant_cnt <= 0;`
358	82	mohor	`else if (quant_cnt_rst)`
359	5	mohor	`quant_cnt <=#Tp 0;`
360	78	mohor	`else if (clk_en_q)`
361	5	mohor	`quant_cnt <=#Tp quant_cnt + 1'b1;`
362			`end`
363
364
365	6	mohor	`/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */`
366	5	mohor	`always @ (posedge clk or posedge rst)`
367			`begin`
368			`if (rst)`
369	6	mohor	`delay <= 0;`
370	78	mohor	`else if (clk_en_q & resync & seg1)`
371	76	mohor	`delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);`
372	5	mohor	`else if (go_sync \| go_seg1)`
373	6	mohor	`delay <=#Tp 0;`
374	5	mohor	`end`
375
376
377	6	mohor	`// If early edge appears within this window (in seg2 stage), phase error is fully compensated`
378	76	mohor	`assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));`
379	5	mohor
380
381	7	mohor	`// Sampling data (memorizing two samples all the time).`
382	5	mohor	`always @ (posedge clk or posedge rst)`
383			`begin`
384			`if (rst)`
385	7	mohor	`sample <= 2'b11;`
386	78	mohor	`else if (clk_en_q)`
387	7	mohor	`sample <= {sample[0], rx};`
388			`end`
389
390
391			`// When enabled, tripple sampling is done here.`
392			`always @ (posedge clk or posedge rst)`
393			`begin`
394			`if (rst)`
395	2	mohor	`begin`
396			`sampled_bit <= 1;`
397	10	mohor	`sampled_bit_q <= 1;`
398			`sample_point <= 0;`
399	2	mohor	`end`
400	78	mohor	`else if (clk_en_q & (~hard_sync))`
401	2	mohor	`begin`
402	7	mohor	`if (seg1 & (quant_cnt == (time_segment1 + delay)))`
403			`begin`
404	10	mohor	`sample_point <=#Tp 1;`
405			`sampled_bit_q <=#Tp sampled_bit;`
406	7	mohor	`if (triple_sampling)`
407			`sampled_bit <=#Tp (sample[0] & sample[1]) \| ( sample[0] & rx) \| (sample[1] & rx);`
408			`else`
409			`sampled_bit <=#Tp rx;`
410			`end`
411	2	mohor	`end`
412	5	mohor	`else`
413	10	mohor	`sample_point <=#Tp 0;`
414	2	mohor	`end`
415
416
417
418	5	mohor	`/* Blocking synchronization (can occur only once in a bit time) */`
419	35	mohor
420	5	mohor	`always @ (posedge clk or posedge rst)`
421			`begin`
422			`if (rst)`
423			`sync_blocked <=#Tp 1'b0;`
424	78	mohor	`else if (clk_en_q)`
425	5	mohor	`begin`
426	100	mohor	`if (resync)`
427	5	mohor	`sync_blocked <=#Tp 1'b1;`
428	76	mohor	`else if (seg2 & (quant_cnt[2:0] == time_segment2))`
429	5	mohor	`sync_blocked <=#Tp 1'b0;`
430			`end`
431			`end`
432	2	mohor
433
434	100	mohor	`/* Blocking hard synchronization when occurs once or when we are transmitting a msg */`
435	24	mohor	`always @ (posedge clk or posedge rst)`
436			`begin`
437			`if (rst)`
438	100	mohor	`hard_sync_blocked <=#Tp 1'b0;`
439			`else if (hard_sync \| transmitting & tx_point)`
440			`hard_sync_blocked <=#Tp 1'b1;`
441			`else if (go_rx_inter)`
442			`hard_sync_blocked <=#Tp 1'b0;`
443	24	mohor	`end`
444	2	mohor
445
446	5	mohor
447	24	mohor
448
449	2	mohor	`endmodule`

Browse

Tools

Subversion Repositories can

[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_btl.v] - Blame information for rev 102