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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.5  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.4  2002/12/26 01:33:05  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:16  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:17:00  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
 
  /* Mode register */
  reset_mode,
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  clk_en,
  sample_point,
  sampled_bit,
  sampled_bit_q,
  hard_sync,
  resync,
 
  /* Output from can_bsp module */
  rx_idle
 
 
 
 
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
 
  /* Mode register */
input         reset_mode;
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output from can_bsp module */
input         rx_idle;
 
/* Output signals from this module */
output        clk_en;
output        sample_point;
output        sampled_bit;
output        sampled_bit_q;
output        hard_sync;
output        resync;
 
 
 
reg     [8:0] clk_cnt;
reg           clk_en;
reg           sync_blocked;
reg           sampled_bit;
reg           sampled_bit_q;
reg     [7:0] quant_cnt;
reg     [3:0] delay;
reg           sync;
reg           seg1;
reg           seg2;
reg           resync_latched;
reg           sample_point;
reg     [1:0] sample;
 
wire          go_sync;
wire          go_seg1;
wire          go_seg2;
wire [8:0]    preset_cnt;
wire          sync_window;
 
 
 
assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
assign hard_sync  =   rx_idle  & (~rx) & sampled_bit & (~sync_blocked);  // Hard synchronization
assign resync     = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked);  // Re-synchronization
 
 
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_cnt <= 0;
  else if (clk_cnt == (preset_cnt-1) | reset_mode)
    clk_cnt <=#Tp 0;
  else
    clk_cnt <=#Tp clk_cnt + 1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en  <= 1'b0;
  else if (clk_cnt == (preset_cnt-1))
    clk_en  <=#Tp 1'b1;
  else
    clk_en  <=#Tp 1'b0;
end
 
 
 
/* Changing states */
 assign go_sync = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt == time_segment2)));
 assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
 assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
 
 
 
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
   SJW is reached */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_latched <= 1'b0;
  else if (resync & seg2 & (~sync_window))
    resync_latched <=#Tp 1'b1;
  else if (go_seg1)
    resync_latched <= 1'b0;
end
 
 
 
/* Synchronization stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync <= 0;
  else if (go_sync)
    sync <=#Tp 1'b1;
  else if (go_seg1)
    sync <=#Tp 1'b0;
end
 
 
/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg1 <= 1;
  else if (go_seg1)
    seg1 <=#Tp 1'b1;
  else if (go_seg2)
    seg1 <=#Tp 1'b0;
end
 
 
/* Seg2 stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg2 <= 0;
  else if (go_seg2)
    seg2 <=#Tp 1'b1;
  else if (go_sync | go_seg1)
    seg2 <=#Tp 1'b0;
end
 
 
/* Quant counter */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    quant_cnt <= 0;
  else if (go_sync || go_seg1 || go_seg2)
    quant_cnt <=#Tp 0;
  else if (clk_en)
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
 
 
/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    delay <= 0;
  else if (clk_en & resync & seg1)
    delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);
  else if (go_sync | go_seg1)
    delay <=#Tp 0;
end
 
 
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));
 
 
// Sampling data (memorizing two samples all the time).
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sample <= 2'b11;
  else if (clk_en)
    sample <= {sample[0], rx};
end
 
 
// When enabled, tripple sampling is done here.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1;
      sampled_bit_q <= 1;
      sample_point <= 0;
    end
  else if (clk_en)
    begin
      if (seg1 & (quant_cnt == (time_segment1 + delay)))
        begin
          sample_point <=#Tp 1;
          sampled_bit_q <=#Tp sampled_bit;
          if (triple_sampling)
            sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
          else
            sampled_bit <=#Tp rx;
        end
    end
  else
    sample_point <=#Tp 0;
end
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync_blocked <=#Tp 1'b0;
  else if (clk_en)
    begin
      if (hard_sync || resync)
        sync_blocked <=#Tp 1'b1;
      else if (seg2 & quant_cnt == time_segment2)
        sync_blocked <=#Tp 1'b0;
    end
end
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	11	mohor	`// Revision 1.6 2002/12/28 04:13:23 mohor`
49			`// Backup version.`
50			`//`
51	10	mohor	`// Revision 1.5 2002/12/27 00:12:52 mohor`
52			`// Header changed, testbench improved to send a frame (crc still missing).`
53			`//`
54	9	mohor	`// Revision 1.4 2002/12/26 01:33:05 mohor`
55			`// Tripple sampling supported.`
56			`//`
57	7	mohor	`// Revision 1.3 2002/12/25 23:44:16 mohor`
58			`// Commented lines removed.`
59			`//`
60	6	mohor	`// Revision 1.2 2002/12/25 14:17:00 mohor`
61			`// Synchronization working.`
62			`//`
63	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
64			`// Initial`
65	2	mohor	`//`
66			`//`
67	5	mohor	`//`
68	2	mohor
69			`// synopsys translate_off`
70			`include "timescale.v"
71			`// synopsys translate_on`
72			`include "can_defines.v"
73
74			`module can_btl`
75			`(`
76			`clk,`
77			`rst,`
78			`rx,`
79
80			`/* Mode register */`
81	10	mohor	`reset_mode,`
82	2	mohor
83			`/* Bus Timing 0 register */`
84			`baud_r_presc,`
85			`sync_jump_width,`
86
87			`/* Bus Timing 1 register */`
88			`time_segment1,`
89			`time_segment2,`
90			`triple_sampling,`
91
92			`/* Output signals from this module */`
93			`clk_en,`
94	10	mohor	`sample_point,`
95			`sampled_bit,`
96			`sampled_bit_q,`
97	11	mohor	`hard_sync,`
98			`resync,`
99	2	mohor
100	10	mohor	`/* Output from can_bsp module */`
101			`rx_idle`
102	2	mohor
103	10	mohor
104	11	mohor
105	2	mohor
106
107			`);`
108
109			`parameter Tp = 1;`
110
111			`input clk;`
112			`input rst;`
113			`input rx;`
114
115	10	mohor	`/* Mode register */`
116	2	mohor	`input reset_mode;`
117
118			`/* Bus Timing 0 register */`
119			`input [5:0] baud_r_presc;`
120			`input [1:0] sync_jump_width;`
121
122			`/* Bus Timing 1 register */`
123			`input [3:0] time_segment1;`
124			`input [2:0] time_segment2;`
125			`input triple_sampling;`
126
127	10	mohor	`/* Output from can_bsp module */`
128			`input rx_idle;`
129
130	2	mohor	`/* Output signals from this module */`
131			`output clk_en;`
132	10	mohor	`output sample_point;`
133			`output sampled_bit;`
134			`output sampled_bit_q;`
135	11	mohor	`output hard_sync;`
136			`output resync;`
137	2	mohor
138
139
140			`reg [8:0] clk_cnt;`
141			`reg clk_en;`
142	5	mohor	`reg sync_blocked;`
143	2	mohor	`reg sampled_bit;`
144	10	mohor	`reg sampled_bit_q;`
145	2	mohor	`reg [7:0] quant_cnt;`
146	6	mohor	`reg [3:0] delay;`
147			`reg sync;`
148			`reg seg1;`
149			`reg seg2;`
150			`reg resync_latched;`
151	10	mohor	`reg sample_point;`
152	7	mohor	`reg [1:0] sample;`
153	2	mohor
154	6	mohor	`wire go_sync;`
155			`wire go_seg1;`
156			`wire go_seg2;`
157			`wire [8:0] preset_cnt;`
158			`wire sync_window;`
159	2	mohor
160	5	mohor
161
162	6	mohor	`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
163	11	mohor	`assign hard_sync = rx_idle & (~rx) & sampled_bit & (~sync_blocked); // Hard synchronization`
164	10	mohor	`assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization`
165	5	mohor
166
167	6	mohor	`/* Generating general enable signal that defines baud rate. */`
168	2	mohor	`always @ (posedge clk or posedge rst)`
169			`begin`
170			`if (rst)`
171	10	mohor	`clk_cnt <= 0;`
172			`else if (clk_cnt == (preset_cnt-1) \| reset_mode)`
173			`clk_cnt <=#Tp 0;`
174			`else`
175			`clk_cnt <=#Tp clk_cnt + 1;`
176			`end`
177
178
179			`always @ (posedge clk or posedge rst)`
180			`begin`
181			`if (rst)`
182			`clk_en <= 1'b0;`
183	2	mohor	`else if (clk_cnt == (preset_cnt-1))`
184	10	mohor	`clk_en <=#Tp 1'b1;`
185	2	mohor	`else`
186	10	mohor	`clk_en <=#Tp 1'b0;`
187	2	mohor	`end`
188
189
190	5	mohor
191	6	mohor	`/* Changing states */`
192	10	mohor	`assign go_sync = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt == time_segment2)));`
193			`assign go_seg1 = clk_en & (sync \| hard_sync \| (resync & seg2 & sync_window) \| (resync_latched & sync_window));`
194			`assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));`
195	5	mohor
196
197	10	mohor
198	6	mohor	`/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when`
199			`SJW is reached */`
200	2	mohor	`always @ (posedge clk or posedge rst)`
201			`begin`
202			`if (rst)`
203	5	mohor	`resync_latched <= 1'b0;`
204	6	mohor	`else if (resync & seg2 & (~sync_window))`
205	5	mohor	`resync_latched <=#Tp 1'b1;`
206			`else if (go_seg1)`
207			`resync_latched <= 1'b0;`
208			`end`
209
210
211
212	6	mohor	`/* Synchronization stage/segment */`
213	5	mohor	`always @ (posedge clk or posedge rst)`
214			`begin`
215			`if (rst)`
216	10	mohor	`sync <= 0;`
217	5	mohor	`else if (go_sync)`
218			`sync <=#Tp 1'b1;`
219			`else if (go_seg1)`
220			`sync <=#Tp 1'b0;`
221			`end`
222
223
224	6	mohor	`/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */`
225	5	mohor	`always @ (posedge clk or posedge rst)`
226			`begin`
227			`if (rst)`
228	10	mohor	`seg1 <= 1;`
229	5	mohor	`else if (go_seg1)`
230			`seg1 <=#Tp 1'b1;`
231			`else if (go_seg2)`
232			`seg1 <=#Tp 1'b0;`
233			`end`
234
235
236	6	mohor	`/* Seg2 stage/segment */`
237	5	mohor	`always @ (posedge clk or posedge rst)`
238			`begin`
239			`if (rst)`
240			`seg2 <= 0;`
241			`else if (go_seg2)`
242			`seg2 <=#Tp 1'b1;`
243			`else if (go_sync \| go_seg1)`
244			`seg2 <=#Tp 1'b0;`
245			`end`
246
247
248	6	mohor	`/* Quant counter */`
249	5	mohor	`always @ (posedge clk or posedge rst)`
250			`begin`
251			`if (rst)`
252			`quant_cnt <= 0;`
253			`else if (go_sync \|\| go_seg1 \|\| go_seg2)`
254			`quant_cnt <=#Tp 0;`
255			`else if (clk_en)`
256			`quant_cnt <=#Tp quant_cnt + 1'b1;`
257			`end`
258
259
260	6	mohor	`/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */`
261	5	mohor	`always @ (posedge clk or posedge rst)`
262			`begin`
263			`if (rst)`
264	6	mohor	`delay <= 0;`
265	5	mohor	`else if (clk_en & resync & seg1)`
266	6	mohor	`delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);`
267	5	mohor	`else if (go_sync \| go_seg1)`
268	6	mohor	`delay <=#Tp 0;`
269	5	mohor	`end`
270
271
272	6	mohor	`// If early edge appears within this window (in seg2 stage), phase error is fully compensated`
273			`assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));`
274	5	mohor
275
276	7	mohor	`// Sampling data (memorizing two samples all the time).`
277	5	mohor	`always @ (posedge clk or posedge rst)`
278			`begin`
279			`if (rst)`
280	7	mohor	`sample <= 2'b11;`
281			`else if (clk_en)`
282			`sample <= {sample[0], rx};`
283			`end`
284
285
286			`// When enabled, tripple sampling is done here.`
287			`always @ (posedge clk or posedge rst)`
288			`begin`
289			`if (rst)`
290	2	mohor	`begin`
291			`sampled_bit <= 1;`
292	10	mohor	`sampled_bit_q <= 1;`
293			`sample_point <= 0;`
294	2	mohor	`end`
295	7	mohor	`else if (clk_en)`
296	2	mohor	`begin`
297	7	mohor	`if (seg1 & (quant_cnt == (time_segment1 + delay)))`
298			`begin`
299	10	mohor	`sample_point <=#Tp 1;`
300			`sampled_bit_q <=#Tp sampled_bit;`
301	7	mohor	`if (triple_sampling)`
302			`sampled_bit <=#Tp (sample[0] & sample[1]) \| ( sample[0] & rx) \| (sample[1] & rx);`
303			`else`
304			`sampled_bit <=#Tp rx;`
305			`end`
306	2	mohor	`end`
307	5	mohor	`else`
308	10	mohor	`sample_point <=#Tp 0;`
309	2	mohor	`end`
310
311
312
313	5	mohor	`/* Blocking synchronization (can occur only once in a bit time) */`
314			`always @ (posedge clk or posedge rst)`
315			`begin`
316			`if (rst)`
317			`sync_blocked <=#Tp 1'b0;`
318			`else if (clk_en)`
319			`begin`
320			`if (hard_sync \|\| resync)`
321			`sync_blocked <=#Tp 1'b1;`
322			`else if (seg2 & quant_cnt == time_segment2)`
323			`sync_blocked <=#Tp 1'b0;`
324			`end`
325			`end`
326	2	mohor
327
328
329
330	5	mohor
331	2	mohor	`endmodule`

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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_btl.v] - Blame information for rev 11