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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/12/26 01:33:05  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:16  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:17:00  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
 
  /* Mode register */
  reset_mode,           // Not used !!!
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  take_sample,
  clk_en,
 
  /* States */
  idle
 
 
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
 
/* Mode register */
input         reset_mode;
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output signals from this module */
output        take_sample;      // NOT USED, YET
output        clk_en;
 
input         idle;
 
 
reg     [8:0] clk_cnt;
reg           clk_en;
reg           sync_blocked;
reg           sampled_bit;
reg     [7:0] quant_cnt;
reg     [3:0] delay;
reg           sync;
reg           seg1;
reg           seg2;
reg           resync_latched;
reg           sample_pulse;
reg     [1:0] sample;
 
wire          go_sync;
wire          go_seg1;
wire          go_seg2;
wire [8:0]    preset_cnt;
wire          hard_sync;
wire          resync;
wire          sync_window;
 
 
 
assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
assign hard_sync  =   idle  & (~rx) & sampled_bit & (~sync_blocked);  // Hard synchronization
assign resync     = (~idle) & (~rx) & sampled_bit & (~sync_blocked);  // Re-synchronization
 
 
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      clk_cnt <= 0;
      clk_en  <= 1'b0;
    end
  else if (clk_cnt == (preset_cnt-1))
    begin
      clk_cnt <=#Tp 0;
      clk_en  <=#Tp 1'b1;
    end
  else
    begin
      clk_cnt <=#Tp clk_cnt + 1;
      clk_en  <=#Tp 1'b0;
    end
end
 
 
 
/* Changing states */
//assign go_sync = clk_en & (seg2 & (~resync) & ((quant_cnt == time_segment2)));
assign go_sync = clk_en & (seg2 & ((quant_cnt == time_segment2)));
assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
assign go_seg2 = clk_en & (seg1 & (quant_cnt == (time_segment1 + delay)));
 
 
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
   SJW is reached */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_latched <= 1'b0;
  else if (resync & seg2 & (~sync_window))
    resync_latched <=#Tp 1'b1;
  else if (go_seg1)
    resync_latched <= 1'b0;
end
 
 
 
/* Synchronization stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync <= 1;
  else if (go_sync)
    sync <=#Tp 1'b1;
  else if (go_seg1)
    sync <=#Tp 1'b0;
end
 
 
/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg1 <= 0;
  else if (go_seg1)
    seg1 <=#Tp 1'b1;
  else if (go_seg2)
    seg1 <=#Tp 1'b0;
end
 
 
/* Seg2 stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg2 <= 0;
  else if (go_seg2)
    seg2 <=#Tp 1'b1;
  else if (go_sync | go_seg1)
    seg2 <=#Tp 1'b0;
end
 
 
/* Quant counter */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    quant_cnt <= 0;
  else if (go_sync || go_seg1 || go_seg2)
    quant_cnt <=#Tp 0;
  else if (clk_en)
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
 
 
/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    delay <= 0;
  else if (clk_en & resync & seg1)
    delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);
  else if (go_sync | go_seg1)
    delay <=#Tp 0;
end
 
 
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));
 
 
// Sampling data (memorizing two samples all the time).
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sample <= 2'b11;
  else if (clk_en)
    sample <= {sample[0], rx};
end
 
 
// When enabled, tripple sampling is done here.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1;
      sample_pulse <= 0;
    end
  else if (clk_en)
    begin
      if (seg1 & (quant_cnt == (time_segment1 + delay)))
        begin
          sample_pulse <=#Tp 1;
          if (triple_sampling)
            sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
          else
            sampled_bit <=#Tp rx;
        end
    end
  else
    sample_pulse <=#Tp 0;       // Sample pulse is for development purposes only. REMOVE ME.
end
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync_blocked <=#Tp 1'b0;
  else if (clk_en)
    begin
      if (hard_sync || resync)
        sync_blocked <=#Tp 1'b1;
      else if (seg2 & quant_cnt == time_segment2)
        sync_blocked <=#Tp 1'b0;
    end
end
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	9	mohor	`// Revision 1.4 2002/12/26 01:33:05 mohor`
49			`// Tripple sampling supported.`
50			`//`
51	7	mohor	`// Revision 1.3 2002/12/25 23:44:16 mohor`
52			`// Commented lines removed.`
53			`//`
54	6	mohor	`// Revision 1.2 2002/12/25 14:17:00 mohor`
55			`// Synchronization working.`
56			`//`
57	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
58			`// Initial`
59	2	mohor	`//`
60			`//`
61	5	mohor	`//`
62	2	mohor
63			`// synopsys translate_off`
64			`include "timescale.v"
65			`// synopsys translate_on`
66			`include "can_defines.v"
67
68			`module can_btl`
69			`(`
70			`clk,`
71			`rst,`
72			`rx,`
73
74			`/* Mode register */`
75			`reset_mode, // Not used !!!`
76
77			`/* Bus Timing 0 register */`
78			`baud_r_presc,`
79			`sync_jump_width,`
80
81			`/* Bus Timing 1 register */`
82			`time_segment1,`
83			`time_segment2,`
84			`triple_sampling,`
85
86			`/* Output signals from this module */`
87			`take_sample,`
88			`clk_en,`
89
90			`/* States */`
91	9	mohor	`idle`
92	2	mohor
93
94
95			`);`
96
97			`parameter Tp = 1;`
98
99			`input clk;`
100			`input rst;`
101			`input rx;`
102
103			`/* Mode register */`
104			`input reset_mode;`
105
106			`/* Bus Timing 0 register */`
107			`input [5:0] baud_r_presc;`
108			`input [1:0] sync_jump_width;`
109
110			`/* Bus Timing 1 register */`
111			`input [3:0] time_segment1;`
112			`input [2:0] time_segment2;`
113			`input triple_sampling;`
114
115			`/* Output signals from this module */`
116	7	mohor	`output take_sample; // NOT USED, YET`
117	2	mohor	`output clk_en;`
118
119			`input idle;`
120
121
122			`reg [8:0] clk_cnt;`
123			`reg clk_en;`
124	5	mohor	`reg sync_blocked;`
125	2	mohor	`reg sampled_bit;`
126			`reg [7:0] quant_cnt;`
127	6	mohor	`reg [3:0] delay;`
128			`reg sync;`
129			`reg seg1;`
130			`reg seg2;`
131			`reg resync_latched;`
132			`reg sample_pulse;`
133	7	mohor	`reg [1:0] sample;`
134	2	mohor
135	6	mohor	`wire go_sync;`
136			`wire go_seg1;`
137			`wire go_seg2;`
138			`wire [8:0] preset_cnt;`
139			`wire hard_sync;`
140			`wire resync;`
141			`wire sync_window;`
142	2	mohor
143	5	mohor
144
145	6	mohor	`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
146			`assign hard_sync = idle & (~rx) & sampled_bit & (~sync_blocked); // Hard synchronization`
147			`assign resync = (~idle) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization`
148	5	mohor
149
150	6	mohor	`/* Generating general enable signal that defines baud rate. */`
151	2	mohor	`always @ (posedge clk or posedge rst)`
152			`begin`
153			`if (rst)`
154			`begin`
155			`clk_cnt <= 0;`
156			`clk_en <= 1'b0;`
157			`end`
158			`else if (clk_cnt == (preset_cnt-1))`
159			`begin`
160			`clk_cnt <=#Tp 0;`
161			`clk_en <=#Tp 1'b1;`
162			`end`
163			`else`
164			`begin`
165			`clk_cnt <=#Tp clk_cnt + 1;`
166			`clk_en <=#Tp 1'b0;`
167			`end`
168			`end`
169
170
171	5	mohor
172	6	mohor	`/* Changing states */`
173	7	mohor	`//assign go_sync = clk_en & (seg2 & (~resync) & ((quant_cnt == time_segment2)));`
174			`assign go_sync = clk_en & (seg2 & ((quant_cnt == time_segment2)));`
175	6	mohor	`assign go_seg1 = clk_en & (sync \| hard_sync \| (resync & seg2 & sync_window) \| (resync_latched & sync_window));`
176			`assign go_seg2 = clk_en & (seg1 & (quant_cnt == (time_segment1 + delay)));`
177	5	mohor
178
179	6	mohor	`/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when`
180			`SJW is reached */`
181	2	mohor	`always @ (posedge clk or posedge rst)`
182			`begin`
183			`if (rst)`
184	5	mohor	`resync_latched <= 1'b0;`
185	6	mohor	`else if (resync & seg2 & (~sync_window))`
186	5	mohor	`resync_latched <=#Tp 1'b1;`
187			`else if (go_seg1)`
188			`resync_latched <= 1'b0;`
189			`end`
190
191
192
193	6	mohor	`/* Synchronization stage/segment */`
194	5	mohor	`always @ (posedge clk or posedge rst)`
195			`begin`
196			`if (rst)`
197			`sync <= 1;`
198			`else if (go_sync)`
199			`sync <=#Tp 1'b1;`
200			`else if (go_seg1)`
201			`sync <=#Tp 1'b0;`
202			`end`
203
204
205	6	mohor	`/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */`
206	5	mohor	`always @ (posedge clk or posedge rst)`
207			`begin`
208			`if (rst)`
209			`seg1 <= 0;`
210			`else if (go_seg1)`
211			`seg1 <=#Tp 1'b1;`
212			`else if (go_seg2)`
213			`seg1 <=#Tp 1'b0;`
214			`end`
215
216
217	6	mohor	`/* Seg2 stage/segment */`
218	5	mohor	`always @ (posedge clk or posedge rst)`
219			`begin`
220			`if (rst)`
221			`seg2 <= 0;`
222			`else if (go_seg2)`
223			`seg2 <=#Tp 1'b1;`
224			`else if (go_sync \| go_seg1)`
225			`seg2 <=#Tp 1'b0;`
226			`end`
227
228
229	6	mohor	`/* Quant counter */`
230	5	mohor	`always @ (posedge clk or posedge rst)`
231			`begin`
232			`if (rst)`
233			`quant_cnt <= 0;`
234			`else if (go_sync \|\| go_seg1 \|\| go_seg2)`
235			`quant_cnt <=#Tp 0;`
236			`else if (clk_en)`
237			`quant_cnt <=#Tp quant_cnt + 1'b1;`
238			`end`
239
240
241	6	mohor	`/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */`
242	5	mohor	`always @ (posedge clk or posedge rst)`
243			`begin`
244			`if (rst)`
245	6	mohor	`delay <= 0;`
246	5	mohor	`else if (clk_en & resync & seg1)`
247	6	mohor	`delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);`
248	5	mohor	`else if (go_sync \| go_seg1)`
249	6	mohor	`delay <=#Tp 0;`
250	5	mohor	`end`
251
252
253	6	mohor	`// If early edge appears within this window (in seg2 stage), phase error is fully compensated`
254			`assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));`
255	5	mohor
256
257	7	mohor	`// Sampling data (memorizing two samples all the time).`
258	5	mohor	`always @ (posedge clk or posedge rst)`
259			`begin`
260			`if (rst)`
261	7	mohor	`sample <= 2'b11;`
262			`else if (clk_en)`
263			`sample <= {sample[0], rx};`
264			`end`
265
266
267			`// When enabled, tripple sampling is done here.`
268			`always @ (posedge clk or posedge rst)`
269			`begin`
270			`if (rst)`
271	2	mohor	`begin`
272			`sampled_bit <= 1;`
273	5	mohor	`sample_pulse <= 0;`
274	2	mohor	`end`
275	7	mohor	`else if (clk_en)`
276	2	mohor	`begin`
277	7	mohor	`if (seg1 & (quant_cnt == (time_segment1 + delay)))`
278			`begin`
279			`sample_pulse <=#Tp 1;`
280			`if (triple_sampling)`
281			`sampled_bit <=#Tp (sample[0] & sample[1]) \| ( sample[0] & rx) \| (sample[1] & rx);`
282			`else`
283			`sampled_bit <=#Tp rx;`
284			`end`
285	2	mohor	`end`
286	5	mohor	`else`
287	6	mohor	`sample_pulse <=#Tp 0; // Sample pulse is for development purposes only. REMOVE ME.`
288	2	mohor	`end`
289
290
291
292	5	mohor	`/* Blocking synchronization (can occur only once in a bit time) */`
293			`always @ (posedge clk or posedge rst)`
294			`begin`
295			`if (rst)`
296			`sync_blocked <=#Tp 1'b0;`
297			`else if (clk_en)`
298			`begin`
299			`if (hard_sync \|\| resync)`
300			`sync_blocked <=#Tp 1'b1;`
301			`else if (seg2 & quant_cnt == time_segment2)`
302			`sync_blocked <=#Tp 1'b0;`
303			`end`
304			`end`
305	2	mohor
306
307
308
309	5	mohor
310	2	mohor	`endmodule`

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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_btl.v] - Blame information for rev 9