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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_fifo.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.21  2003/08/14 16:04:52  simons
// Artisan ram instances added.
//
// Revision 1.20  2003/07/16 14:00:45  mohor
// Fixed according to the linter.
//
// Revision 1.19  2003/07/03 09:30:44  mohor
// PCI_BIST replaced with CAN_BIST.
//
// Revision 1.18  2003/06/27 22:14:23  simons
// Overrun fifo implemented with FFs, because it is not possible to create such a memory.
//
// Revision 1.17  2003/06/27 20:56:15  simons
// Virtual silicon ram instances added.
//
// Revision 1.16  2003/06/18 23:03:44  mohor
// Typo fixed.
//
// Revision 1.15  2003/06/11 09:37:05  mohor
// overrun and length_info fifos are initialized at the end of reset.
//
// Revision 1.14  2003/03/05 15:02:30  mohor
// Xilinx RAM added.
//
// Revision 1.13  2003/03/01 22:53:33  mohor
// Actel APA ram supported.
//
// Revision 1.12  2003/02/19 14:44:03  mohor
// CAN core finished. Host interface added. Registers finished.
// Synchronization to the wishbone finished.
//
// Revision 1.11  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.10  2003/02/11 00:56:06  mohor
// Wishbone interface added.
//
// Revision 1.9  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.8  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.7  2003/01/17 17:44:31  mohor
// Fifo corrected to be synthesizable.
//
// Revision 1.6  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored
// to fifo, just the frame information (identifier, ...). Data length
// that is stored is the received data length and not the actual data
// length that is stored to fifo.
//
// Revision 1.5  2003/01/14 17:25:09  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.4  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.3  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.2  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.1  2003/01/08 02:10:55  mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_fifo
(
  clk,
  rst,
 
  wr,
 
  data_in,
  addr,
  data_out,
  fifo_selected,
 
  reset_mode,
  release_buffer,
  extended_mode,
  overrun,
  info_empty,
  info_cnt
 
`ifdef CAN_BIST
  ,
  scanb_rst,
  scanb_clk,
  scanb_si,
  scanb_so,
  scanb_en
`endif
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         wr;
input   [7:0] data_in;
input   [5:0] addr;
input         reset_mode;
input         release_buffer;
input         extended_mode;
input         fifo_selected;
 
output  [7:0] data_out;
output        overrun;
output        info_empty;
output  [6:0] info_cnt;
 
`ifdef CAN_BIST
input         scanb_rst;
input         scanb_clk;
input         scanb_si;
output        scanb_so;
input         scanb_en;
wire          scanb_s_0;
`endif
 
`ifdef ACTEL_APA_RAM
`else
`ifdef XILINX_RAM
`else
`ifdef ARTISAN_RAM
  reg           overrun_info[0:63];
`else
`ifdef VIRTUALSILICON_RAM
  reg           overrun_info[0:63];
`else
  reg     [7:0] fifo [0:63];
  reg     [3:0] length_fifo[0:63];
  reg           overrun_info[0:63];
`endif
`endif
`endif
`endif
 
reg     [5:0] rd_pointer;
reg     [5:0] wr_pointer;
reg     [5:0] read_address;
reg     [5:0] wr_info_pointer;
reg     [5:0] rd_info_pointer;
reg           wr_q;
reg     [3:0] len_cnt;
reg     [6:0] fifo_cnt;
reg     [6:0] info_cnt;
reg           latch_overrun;
reg           initialize_memories;
 
wire    [3:0] length_info;
wire          write_length_info;
wire          fifo_empty;
wire          fifo_full;
wire          info_full;
 
assign write_length_info = (~wr) & wr_q;
 
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_q <=#Tp 1'b0;
  else if (reset_mode)
    wr_q <=#Tp 1'b0;
  else
    wr_q <=#Tp wr;
end
 
 
// length counter
always @ (posedge clk or posedge rst)
begin
  if (rst)
    len_cnt <= 4'h0;
  else if (reset_mode | write_length_info)
    len_cnt <=#Tp 4'h0;
  else if (wr & (~fifo_full))
    len_cnt <=#Tp len_cnt + 1'b1;
end
 
 
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_info_pointer <= 6'h0;
  else if (write_length_info & (~info_full) | initialize_memories)
    wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
  else if (reset_mode)
    wr_info_pointer <=#Tp 6'h0;
end
 
 
 
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_info_pointer <= 6'h0;
  else if (reset_mode)
    rd_info_pointer <=#Tp 6'h0;
  else if (release_buffer & (~fifo_empty))
    rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
 
 
// rd_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_pointer <= 5'h0;
  else if (release_buffer & (~fifo_empty))
    rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
  else if (reset_mode)
    rd_pointer <=#Tp 5'h0;
end
 
 
// wr_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_pointer <= 5'h0;
  else if (wr & (~fifo_full))
    wr_pointer <=#Tp wr_pointer + 1'b1;
  else if (reset_mode)
    wr_pointer <=#Tp 5'h0;
end
 
 
// latch_overrun
always @ (posedge clk or posedge rst)
begin
  if (rst)
    latch_overrun <= 1'b0;
  else if (reset_mode | write_length_info)
    latch_overrun <=#Tp 1'b0;
  else if (wr & fifo_full)
    latch_overrun <=#Tp 1'b1;
end
 
 
// Counting data in fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    fifo_cnt <= 7'h0;
  else if (wr & (~release_buffer) & (~fifo_full))
    fifo_cnt <=#Tp fifo_cnt + 1'b1;
  else if ((~wr) & release_buffer & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
  else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
  else if (reset_mode)
    fifo_cnt <=#Tp 7'h0;
end
 
assign fifo_full = fifo_cnt == 7'd64;
assign fifo_empty = fifo_cnt == 7'd0;
 
 
// Counting data in length_fifo and overrun_info fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    info_cnt <=#Tp 7'h0;
  else if (reset_mode)
    info_cnt <=#Tp 7'h0;
  else if (write_length_info ^ release_buffer)
    begin
      if (release_buffer & (~info_empty))
        info_cnt <=#Tp info_cnt - 1'b1;
      else if (write_length_info & (~info_full))
        info_cnt <=#Tp info_cnt + 1'b1;
    end
end
 
assign info_full = info_cnt == 7'd64;
assign info_empty = info_cnt == 7'd0;
 
 
// Selecting which address will be used for reading data from rx fifo
always @ (extended_mode or rd_pointer or addr)
begin
  if (extended_mode)      // extended mode
    read_address = rd_pointer + (addr - 6'd16);
  else                    // normal mode
    read_address = rd_pointer + (addr - 6'd20);
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    initialize_memories <= 1'b1;
  else if (&wr_info_pointer)
    initialize_memories <=#Tp 1'b0;
end
 
 
`ifdef ACTEL_APA_RAM
  actel_ram_64x8_sync fifo
  (
    .DO      (data_out),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (data_in),
    .PO      (),                       // parity not used
    .WRB     (~(wr & (~fifo_full))),
    .RDB     (~fifo_selected),
    .WADDR   (wr_pointer),
    .RADDR   (read_address)
  );
 
 
  actel_ram_64x4_sync info_fifo
  (
    .DO      (length_info),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (len_cnt & {4{~initialize_memories}}),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
 
 
  actel_ram_64x1_sync overrun_fifo
  (
    .DO      (overrun),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
`else
`ifdef XILINX_RAM
 
/*
  ram_64x8_sync fifo
  (
    .addra(wr_pointer),
    .addrb(read_address),
    .clka(clk),
    .clkb(clk),
    .dina(data_in),
    .doutb(data_out),
    .wea(wr & (~fifo_full))
  );
*/
 
  RAMB4_S8_S8 fifo
  (
    .DOA(),
    .DOB(data_out),
    .ADDRA({3'h0, wr_pointer}),
    .CLKA(clk),
    .DIA(data_in),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(wr & (~fifo_full)),
    .ADDRB({3'h0, read_address}),
    .CLKB(clk),
    .DIB(8'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
 
/*
  ram_64x4_sync info_fifo
  (
    .addra(wr_info_pointer),
    .addrb(rd_info_pointer),
    .clka(clk),
    .clkb(clk),
    .dina(len_cnt),
    .doutb(length_info),
    .wea(write_length_info & (~info_full))
  );
*/
  RAMB4_S4_S4 info_fifo
  (
    .DOA(),
    .DOB(length_info),
    .ADDRA({4'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA(len_cnt & {4{~initialize_memories}}),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({4'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(4'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
/*
  ram_64x1_sync overrun_fifo
  (
    .addra(wr_info_pointer),
    .addrb(rd_info_pointer),
    .clka(clk),
    .clkb(clk),
    .dina(latch_overrun | (wr & fifo_full)),
    .doutb(overrun),
    .wea(write_length_info & (~info_full))
  );
*/
 
 
  RAMB4_S1_S1 overrun_fifo
  (
    .DOA(),
    .DOB(overrun),
    .ADDRA({6'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({6'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(1'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
`else
`ifdef VIRTUALSILICON_RAM
 
`ifdef CAN_BIST
    vs_hdtp_64x8_bist fifo
`else
    vs_hdtp_64x8 fifo
`endif
    (
        .RCK        (clk),
        .WCK        (clk),
        .RADR       (read_address),
        .WADR       (wr_pointer),
        .DI         (data_in),
        .DOUT       (data_out),
        .REN        (~fifo_selected),
        .WEN        (~(wr & (~fifo_full)))
    `ifdef CAN_BIST
        ,
        // debug chain signals
        .scanb_rst  (scanb_rst),
        .scanb_clk  (scanb_clk),
        .scanb_si   (scanb_si),
        .scanb_so   (scanb_s_0),
        .scanb_en   (scanb_en)
    `endif
    );
 
`ifdef CAN_BIST
    vs_hdtp_64x4_bist info_fifo
`else
    vs_hdtp_64x4 info_fifo
`endif
    (
        .RCK        (clk),
        .WCK        (clk),
        .RADR       (rd_info_pointer),
        .WADR       (wr_info_pointer),
        .DI         (len_cnt & {4{~initialize_memories}}),
        .DOUT       (length_info),
        .REN        (1'b0),
        .WEN        (~(write_length_info & (~info_full) | initialize_memories))
    `ifdef CAN_BIST
        ,
        // debug chain signals
        .scanb_rst  (scanb_rst),
        .scanb_clk  (scanb_clk),
        .scanb_si   (scanb_s_0),
        .scanb_so   (scanb_so),
        .scanb_en   (scanb_en)
    `endif
    );
 
    // overrun_info
    always @ (posedge clk)
    begin
      if (write_length_info & (~info_full) | initialize_memories)
        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
    end
 
 
    // reading overrun
    assign overrun = overrun_info[rd_info_pointer];
 
`else
`ifdef ARTISAN_RAM
 
`ifdef CAN_BIST
    art_hstp_64x8_bist fifo
    (
        .CLKR       (clk),
        .CLKW       (clk),
        .AR         (read_address),
        .AW         (wr_pointer),
        .D          (data_in),
        .Q          (data_out),
        .REN        (~fifo_selected),
        .WEN        (~(wr & (~fifo_full))),
        .scanb_rst  (scanb_rst),
        .scanb_clk  (scanb_clk),
        .scanb_si   (scanb_si),
        .scanb_so   (scanb_s_0),
        .scanb_en   (scanb_en)
    );
    art_hstp_64x4_bist info_fifo
    (
        .CLKR       (clk),
        .CLKW       (clk),
        .AR         (rd_info_pointer),
        .AW         (wr_info_pointer),
        .D          (len_cnt & {4{~initialize_memories}}),
        .Q          (length_info),
        .REN        (1'b0),
        .WEN        (~(write_length_info & (~info_full) | initialize_memories)),
        .scanb_rst  (scanb_rst),
        .scanb_clk  (scanb_clk),
        .scanb_si   (scanb_s_0),
        .scanb_so   (scanb_so),
        .scanb_en   (scanb_en)
    );
`else
    art_hsdp_64x8 fifo
    (
        .CENA       (1'b0),
        .CENB       (1'b0),
        .CLKA       (clk),
        .CLKB       (clk),
        .AA         (read_address),
        .AB         (wr_pointer),
        .DA         (8'h00),
        .DB         (data_in),
        .QA         (data_out),
        .QB         (),
        .OENA       (~fifo_selected),
        .OENB       (1'b1),
        .WENA       (1'b1),
        .WENB       (~(wr & (~fifo_full)))
    );
    art_hsdp_64x4 info_fifo
    (
        .CENA       (1'b0),
        .CENB       (1'b0),
        .CLKA       (clk),
        .CLKB       (clk),
        .AA         (rd_info_pointer),
        .AB         (wr_info_pointer),
        .DA         (4'h0),
        .DB         (len_cnt & {4{~initialize_memories}}),
        .QA         (length_info),
        .QB         (),
        .OENA       (1'b0),
        .OENB       (1'b1),
        .WENA       (1'b1),
        .WENB       (~(write_length_info & (~info_full) | initialize_memories))
    );
`endif
 
    // overrun_info
    always @ (posedge clk)
    begin
      if (write_length_info & (~info_full) | initialize_memories)
        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
    end
 
 
    // reading overrun
    assign overrun = overrun_info[rd_info_pointer];
 
`else
  // writing data to fifo
  always @ (posedge clk)
  begin
    if (wr & (~fifo_full))
      fifo[wr_pointer] <=#Tp data_in;
  end
 
  // reading from fifo
  assign data_out = fifo[read_address];
 
 
  // writing length_fifo
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
  end
 
 
  // reading length_fifo
  assign length_info = length_fifo[rd_info_pointer];
 
  // overrun_info
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
  end
 
 
  // reading overrun
  assign overrun = overrun_info[rd_info_pointer];
 
 
`endif
`endif
`endif
`endif
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	11	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_fifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002, 2003 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	11	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	118	mohor	`// Revision 1.21 2003/08/14 16:04:52 simons`
54			`// Artisan ram instances added.`
55			`//`
56	115	simons	`// Revision 1.20 2003/07/16 14:00:45 mohor`
57			`// Fixed according to the linter.`
58			`//`
59	109	mohor	`// Revision 1.19 2003/07/03 09:30:44 mohor`
60			`// PCI_BIST replaced with CAN_BIST.`
61			`//`
62	99	mohor	`// Revision 1.18 2003/06/27 22:14:23 simons`
63			`// Overrun fifo implemented with FFs, because it is not possible to create such a memory.`
64			`//`
65	97	simons	`// Revision 1.17 2003/06/27 20:56:15 simons`
66			`// Virtual silicon ram instances added.`
67			`//`
68	95	simons	`// Revision 1.16 2003/06/18 23:03:44 mohor`
69			`// Typo fixed.`
70			`//`
71	85	mohor	`// Revision 1.15 2003/06/11 09:37:05 mohor`
72			`// overrun and length_info fifos are initialized at the end of reset.`
73			`//`
74	73	mohor	`// Revision 1.14 2003/03/05 15:02:30 mohor`
75			`// Xilinx RAM added.`
76			`//`
77	51	mohor	`// Revision 1.13 2003/03/01 22:53:33 mohor`
78			`// Actel APA ram supported.`
79			`//`
80	48	mohor	`// Revision 1.12 2003/02/19 14:44:03 mohor`
81			`// CAN core finished. Host interface added. Registers finished.`
82			`// Synchronization to the wishbone finished.`
83			`//`
84	39	mohor	`// Revision 1.11 2003/02/14 20:17:01 mohor`
85			`// Several registers added. Not finished, yet.`
86			`//`
87	35	mohor	`// Revision 1.10 2003/02/11 00:56:06 mohor`
88			`// Wishbone interface added.`
89			`//`
90	31	mohor	`// Revision 1.9 2003/02/09 02:24:33 mohor`
91			`// Bosch license warning added. Error counters finished. Overload frames`
92			`// still need to be fixed.`
93			`//`
94	28	mohor	`// Revision 1.8 2003/01/31 01:13:38 mohor`
95			`// backup.`
96			`//`
97	24	mohor	`// Revision 1.7 2003/01/17 17:44:31 mohor`
98			`// Fifo corrected to be synthesizable.`
99			`//`
100	23	mohor	`// Revision 1.6 2003/01/15 13:16:47 mohor`
101	31	mohor	`// When a frame with "remote request" is received, no data is stored`
102			`// to fifo, just the frame information (identifier, ...). Data length`
103			`// that is stored is the received data length and not the actual data`
104			`// length that is stored to fifo.`
105	23	mohor	`//`
106	18	mohor	`// Revision 1.5 2003/01/14 17:25:09 mohor`
107			`// Addresses corrected to decimal values (previously hex).`
108			`//`
109	17	mohor	`// Revision 1.4 2003/01/14 12:19:35 mohor`
110			`// rx_fifo is now working.`
111			`//`
112	16	mohor	`// Revision 1.3 2003/01/09 21:54:45 mohor`
113			`// rx fifo added. Not 100 % verified, yet.`
114			`//`
115	14	mohor	`// Revision 1.2 2003/01/09 14:46:58 mohor`
116			`// Temporary files (backup).`
117			`//`
118	13	mohor	`// Revision 1.1 2003/01/08 02:10:55 mohor`
119			`// Acceptance filter added.`
120	11	mohor	`//`
121			`//`
122			`//`
123	13	mohor	`//`
124	11	mohor
125			`// synopsys translate_off`
126			`include "timescale.v"
127			`// synopsys translate_on`
128			`include "can_defines.v"
129
130			`module can_fifo`
131			`(`
132			`clk,`
133			`rst,`
134
135			`wr,`
136
137			`data_in,`
138	14	mohor	`addr,`
139	11	mohor	`data_out,`
140	48	mohor	`fifo_selected,`
141	11	mohor
142			`reset_mode,`
143	14	mohor	`release_buffer,`
144	35	mohor	`extended_mode,`
145			`overrun,`
146	39	mohor	`info_empty,`
147			`info_cnt`
148	13	mohor
149	95	simons	`ifdef CAN_BIST
150			`,`
151			`scanb_rst,`
152			`scanb_clk,`
153			`scanb_si,`
154			`scanb_so,`
155			`scanb_en`
156			`endif
157	11	mohor	`);`
158
159			`parameter Tp = 1;`
160
161			`input clk;`
162			`input rst;`
163			`input wr;`
164			`input [7:0] data_in;`
165	109	mohor	`input [5:0] addr;`
166	11	mohor	`input reset_mode;`
167			`input release_buffer;`
168	14	mohor	`input extended_mode;`
169	48	mohor	`input fifo_selected;`
170	11	mohor
171	13	mohor	`output [7:0] data_out;`
172	35	mohor	`output overrun;`
173			`output info_empty;`
174	39	mohor	`output [6:0] info_cnt;`
175	11	mohor
176	95	simons	`ifdef CAN_BIST
177			`input scanb_rst;`
178			`input scanb_clk;`
179			`input scanb_si;`
180			`output scanb_so;`
181			`input scanb_en;`
182			`wire scanb_s_0;`
183			`endif
184
185	48	mohor	`ifdef ACTEL_APA_RAM
186			`else
187	51	mohor	`ifdef XILINX_RAM
188			`else
189	115	simons	`ifdef ARTISAN_RAM
190			`reg overrun_info[0:63];`
191			`else
192	95	simons	`ifdef VIRTUALSILICON_RAM
193	97	simons	`reg overrun_info[0:63];`
194	95	simons	`else
195	48	mohor	`reg [7:0] fifo [0:63];`
196			`reg [3:0] length_fifo[0:63];`
197			`reg overrun_info[0:63];`
198			`endif
199	51	mohor	`endif
200	95	simons	`endif
201	115	simons	`endif
202	11	mohor
203			`reg [5:0] rd_pointer;`
204			`reg [5:0] wr_pointer;`
205	14	mohor	`reg [5:0] read_address;`
206	16	mohor	`reg [5:0] wr_info_pointer;`
207			`reg [5:0] rd_info_pointer;`
208	13	mohor	`reg wr_q;`
209			`reg [3:0] len_cnt;`
210	16	mohor	`reg [6:0] fifo_cnt;`
211	24	mohor	`reg [6:0] info_cnt;`
212	16	mohor	`reg latch_overrun;`
213	73	mohor	`reg initialize_memories;`
214	11	mohor
215	48	mohor	`wire [3:0] length_info;`
216	13	mohor	`wire write_length_info;`
217	16	mohor	`wire fifo_empty;`
218			`wire fifo_full;`
219	24	mohor	`wire info_full;`
220	11	mohor
221	13	mohor	`assign write_length_info = (~wr) & wr_q;`
222
223			`// Delayed write signal`
224			`always @ (posedge clk or posedge rst)`
225			`begin`
226			`if (rst)`
227	109	mohor	`wr_q <=#Tp 1'b0;`
228	13	mohor	`else if (reset_mode)`
229	109	mohor	`wr_q <=#Tp 1'b0;`
230	13	mohor	`else`
231			`wr_q <=#Tp wr;`
232			`end`
233
234
235			`// length counter`
236			`always @ (posedge clk or posedge rst)`
237			`begin`
238			`if (rst)`
239	109	mohor	`len_cnt <= 4'h0;`
240	13	mohor	`else if (reset_mode \| write_length_info)`
241	109	mohor	`len_cnt <=#Tp 4'h0;`
242	16	mohor	`else if (wr & (~fifo_full))`
243	13	mohor	`len_cnt <=#Tp len_cnt + 1'b1;`
244			`end`
245
246
247			`// wr_info_pointer`
248			`always @ (posedge clk or posedge rst)`
249			`begin`
250			`if (rst)`
251	109	mohor	`wr_info_pointer <= 6'h0;`
252	73	mohor	`else if (write_length_info & (~info_full) \| initialize_memories)`
253			`wr_info_pointer <=#Tp wr_info_pointer + 1'b1;`
254	13	mohor	`else if (reset_mode)`
255	109	mohor	`wr_info_pointer <=#Tp 6'h0;`
256	13	mohor	`end`
257
258
259
260			`// rd_info_pointer`
261	11	mohor	`always @ (posedge clk or posedge rst)`
262			`begin`
263			`if (rst)`
264	109	mohor	`rd_info_pointer <= 6'h0;`
265	11	mohor	`else if (reset_mode)`
266	109	mohor	`rd_info_pointer <=#Tp 6'h0;`
267	16	mohor	`else if (release_buffer & (~fifo_empty))`
268	13	mohor	`rd_info_pointer <=#Tp rd_info_pointer + 1'b1;`
269	11	mohor	`end`
270
271
272			`// rd_pointer`
273			`always @ (posedge clk or posedge rst)`
274			`begin`
275			`if (rst)`
276	109	mohor	`rd_pointer <= 5'h0;`
277	16	mohor	`else if (release_buffer & (~fifo_empty))`
278	109	mohor	`rd_pointer <=#Tp rd_pointer + {2'h0, length_info};`
279	11	mohor	`else if (reset_mode)`
280	109	mohor	`rd_pointer <=#Tp 5'h0;`
281	11	mohor	`end`
282
283
284			`// wr_pointer`
285			`always @ (posedge clk or posedge rst)`
286			`begin`
287			`if (rst)`
288	109	mohor	`wr_pointer <= 5'h0;`
289	16	mohor	`else if (wr & (~fifo_full))`
290	13	mohor	`wr_pointer <=#Tp wr_pointer + 1'b1;`
291	11	mohor	`else if (reset_mode)`
292	109	mohor	`wr_pointer <=#Tp 5'h0;`
293	11	mohor	`end`
294
295
296	16	mohor	`// latch_overrun`
297			`always @ (posedge clk or posedge rst)`
298			`begin`
299			`if (rst)`
300	109	mohor	`latch_overrun <= 1'b0;`
301	16	mohor	`else if (reset_mode \| write_length_info)`
302	109	mohor	`latch_overrun <=#Tp 1'b0;`
303	16	mohor	`else if (wr & fifo_full)`
304			`latch_overrun <=#Tp 1'b1;`
305			`end`
306
307
308			`// Counting data in fifo`
309			`always @ (posedge clk or posedge rst)`
310			`begin`
311			`if (rst)`
312	109	mohor	`fifo_cnt <= 7'h0;`
313	16	mohor	`else if (wr & (~release_buffer) & (~fifo_full))`
314			`fifo_cnt <=#Tp fifo_cnt + 1'b1;`
315			`else if ((~wr) & release_buffer & (~fifo_empty))`
316	109	mohor	`fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};`
317	16	mohor	`else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))`
318	109	mohor	`fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;`
319	16	mohor	`else if (reset_mode)`
320	109	mohor	`fifo_cnt <=#Tp 7'h0;`
321	16	mohor	`end`
322
323	109	mohor	`assign fifo_full = fifo_cnt == 7'd64;`
324			`assign fifo_empty = fifo_cnt == 7'd0;`
325	16	mohor
326
327	48	mohor	`// Counting data in length_fifo and overrun_info fifo`
328	24	mohor	`always @ (posedge clk or posedge rst)`
329			`begin`
330			`if (rst)`
331	109	mohor	`info_cnt <=#Tp 7'h0;`
332			`else if (reset_mode)`
333			`info_cnt <=#Tp 7'h0;`
334	24	mohor	`else if (write_length_info ^ release_buffer)`
335			`begin`
336			`if (release_buffer & (~info_empty))`
337			`info_cnt <=#Tp info_cnt - 1'b1;`
338			`else if (write_length_info & (~info_full))`
339			`info_cnt <=#Tp info_cnt + 1'b1;`
340			`end`
341			`end`
342
343	109	mohor	`assign info_full = info_cnt == 7'd64;`
344			`assign info_empty = info_cnt == 7'd0;`
345	16	mohor
346	24	mohor
347	14	mohor	`// Selecting which address will be used for reading data from rx fifo`
348			`always @ (extended_mode or rd_pointer or addr)`
349			`begin`
350			`if (extended_mode) // extended mode`
351	109	mohor	`read_address = rd_pointer + (addr - 6'd16);`
352	14	mohor	`else // normal mode`
353	109	mohor	`read_address = rd_pointer + (addr - 6'd20);`
354	14	mohor	`end`
355	11	mohor
356
357	73	mohor	`always @ (posedge clk or posedge rst)`
358			`begin`
359			`if (rst)`
360	109	mohor	`initialize_memories <= 1'b1;`
361	73	mohor	`else if (&wr_info_pointer)`
362			`initialize_memories <=#Tp 1'b0;`
363			`end`
364	14	mohor
365	73	mohor
366	48	mohor	`ifdef ACTEL_APA_RAM
367			`actel_ram_64x8_sync fifo`
368			`(`
369			`.DO (data_out),`
370			`.RCLOCK (clk),`
371			`.WCLOCK (clk),`
372			`.DI (data_in),`
373			`.PO (), // parity not used`
374			`.WRB (~(wr & (~fifo_full))),`
375			`.RDB (~fifo_selected),`
376			`.WADDR (wr_pointer),`
377			`.RADDR (read_address)`
378			`);`
379	14	mohor
380
381	48	mohor	`actel_ram_64x4_sync info_fifo`
382			`(`
383			`.DO (length_info),`
384			`.RCLOCK (clk),`
385			`.WCLOCK (clk),`
386	73	mohor	`.DI (len_cnt & {4{~initialize_memories}}),`
387	48	mohor	`.PO (), // parity not used`
388	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
389	48	mohor	`.RDB (1'b0), // always enabled`
390			`.WADDR (wr_info_pointer),`
391			`.RADDR (rd_info_pointer)`
392			`);`
393	14	mohor
394
395	48	mohor	`actel_ram_64x1_sync overrun_fifo`
396			`(`
397			`.DO (overrun),`
398			`.RCLOCK (clk),`
399			`.WCLOCK (clk),`
400	73	mohor	`.DI ((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
401	48	mohor	`.PO (), // parity not used`
402	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
403	48	mohor	`.RDB (1'b0), // always enabled`
404			`.WADDR (wr_info_pointer),`
405			`.RADDR (rd_info_pointer)`
406			`);`
407			`else
408	51	mohor	`ifdef XILINX_RAM
409
410			`/*`
411			`ram_64x8_sync fifo`
412			`(`
413			`.addra(wr_pointer),`
414			`.addrb(read_address),`
415			`.clka(clk),`
416			`.clkb(clk),`
417			`.dina(data_in),`
418			`.doutb(data_out),`
419			`.wea(wr & (~fifo_full))`
420			`);`
421			`*/`
422
423			`RAMB4_S8_S8 fifo`
424			`(`
425			`.DOA(),`
426			`.DOB(data_out),`
427			`.ADDRA({3'h0, wr_pointer}),`
428			`.CLKA(clk),`
429			`.DIA(data_in),`
430			`.ENA(1'b1),`
431			`.RSTA(1'b0),`
432			`.WEA(wr & (~fifo_full)),`
433			`.ADDRB({3'h0, read_address}),`
434			`.CLKB(clk),`
435			`.DIB(8'h0),`
436			`.ENB(1'b1),`
437			`.RSTB(1'b0),`
438			`.WEB(1'b0)`
439			`);`
440
441
442
443			`/*`
444			`ram_64x4_sync info_fifo`
445			`(`
446			`.addra(wr_info_pointer),`
447			`.addrb(rd_info_pointer),`
448			`.clka(clk),`
449			`.clkb(clk),`
450			`.dina(len_cnt),`
451			`.doutb(length_info),`
452			`.wea(write_length_info & (~info_full))`
453			`);`
454			`*/`
455			`RAMB4_S4_S4 info_fifo`
456			`(`
457			`.DOA(),`
458			`.DOB(length_info),`
459			`.ADDRA({4'h0, wr_info_pointer}),`
460			`.CLKA(clk),`
461	73	mohor	`.DIA(len_cnt & {4{~initialize_memories}}),`
462	51	mohor	`.ENA(1'b1),`
463			`.RSTA(1'b0),`
464	73	mohor	`.WEA(write_length_info & (~info_full) \| initialize_memories),`
465	51	mohor	`.ADDRB({4'h0, rd_info_pointer}),`
466			`.CLKB(clk),`
467			`.DIB(4'h0),`
468			`.ENB(1'b1),`
469			`.RSTB(1'b0),`
470			`.WEB(1'b0)`
471			`);`
472
473			`/*`
474			`ram_64x1_sync overrun_fifo`
475			`(`
476			`.addra(wr_info_pointer),`
477			`.addrb(rd_info_pointer),`
478			`.clka(clk),`
479			`.clkb(clk),`
480			`.dina(latch_overrun \| (wr & fifo_full)),`
481			`.doutb(overrun),`
482			`.wea(write_length_info & (~info_full))`
483			`);`
484			`*/`
485
486
487			`RAMB4_S1_S1 overrun_fifo`
488			`(`
489			`.DOA(),`
490			`.DOB(overrun),`
491			`.ADDRA({6'h0, wr_info_pointer}),`
492			`.CLKA(clk),`
493	73	mohor	`.DIA((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
494	51	mohor	`.ENA(1'b1),`
495			`.RSTA(1'b0),`
496	73	mohor	`.WEA(write_length_info & (~info_full) \| initialize_memories),`
497	51	mohor	`.ADDRB({6'h0, rd_info_pointer}),`
498			`.CLKB(clk),`
499			`.DIB(1'h0),`
500			`.ENB(1'b1),`

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