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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_bsp.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2003/01/16 13:36:19  mohor
// Form error supported. When receiving messages, last bit of the end-of-frame
// does not generate form error. Receiver goes to the idle mode one bit sooner.
// (CAN specification ver 2.0, part B, page 57).
//
// Revision 1.13  2003/01/15 21:59:45  mohor
// Data is stored to fifo at the end of ack stage.
//
// Revision 1.12  2003/01/15 21:05:11  mohor
// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
//
// Revision 1.11  2003/01/15 14:40:23  mohor
// RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.
//
// Revision 1.10  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.
//
// Revision 1.9  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.8  2003/01/10 17:51:33  mohor
// Temporary version (backup).
//
// Revision 1.7  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.6  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.5  2003/01/08 13:30:31  mohor
// Temp version.
//
// Revision 1.4  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.3  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.2  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_bsp
(
  clk,
  rst,
 
  sample_point,
  sampled_bit,
  sampled_bit_q,
  tx_point,
  hard_sync,
 
  addr,
  data_out,
 
 
  /* Mode register */
  reset_mode,
  acceptance_filter_mode,
 
  /* Command register */
  release_buffer,
 
  /* Clock Divider register */
  extended_mode,
 
  rx_idle,
  transmitting,
 
  /* This section is for BASIC and EXTENDED mode */
  /* Acceptance code register */
  acceptance_code_0,
 
  /* Acceptance mask register */
  acceptance_mask_0,
  /* End: This section is for BASIC and EXTENDED mode */
 
  /* This section is for EXTENDED mode */
  /* Acceptance code register */
  acceptance_code_1,
  acceptance_code_2,
  acceptance_code_3,
 
  /* Acceptance mask register */
  acceptance_mask_1,
  acceptance_mask_2,
  acceptance_mask_3,
  /* End: This section is for EXTENDED mode */
 
  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
  tx_data_0,
  tx_data_1,
  tx_data_2,
  tx_data_3,
  tx_data_4,
  tx_data_5,
  tx_data_6,
  tx_data_7,
  tx_data_8,
  tx_data_9,
  tx_data_10,
  tx_data_11,
  tx_data_12,
  /* End: Tx data registers */
 
  /* Tx signal */
  tx
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         sample_point;
input         sampled_bit;
input         sampled_bit_q;
input         tx_point;
input         hard_sync;
input   [7:0] addr;
output  [7:0] data_out;
 
 
input         reset_mode;
input         acceptance_filter_mode;
input         extended_mode;
 
/* Command register */
input         release_buffer;
 
output        rx_idle;
output        transmitting;
 
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
input   [7:0] acceptance_code_0;
 
/* Acceptance mask register */
input   [7:0] acceptance_mask_0;
 
/* End: This section is for BASIC and EXTENDED mode */
 
 
/* This section is for EXTENDED mode */
/* Acceptance code register */
input   [7:0] acceptance_code_1;
input   [7:0] acceptance_code_2;
input   [7:0] acceptance_code_3;
 
/* Acceptance mask register */
input   [7:0] acceptance_mask_1;
input   [7:0] acceptance_mask_2;
input   [7:0] acceptance_mask_3;
/* End: This section is for EXTENDED mode */
 
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
input   [7:0] tx_data_0;
input   [7:0] tx_data_1;
input   [7:0] tx_data_2;
input   [7:0] tx_data_3;
input   [7:0] tx_data_4;
input   [7:0] tx_data_5;
input   [7:0] tx_data_6;
input   [7:0] tx_data_7;
input   [7:0] tx_data_8;
input   [7:0] tx_data_9;
input   [7:0] tx_data_10;
input   [7:0] tx_data_11;
input   [7:0] tx_data_12;
/* End: Tx data registers */
 
/* Tx signal */
output        tx;
 
reg           reset_mode_q;
reg     [5:0] bit_cnt;
 
reg     [3:0] data_len;
reg    [28:0] id;
reg     [2:0] bit_stuff_cnt;
reg           stuff_error;
 
wire          bit_de_stuff;
 
 
/* Rx state machine */
wire          go_rx_idle;
wire          go_rx_id1;
wire          go_rx_rtr1;
wire          go_rx_ide;
wire          go_rx_id2;
wire          go_rx_rtr2;
wire          go_rx_r1;
wire          go_rx_r0;
wire          go_rx_dlc;
wire          go_rx_data;
wire          go_rx_crc;
wire          go_rx_crc_lim;
wire          go_rx_ack;
wire          go_rx_ack_lim;
wire          go_rx_eof;
wire          go_error_frame;
wire          go_overload_frame;
wire          go_rx_inter;
 
wire          go_crc_enable;
wire          rst_crc_enable;
 
wire          bit_de_stuff_set;
wire          bit_de_stuff_reset;
 
reg           rx_idle;
reg           rx_id1;
reg           rx_rtr1;
reg           rx_ide;
reg           rx_id2;
reg           rx_rtr2;
reg           rx_r1;
reg           rx_r0;
reg           rx_dlc;
reg           rx_data;
reg           rx_crc;
reg           rx_crc_lim;
reg           rx_ack;
reg           rx_ack_lim;
reg           rx_eof;
reg           rx_inter;
 
reg           rtr1;
reg           ide;
reg           rtr2;
reg    [14:0] crc_in;
 
reg     [7:0] tmp_data;
reg     [7:0] tmp_fifo [0:7];
reg           write_data_to_tmp_fifo;
reg     [2:0] byte_cnt;
reg           bit_stuff_cnt_en;
reg           crc_enable;
 
reg     [2:0] eof_cnt;
wire   [14:0] calculated_crc;
wire          remote_rq;
wire    [3:0] limited_data_len;
//reg           form_error;
wire          form_error;
wire          set_form_error;
reg           transmitting;
 
reg           error_frame;
reg           enable_error_cnt2;
reg     [2:0] error_cnt1;
reg     [2:0] error_cnt2;
reg           tx;
reg           crc_error;
 
wire          error_frame_ended;
wire          bit_error = 0; // FIX ME !!!
wire          acknowledge_error = 0; // FIX ME !!!
wire          need_to_tx = 0; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
                              // of intermission, it starts reading the identifier (and transmitting its own). // FIX ME !!!
wire          overload_needed = 0;  // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
                                    // be send in a row. Counter?   FIX ME
 
assign go_rx_idle     =                   sample_point &  sampled_bit & rx_inter & (bit_cnt == 2);  // Look the following line for TX
//assign go_rx_id1      =                   sample_point &  (~sampled_bit) & (rx_idle | rx_inter & (bit_cnt == 2) & need_to_tx);
assign go_rx_id1      =                   sample_point &  (~sampled_bit) & (rx_idle | rx_inter & (bit_cnt == 2));
assign go_rx_rtr1     = (~bit_de_stuff) & sample_point &  rx_id1  & (bit_cnt == 10);
assign go_rx_ide      = (~bit_de_stuff) & sample_point &  rx_rtr1;
assign go_rx_id2      = (~bit_de_stuff) & sample_point &  rx_ide  &   sampled_bit;
assign go_rx_rtr2     = (~bit_de_stuff) & sample_point &  rx_id2  & (bit_cnt == 17);
assign go_rx_r1       = (~bit_de_stuff) & sample_point &  rx_rtr2;
assign go_rx_r0       = (~bit_de_stuff) & sample_point & (rx_ide  & (~sampled_bit) | rx_r1);
assign go_rx_dlc      = (~bit_de_stuff) & sample_point &  rx_r0;
assign go_rx_data     = (~bit_de_stuff) & sample_point &  rx_dlc  & (bit_cnt == 3) &  (sampled_bit   |   (|data_len[2:0])) & (~remote_rq);
assign go_rx_crc      = (~bit_de_stuff) & sample_point & (rx_dlc  & (bit_cnt == 3) & ((~sampled_bit) & (~(|data_len[2:0])) | remote_rq) |
                                                          rx_data & (bit_cnt == ((limited_data_len<<3) - 1'b1)));
assign go_rx_crc_lim  = (~bit_de_stuff) & sample_point &  rx_crc  & (bit_cnt == 14);
assign go_rx_ack      =                   sample_point &  rx_crc_lim;
assign go_rx_ack_lim  =                   sample_point &  rx_ack;
assign go_rx_eof      =                   sample_point &  rx_ack_lim  | (~reset_mode) & reset_mode_q;
assign go_rx_inter    =                 ((sample_point &  rx_eof  & (eof_cnt == 6)) | error_frame_ended) & (~overload_needed);
 
assign go_error_frame = form_error | stuff_error | bit_error | acknowledge_error | (crc_error & go_rx_eof);
assign error_frame_ended = (error_cnt2 == 7) & tx_point;
 
assign go_overload_frame = ((sample_point &  rx_eof  & (eof_cnt == 6)) | error_frame_ended) & overload_needed |
                             sample_point & (~sampled_bit) & rx_inter & ((bit_cnt == 0) | (bit_cnt == 1))     |
                             sample_point & (~sampled_bit) & (error_cnt2 == 7)
                            ;
 
assign go_crc_enable  = hard_sync;
assign rst_crc_enable = go_rx_crc;
 
assign bit_de_stuff_set   = go_rx_id1;
assign bit_de_stuff_reset = go_rx_crc_lim | reset_mode | go_error_frame;
 
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
assign limited_data_len = (data_len < 8)? data_len : 4'h8;
 
 
// Rx idle state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_idle <= 1'b0;
  else if (reset_mode | go_rx_id1 | error_frame)
    rx_idle <=#Tp 1'b0;
  else if (go_rx_idle)
    rx_idle <=#Tp 1'b1;
end
 
 
// Rx id1 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_id1 <= 1'b0;
  else if (reset_mode | go_rx_rtr1 | error_frame)
    rx_id1 <=#Tp 1'b0;
  else if (go_rx_id1)
    rx_id1 <=#Tp 1'b1;
end
 
 
// Rx rtr1 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_rtr1 <= 1'b0;
  else if (reset_mode | go_rx_ide | error_frame)
    rx_rtr1 <=#Tp 1'b0;
  else if (go_rx_rtr1)
    rx_rtr1 <=#Tp 1'b1;
end
 
 
// Rx ide state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ide <= 1'b0;
  else if (reset_mode | go_rx_r0 | go_rx_id2 | error_frame)
    rx_ide <=#Tp 1'b0;
  else if (go_rx_ide)
    rx_ide <=#Tp 1'b1;
end
 
 
// Rx id2 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_id2 <= 1'b0;
  else if (reset_mode | go_rx_rtr2 | error_frame)
    rx_id2 <=#Tp 1'b0;
  else if (go_rx_id2)
    rx_id2 <=#Tp 1'b1;
end
 
 
// Rx rtr2 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_rtr2 <= 1'b0;
  else if (reset_mode | go_rx_r1 | error_frame)
    rx_rtr2 <=#Tp 1'b0;
  else if (go_rx_rtr2)
    rx_rtr2 <=#Tp 1'b1;
end
 
 
// Rx r0 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_r1 <= 1'b0;
  else if (reset_mode | go_rx_r0 | error_frame)
    rx_r1 <=#Tp 1'b0;
  else if (go_rx_r1)
    rx_r1 <=#Tp 1'b1;
end
 
 
// Rx r0 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_r0 <= 1'b0;
  else if (reset_mode | go_rx_dlc | error_frame)
    rx_r0 <=#Tp 1'b0;
  else if (go_rx_r0)
    rx_r0 <=#Tp 1'b1;
end
 
 
// Rx dlc state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_dlc <= 1'b0;
  else if (reset_mode | go_rx_data | go_rx_crc | error_frame)
    rx_dlc <=#Tp 1'b0;
  else if (go_rx_dlc)
    rx_dlc <=#Tp 1'b1;
end
 
 
// Rx data state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_data <= 1'b0;
  else if (reset_mode | go_rx_crc | error_frame)
    rx_data <=#Tp 1'b0;
  else if (go_rx_data)
    rx_data <=#Tp 1'b1;
end
 
 
// Rx crc state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_crc <= 1'b0;
  else if (reset_mode | go_rx_crc_lim | error_frame)
    rx_crc <=#Tp 1'b0;
  else if (go_rx_crc)
    rx_crc <=#Tp 1'b1;
end
 
 
// Rx crc delimiter state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_crc_lim <= 1'b0;
  else if (reset_mode | go_rx_ack | error_frame)
    rx_crc_lim <=#Tp 1'b0;
  else if (go_rx_crc_lim)
    rx_crc_lim <=#Tp 1'b1;
end
 
 
// Rx ack state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ack <= 1'b0;
  else if (reset_mode | go_rx_ack_lim | error_frame)
    rx_ack <=#Tp 1'b0;
  else if (go_rx_ack)
    rx_ack <=#Tp 1'b1;
end
 
 
// Rx ack delimiter state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ack_lim <= 1'b0;
  else if (reset_mode | go_rx_eof | error_frame)
    rx_ack_lim <=#Tp 1'b0;
  else if (go_rx_ack_lim)
    rx_ack_lim <=#Tp 1'b1;
end
 
 
// Rx eof state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_eof <= 1'b0;
  else if (go_rx_inter | error_frame)
    rx_eof <=#Tp 1'b0;
  else if (go_rx_eof)
    rx_eof <=#Tp 1'b1;
end
 
 
 
// Interframe space
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_inter <= 1'b0;
  else if (go_rx_idle | go_rx_id1 | go_overload_frame | go_error_frame)
    rx_inter <=#Tp 1'b0;
  else if (go_rx_inter)
    rx_inter <=#Tp 1'b1;
end
 
 
// ID register
always @ (posedge clk or posedge rst)
begin
  if (rst)
    id <= 0;
  else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
    id <=#Tp {id[27:0], sampled_bit};
end
 
 
// rtr1 bit
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rtr1 <= 0;
  else if (sample_point & rx_rtr1 & (~bit_de_stuff))
    rtr1 <=#Tp sampled_bit;
end
 
 
// rtr2 bit
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rtr2 <= 0;
  else if (sample_point & rx_rtr2 & (~bit_de_stuff))
    rtr2 <=#Tp sampled_bit;
end
 
 
// ide bit
always @ (posedge clk or posedge rst)
begin
  if (rst)
    ide <= 0;
  else if (sample_point & rx_ide & (~bit_de_stuff))
    ide <=#Tp sampled_bit;
end
 
 
// Data length
always @ (posedge clk or posedge rst)
begin
  if (rst)
    data_len <= 0;
  else if (sample_point & rx_dlc & (~bit_de_stuff))
    data_len <=#Tp {data_len[2:0], sampled_bit};
end
 
 
// Data
always @ (posedge clk or posedge rst)
begin
  if (rst)
    tmp_data <= 0;
  else if (sample_point & rx_data & (~bit_de_stuff))
    tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    write_data_to_tmp_fifo <= 0;
  else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
    write_data_to_tmp_fifo <=#Tp 1'b1;
  else
    write_data_to_tmp_fifo <=#Tp 0;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    byte_cnt <= 0;
  else if (write_data_to_tmp_fifo)
    byte_cnt <=#Tp byte_cnt + 1;
  else if (sample_point & go_rx_crc_lim)
    byte_cnt <=#Tp 0;
end
 
 
always @ (posedge clk)
begin
  if (write_data_to_tmp_fifo)
    tmp_fifo[byte_cnt] <=#Tp tmp_data;
end
 
 
 
// CRC
always @ (posedge clk or posedge rst)
begin
  if (rst)
    crc_in <= 0;
  else if (sample_point & rx_crc & (~bit_de_stuff))
    crc_in <=#Tp {crc_in[13:0], sampled_bit};
end
 
 
// bit_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_cnt <= 0;
  else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc |
           go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)
    bit_cnt <=#Tp 0;
  else if (sample_point & (~bit_de_stuff))
    bit_cnt <=#Tp bit_cnt + 1'b1;
end
 
 
// eof_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    eof_cnt <= 0;
  else if (sample_point)
    begin
      if (rx_eof & sampled_bit)
        eof_cnt <=#Tp eof_cnt + 1'b1;
      else
        eof_cnt <=#Tp 0;
    end
end
 
 
// Enabling bit de-stuffing
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_stuff_cnt_en <= 1'b0;
  else if (bit_de_stuff_set)
    bit_stuff_cnt_en <=#Tp 1'b1;
  else if (bit_de_stuff_reset)
    bit_stuff_cnt_en <=#Tp 1'b0;
end
 
 
// bit_stuff_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_stuff_cnt <= 1;
  else if (bit_de_stuff_reset)
    bit_stuff_cnt <=#Tp 1;
  else if (sample_point & bit_stuff_cnt_en)
    begin
      if (bit_stuff_cnt == 5)
        bit_stuff_cnt <=#Tp 1;
      else if (sampled_bit == sampled_bit_q)
        bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1;
      else
        bit_stuff_cnt <=#Tp 1;
    end
end
 
 
assign bit_de_stuff = bit_stuff_cnt == 5;
 
 
 
// stuff_error
always @ (posedge clk or posedge rst)
begin
  if (rst)
    stuff_error <= 0;
  else if (reset_mode | go_rx_idle | error_frame)     // Stuff error might reset itself
    stuff_error <=#Tp 0;
  else if (sample_point & bit_stuff_cnt_en & bit_de_stuff & (sampled_bit == sampled_bit_q))
    stuff_error <=#Tp 1'b1;
end
 
 
// Generating delayed reset_mode signal
always @ (posedge clk)
begin
  reset_mode_q <=#Tp reset_mode;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    crc_enable <= 1'b0;
  else if (go_crc_enable)
    crc_enable <=#Tp 1'b1;
  else if (reset_mode | rst_crc_enable)
    crc_enable <=#Tp 1'b0;
end
 
 
// CRC error generation
always @ (posedge clk or posedge rst)
begin
  if (rst)
    crc_error <= 0;
  else if (go_rx_ack)
    crc_error <=#Tp crc_in != calculated_crc;
  else if (reset_mode | go_rx_idle | error_frame)   // CRC error might reset itself
    crc_error <=#Tp 0;
end
 
 
// Conditions for form error
//assign set_form_error = sample_point & ( (~bit_de_stuff) & rx_ide     &   sampled_bit & (~rtr1) |
assign     form_error = sample_point & ( (~bit_de_stuff) & rx_ide     &   sampled_bit & (~rtr1) |
                                                           rx_crc_lim & (~sampled_bit)          |
                                                           rx_ack_lim & (~sampled_bit)          |
                                                           rx_eof     & (~sampled_bit)
                                       );
 
/*
// Form error
always @ (posedge clk or posedge rst)
begin
  if (rst)
    form_error <= 1'b0;
  else if (reset_mode | go_rx_idle | error_frame)
    form_error <=#Tp 1'b0;
  else if (set_form_error)
    form_error <=#Tp 1'b1;
end
*/
 
// Instantiation of the RX CRC module
can_crc i_can_crc_rx
(
  .clk(clk),
//  .data(sampled_bit & (~rx_crc)),     // Zeros are shifted in for calculation when we are in crc stage
  .data(sampled_bit ),     // Zeros are shifted in for calculation when we are in crc stage
  .enable(crc_enable & sample_point & (~bit_de_stuff)),
  .initialize(rx_eof),
  .crc(calculated_crc)
);
 
 
 
wire          id_ok;        // If received ID matches ID set in registers
wire          no_byte0;     // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
wire          no_byte1;     // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
 
assign no_byte0 = rtr1 | (data_len<1);
assign no_byte1 = rtr1 | (data_len<2);
 
can_acf i_can_acf
(
  .clk(clk),
  .rst(rst),
 
  .id(id),
 
  /* Mode register */
  .reset_mode(reset_mode),
  .acceptance_filter_mode(acceptance_filter_mode),
 
  // Clock Divider register
  .extended_mode(extended_mode),
 
  /* This section is for BASIC and EXTENDED mode */
  /* Acceptance code register */
  .acceptance_code_0(acceptance_code_0),
 
  /* Acceptance mask register */
  .acceptance_mask_0(acceptance_mask_0),
  /* End: This section is for BASIC and EXTENDED mode */
 
  /* This section is for EXTENDED mode */
  /* Acceptance code register */
  .acceptance_code_1(acceptance_code_1),
  .acceptance_code_2(acceptance_code_2),
  .acceptance_code_3(acceptance_code_3),
 
  /* Acceptance mask register */
  .acceptance_mask_1(acceptance_mask_1),
  .acceptance_mask_2(acceptance_mask_2),
  .acceptance_mask_3(acceptance_mask_3),
  /* End: This section is for EXTENDED mode */
 
  .go_rx_crc_lim(go_rx_crc_lim),
  .go_rx_idle(go_rx_idle),
 
  .data0(tmp_fifo[0]),
  .data1(tmp_fifo[1]),
  .rtr1(rtr1),
  .rtr2(rtr2),
  .ide(ide),
  .no_byte0(no_byte0),
  .no_byte1(no_byte1),
 
  .id_ok(id_ok)
 
);
 
 
 
reg [3:0]   data_cnt;       // Counting the data bytes that are written to FIFO
reg [2:0]   header_cnt;     // Counting header length
reg         wr_fifo;        // Write data and header to 64-byte fifo
reg [7:0]   data_for_fifo;  // Multiplexed data that is stored to 64-byte fifo
 
 
wire [2:0]  header_len;
wire        storing_header;
wire [3:0]  limited_data_len_minus1;
wire        reset_wr_fifo;
wire        no_error;
 
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
assign storing_header = header_cnt < header_len;
assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 8)? (data_len -1'b1) : 4'h7);   // - 1 because counter counts from 0
assign reset_wr_fifo = data_cnt == (limited_data_len_minus1 + header_len);
assign no_error = (~crc_error) & (~form_error) & (~stuff_error);
 
 
 
// Write enable signal for 64-byte rx fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_fifo <= 1'b0;
  else if (reset_wr_fifo)
    wr_fifo <=#Tp 1'b0;
  else if (go_rx_inter & id_ok & (~error_frame_ended))
    wr_fifo <=#Tp 1'b1;
end
 
 
// Header counter. Header length depends on the mode of operation and frame format.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    header_cnt <= 0;
  else if (reset_wr_fifo)
    header_cnt <=#Tp 0;
  else if (wr_fifo & storing_header)
    header_cnt <=#Tp header_cnt + 1;
end
 
 
// Data counter. Length of the data is limited to 8 bytes.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    data_cnt <= 0;
  else if (reset_wr_fifo)
    data_cnt <=#Tp 0;
  else if (wr_fifo)
    data_cnt <=#Tp data_cnt + 1;
end
 
 
// Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
always @ (extended_mode or ide or data_cnt or header_cnt or  header_len or
          storing_header or id or rtr1 or rtr2 or data_len or
          tmp_fifo[0] or tmp_fifo[2] or tmp_fifo[4] or tmp_fifo[6] or
          tmp_fifo[1] or tmp_fifo[3] or tmp_fifo[5] or tmp_fifo[7])
begin
  if (storing_header)
    begin
      if (extended_mode)      // extended mode
        begin
          if (ide)              // extended format
            begin
              case (header_cnt) // synthesis parallel_case 
                3'h0  : data_for_fifo <= {1'b1, rtr2, 2'h0, data_len};
                3'h1  : data_for_fifo <= id[28:21];
                3'h2  : data_for_fifo <= id[20:13];
                3'h3  : data_for_fifo <= id[12:5];
                3'h4  : data_for_fifo <= {id[4:0], 3'h0};
                default: data_for_fifo <= 0;
              endcase
            end
          else                  // standard format
            begin
              case (header_cnt) // synthesis parallel_case 
                3'h0  : data_for_fifo <= {1'b0, rtr1, 2'h0, data_len};
                3'h1  : data_for_fifo <= id[10:3];
                3'h2  : data_for_fifo <= {id[2:0], 5'h0};
                default: data_for_fifo <= 0;
              endcase
            end
        end
      else                    // normal mode
        begin
          case (header_cnt) // synthesis parallel_case 
            3'h0  : data_for_fifo <= id[10:3];
            3'h1  : data_for_fifo <= {id[2:0], rtr1, data_len};
            default: data_for_fifo <= 0;
          endcase
        end
    end
  else
    data_for_fifo <= tmp_fifo[data_cnt-header_len];
end
 
 
 
 
// Instantiation of the RX fifo module
can_fifo i_can_fifo
(
  .clk(clk),
  .rst(rst),
 
  .wr(wr_fifo),
 
  .data_in(data_for_fifo),
  .addr(addr),
  .data_out(data_out),
 
  .reset_mode(reset_mode),
  .release_buffer(release_buffer),
  .extended_mode(extended_mode)
 
 
);
 
 
 
// transmitting signals that core is a transmitter. No synchronization is done meanwhile.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    transmitting <= 1'b0;
  else if (go_rx_idle | reset_mode)
    transmitting <=#Tp 1'b0;
  else if (~no_error)
    transmitting <=#Tp 1'b1;
end
 
 
 
// Transmitting error frame. The same counters are used for sending overload frame, too.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    error_frame <= 1'b0;
  else if (reset_mode | error_frame_ended)
    error_frame <=#Tp 1'b0;
  else if (go_error_frame | go_overload_frame)
    error_frame <=#Tp 1'b1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    error_cnt1 <= 1'b0;
  else if (reset_mode | error_frame_ended)
    error_cnt1 <=#Tp 1'b0;
  else if (error_frame & tx_point & (error_cnt1 < 6))
    error_cnt1 <=#Tp error_cnt1 + 1'b1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    enable_error_cnt2 <= 1'b0;
  else if (reset_mode | error_frame_ended)
    enable_error_cnt2 <=#Tp 1'b0;
  else if (sample_point & sampled_bit & (error_cnt1 == 6))
    enable_error_cnt2 <=#Tp 1'b1;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    error_cnt2 <= 1'b0;
  else if (reset_mode | error_frame_ended)
    error_cnt2 <=#Tp 1'b0;
  else if (enable_error_cnt2 & tx_point)
    error_cnt2 <=#Tp error_cnt2 + 1'b1;
end
 
 
wire node_error_passive = 1;
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    tx <= 1'b1;
  else if (reset_mode | error_frame_ended)
    tx <=#Tp 1'b1;
  else if (tx_point & error_frame)
    begin
      if (error_cnt1 < 6)
        begin
          if (node_error_passive)
            tx <=#Tp 1'b1;
          else
            tx <=#Tp 1'b0;
        end
      else if (error_cnt2 < 7)
        tx <=#Tp 1'b1;
    end
end
 
 
 
 
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_bsp.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	24	mohor	`// Revision 1.14 2003/01/16 13:36:19 mohor`
49			`// Form error supported. When receiving messages, last bit of the end-of-frame`
50			`// does not generate form error. Receiver goes to the idle mode one bit sooner.`
51			`// (CAN specification ver 2.0, part B, page 57).`
52			`//`
53	22	mohor	`// Revision 1.13 2003/01/15 21:59:45 mohor`
54			`// Data is stored to fifo at the end of ack stage.`
55			`//`
56	21	mohor	`// Revision 1.12 2003/01/15 21:05:11 mohor`
57			`// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).`
58			`//`
59	20	mohor	`// Revision 1.11 2003/01/15 14:40:23 mohor`
60			`// RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.`
61			`//`
62	19	mohor	`// Revision 1.10 2003/01/15 13:16:47 mohor`
63			`// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.`
64			`//`
65	18	mohor	`// Revision 1.9 2003/01/14 12:19:35 mohor`
66			`// rx_fifo is now working.`
67			`//`
68	16	mohor	`// Revision 1.8 2003/01/10 17:51:33 mohor`
69			`// Temporary version (backup).`
70			`//`
71	15	mohor	`// Revision 1.7 2003/01/09 21:54:45 mohor`
72			`// rx fifo added. Not 100 % verified, yet.`
73			`//`
74	14	mohor	`// Revision 1.6 2003/01/09 14:46:58 mohor`
75			`// Temporary files (backup).`
76			`//`
77	13	mohor	`// Revision 1.5 2003/01/08 13:30:31 mohor`
78			`// Temp version.`
79			`//`
80	12	mohor	`// Revision 1.4 2003/01/08 02:10:53 mohor`
81			`// Acceptance filter added.`
82			`//`
83	11	mohor	`// Revision 1.3 2002/12/28 04:13:23 mohor`
84			`// Backup version.`
85			`//`
86	10	mohor	`// Revision 1.2 2002/12/27 00:12:52 mohor`
87			`// Header changed, testbench improved to send a frame (crc still missing).`
88			`//`
89	9	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
90			`// Initial`
91	2	mohor	`//`
92			`//`
93	9	mohor	`//`
94	2	mohor
95			`// synopsys translate_off`
96			`include "timescale.v"
97			`// synopsys translate_on`
98			`include "can_defines.v"
99
100			`module can_bsp`
101			`(`
102			`clk,`
103	10	mohor	`rst,`
104
105			`sample_point,`
106			`sampled_bit,`
107			`sampled_bit_q,`
108	24	mohor	`tx_point,`
109	11	mohor	`hard_sync,`
110
111	14	mohor	`addr,`
112			`data_out,`
113
114
115	11	mohor	`/* Mode register */`
116	10	mohor	`reset_mode,`
117	11	mohor	`acceptance_filter_mode,`
118
119	15	mohor	`/* Command register */`
120			`release_buffer,`
121
122			`/* Clock Divider register */`
123	11	mohor	`extended_mode,`
124
125			`rx_idle,`
126	24	mohor	`transmitting,`
127	11	mohor
128			`/* This section is for BASIC and EXTENDED mode */`
129			`/* Acceptance code register */`
130			`acceptance_code_0,`
131
132			`/* Acceptance mask register */`
133			`acceptance_mask_0,`
134			`/* End: This section is for BASIC and EXTENDED mode */`
135	10	mohor
136	11	mohor	`/* This section is for EXTENDED mode */`
137			`/* Acceptance code register */`
138			`acceptance_code_1,`
139			`acceptance_code_2,`
140			`acceptance_code_3,`
141	10	mohor
142	11	mohor	`/* Acceptance mask register */`
143			`acceptance_mask_1,`
144			`acceptance_mask_2,`
145	18	mohor	`acceptance_mask_3,`
146	11	mohor	`/* End: This section is for EXTENDED mode */`
147	10	mohor
148	18	mohor	`/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */`
149			`tx_data_0,`
150			`tx_data_1,`
151			`tx_data_2,`
152			`tx_data_3,`
153			`tx_data_4,`
154			`tx_data_5,`
155			`tx_data_6,`
156			`tx_data_7,`
157			`tx_data_8,`
158			`tx_data_9,`
159			`tx_data_10,`
160			`tx_data_11,`
161	24	mohor	`tx_data_12,`
162	18	mohor	`/* End: Tx data registers */`
163	24	mohor
164			`/* Tx signal */`
165			`tx`
166	18	mohor
167	2	mohor	`);`
168
169			`parameter Tp = 1;`
170
171	10	mohor	`input clk;`
172			`input rst;`
173			`input sample_point;`
174			`input sampled_bit;`
175			`input sampled_bit_q;`
176	24	mohor	`input tx_point;`
177	11	mohor	`input hard_sync;`
178	14	mohor	`input [7:0] addr;`
179			`output [7:0] data_out;`
180	11	mohor
181	14	mohor
182	10	mohor	`input reset_mode;`
183	11	mohor	`input acceptance_filter_mode;`
184			`input extended_mode;`
185	2	mohor
186	15	mohor	`/* Command register */`
187			`input release_buffer;`
188	11	mohor
189	10	mohor	`output rx_idle;`
190	24	mohor	`output transmitting;`
191	2	mohor
192	11	mohor	`/* This section is for BASIC and EXTENDED mode */`
193			`/* Acceptance code register */`
194			`input [7:0] acceptance_code_0;`
195
196			`/* Acceptance mask register */`
197			`input [7:0] acceptance_mask_0;`
198
199			`/* End: This section is for BASIC and EXTENDED mode */`
200
201
202			`/* This section is for EXTENDED mode */`
203			`/* Acceptance code register */`
204			`input [7:0] acceptance_code_1;`
205			`input [7:0] acceptance_code_2;`
206			`input [7:0] acceptance_code_3;`
207
208			`/* Acceptance mask register */`
209			`input [7:0] acceptance_mask_1;`
210			`input [7:0] acceptance_mask_2;`
211			`input [7:0] acceptance_mask_3;`
212			`/* End: This section is for EXTENDED mode */`
213
214	24	mohor	`/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */`
215	18	mohor	`input [7:0] tx_data_0;`
216			`input [7:0] tx_data_1;`
217			`input [7:0] tx_data_2;`
218			`input [7:0] tx_data_3;`
219			`input [7:0] tx_data_4;`
220			`input [7:0] tx_data_5;`
221			`input [7:0] tx_data_6;`
222			`input [7:0] tx_data_7;`
223			`input [7:0] tx_data_8;`
224			`input [7:0] tx_data_9;`
225			`input [7:0] tx_data_10;`
226			`input [7:0] tx_data_11;`
227			`input [7:0] tx_data_12;`
228	24	mohor	`/* End: Tx data registers */`
229	11	mohor
230	24	mohor	`/* Tx signal */`
231			`output tx;`
232	11	mohor
233	10	mohor	`reg reset_mode_q;`
234			`reg [5:0] bit_cnt;`
235	2	mohor
236	10	mohor	`reg [3:0] data_len;`
237			`reg [28:0] id;`
238			`reg [2:0] bit_stuff_cnt;`
239			`reg stuff_error;`
240
241			`wire bit_de_stuff;`
242
243
244			`/* Rx state machine */`
245			`wire go_rx_idle;`
246			`wire go_rx_id1;`
247			`wire go_rx_rtr1;`
248			`wire go_rx_ide;`
249			`wire go_rx_id2;`
250			`wire go_rx_rtr2;`
251			`wire go_rx_r1;`
252			`wire go_rx_r0;`
253			`wire go_rx_dlc;`
254			`wire go_rx_data;`
255			`wire go_rx_crc;`
256	11	mohor	`wire go_rx_crc_lim;`
257	10	mohor	`wire go_rx_ack;`
258	11	mohor	`wire go_rx_ack_lim;`
259	10	mohor	`wire go_rx_eof;`
260	24	mohor	`wire go_error_frame;`
261			`wire go_overload_frame;`
262			`wire go_rx_inter;`
263	10	mohor
264	11	mohor	`wire go_crc_enable;`
265			`wire rst_crc_enable;`
266
267			`wire bit_de_stuff_set;`
268			`wire bit_de_stuff_reset;`
269
270	10	mohor	`reg rx_idle;`
271			`reg rx_id1;`
272			`reg rx_rtr1;`
273			`reg rx_ide;`
274			`reg rx_id2;`
275			`reg rx_rtr2;`
276			`reg rx_r1;`
277			`reg rx_r0;`
278			`reg rx_dlc;`
279			`reg rx_data;`
280			`reg rx_crc;`
281	11	mohor	`reg rx_crc_lim;`
282	10	mohor	`reg rx_ack;`
283	11	mohor	`reg rx_ack_lim;`
284	10	mohor	`reg rx_eof;`
285	24	mohor	`reg rx_inter;`
286	10	mohor
287	19	mohor	`reg rtr1;`
288			`reg ide;`
289			`reg rtr2;`
290			`reg [14:0] crc_in;`
291
292	24	mohor	`reg [7:0] tmp_data;`
293			`reg [7:0] tmp_fifo [0:7];`
294			`reg write_data_to_tmp_fifo;`
295			`reg [2:0] byte_cnt;`
296			`reg bit_stuff_cnt_en;`
297	11	mohor	`reg crc_enable;`
298
299	10	mohor	`reg [2:0] eof_cnt;`
300	11	mohor	`wire [14:0] calculated_crc;`
301	19	mohor	`wire remote_rq;`
302	22	mohor	`wire [3:0] limited_data_len;`
303	24	mohor	`//reg form_error;`
304			`wire form_error;`
305	22	mohor	`wire set_form_error;`
306	24	mohor	`reg transmitting;`
307	10	mohor
308	24	mohor	`reg error_frame;`
309			`reg enable_error_cnt2;`
310			`reg [2:0] error_cnt1;`
311			`reg [2:0] error_cnt2;`
312			`reg tx;`
313			`reg crc_error;`
314
315			`wire error_frame_ended;`
316			`wire bit_error = 0; // FIX ME !!!`
317			`wire acknowledge_error = 0; // FIX ME !!!`
318			`wire need_to_tx = 0; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit`
319			`// of intermission, it starts reading the identifier (and transmitting its own). // FIX ME !!!`
320			`wire overload_needed = 0; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to`
321			`// be send in a row. Counter? FIX ME`
322
323			`assign go_rx_idle = sample_point & sampled_bit & rx_inter & (bit_cnt == 2); // Look the following line for TX`
324			`//assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle \| rx_inter & (bit_cnt == 2) & need_to_tx);`
325			`assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle \| rx_inter & (bit_cnt == 2));`
326	11	mohor	`assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt == 10);`
327			`assign go_rx_ide = (~bit_de_stuff) & sample_point & rx_rtr1;`
328			`assign go_rx_id2 = (~bit_de_stuff) & sample_point & rx_ide & sampled_bit;`
329			`assign go_rx_rtr2 = (~bit_de_stuff) & sample_point & rx_id2 & (bit_cnt == 17);`
330			`assign go_rx_r1 = (~bit_de_stuff) & sample_point & rx_rtr2;`
331			`assign go_rx_r0 = (~bit_de_stuff) & sample_point & (rx_ide & (~sampled_bit) \| rx_r1);`
332			`assign go_rx_dlc = (~bit_de_stuff) & sample_point & rx_r0;`
333	19	mohor	`assign go_rx_data = (~bit_de_stuff) & sample_point & rx_dlc & (bit_cnt == 3) & (sampled_bit \| (\|data_len[2:0])) & (~remote_rq);`
334			`assign go_rx_crc = (~bit_de_stuff) & sample_point & (rx_dlc & (bit_cnt == 3) & ((~sampled_bit) & (~(\|data_len[2:0])) \| remote_rq) \|`
335			`rx_data & (bit_cnt == ((limited_data_len<<3) - 1'b1)));`
336	20	mohor	`assign go_rx_crc_lim = (~bit_de_stuff) & sample_point & rx_crc & (bit_cnt == 14);`
337	11	mohor	`assign go_rx_ack = sample_point & rx_crc_lim;`
338			`assign go_rx_ack_lim = sample_point & rx_ack;`
339			`assign go_rx_eof = sample_point & rx_ack_lim \| (~reset_mode) & reset_mode_q;`
340	24	mohor	`assign go_rx_inter = ((sample_point & rx_eof & (eof_cnt == 6)) \| error_frame_ended) & (~overload_needed);`
341	10	mohor
342	24	mohor	`assign go_error_frame = form_error \| stuff_error \| bit_error \| acknowledge_error \| (crc_error & go_rx_eof);`
343			`assign error_frame_ended = (error_cnt2 == 7) & tx_point;`
344
345			`assign go_overload_frame = ((sample_point & rx_eof & (eof_cnt == 6)) \| error_frame_ended) & overload_needed \|`
346			`sample_point & (~sampled_bit) & rx_inter & ((bit_cnt == 0) \| (bit_cnt == 1)) \|`
347			`sample_point & (~sampled_bit) & (error_cnt2 == 7)`
348			`;`
349
350	11	mohor	`assign go_crc_enable = hard_sync;`
351			`assign rst_crc_enable = go_rx_crc;`
352	10	mohor
353	11	mohor	`assign bit_de_stuff_set = go_rx_id1;`
354	24	mohor	`assign bit_de_stuff_reset = go_rx_crc_lim \| reset_mode \| go_error_frame;`
355	11	mohor
356	19	mohor	`assign remote_rq = ((~ide) & rtr1) \| (ide & rtr2);`
357			`assign limited_data_len = (data_len < 8)? data_len : 4'h8;`
358	11	mohor
359	19	mohor
360	10	mohor	`// Rx idle state`
361			`always @ (posedge clk or posedge rst)`
362			`begin`
363			`if (rst)`
364	24	mohor	`rx_idle <= 1'b0;`
365			`else if (reset_mode \| go_rx_id1 \| error_frame)`
366	10	mohor	`rx_idle <=#Tp 1'b0;`
367			`else if (go_rx_idle)`
368			`rx_idle <=#Tp 1'b1;`
369			`end`
370
371
372			`// Rx id1 state`
373			`always @ (posedge clk or posedge rst)`
374			`begin`
375			`if (rst)`
376			`rx_id1 <= 1'b0;`
377	24	mohor	`else if (reset_mode \| go_rx_rtr1 \| error_frame)`
378	10	mohor	`rx_id1 <=#Tp 1'b0;`
379			`else if (go_rx_id1)`
380			`rx_id1 <=#Tp 1'b1;`
381			`end`
382
383
384			`// Rx rtr1 state`
385			`always @ (posedge clk or posedge rst)`
386			`begin`
387			`if (rst)`
388			`rx_rtr1 <= 1'b0;`
389	24	mohor	`else if (reset_mode \| go_rx_ide \| error_frame)`
390	10	mohor	`rx_rtr1 <=#Tp 1'b0;`
391			`else if (go_rx_rtr1)`
392			`rx_rtr1 <=#Tp 1'b1;`
393			`end`
394
395
396			`// Rx ide state`
397			`always @ (posedge clk or posedge rst)`
398			`begin`
399			`if (rst)`
400			`rx_ide <= 1'b0;`
401	24	mohor	`else if (reset_mode \| go_rx_r0 \| go_rx_id2 \| error_frame)`
402	10	mohor	`rx_ide <=#Tp 1'b0;`
403			`else if (go_rx_ide)`
404			`rx_ide <=#Tp 1'b1;`
405			`end`
406
407
408			`// Rx id2 state`
409			`always @ (posedge clk or posedge rst)`
410			`begin`
411			`if (rst)`
412			`rx_id2 <= 1'b0;`
413	24	mohor	`else if (reset_mode \| go_rx_rtr2 \| error_frame)`
414	10	mohor	`rx_id2 <=#Tp 1'b0;`
415			`else if (go_rx_id2)`
416			`rx_id2 <=#Tp 1'b1;`
417			`end`
418
419
420			`// Rx rtr2 state`
421			`always @ (posedge clk or posedge rst)`
422			`begin`
423			`if (rst)`
424			`rx_rtr2 <= 1'b0;`
425	24	mohor	`else if (reset_mode \| go_rx_r1 \| error_frame)`
426	10	mohor	`rx_rtr2 <=#Tp 1'b0;`
427			`else if (go_rx_rtr2)`
428			`rx_rtr2 <=#Tp 1'b1;`
429			`end`
430
431
432			`// Rx r0 state`
433			`always @ (posedge clk or posedge rst)`
434			`begin`
435			`if (rst)`
436			`rx_r1 <= 1'b0;`
437	24	mohor	`else if (reset_mode \| go_rx_r0 \| error_frame)`
438	10	mohor	`rx_r1 <=#Tp 1'b0;`
439			`else if (go_rx_r1)`
440			`rx_r1 <=#Tp 1'b1;`
441			`end`
442
443
444			`// Rx r0 state`
445			`always @ (posedge clk or posedge rst)`
446			`begin`
447			`if (rst)`
448			`rx_r0 <= 1'b0;`
449	24	mohor	`else if (reset_mode \| go_rx_dlc \| error_frame)`
450	10	mohor	`rx_r0 <=#Tp 1'b0;`
451			`else if (go_rx_r0)`
452			`rx_r0 <=#Tp 1'b1;`
453			`end`
454
455
456			`// Rx dlc state`
457			`always @ (posedge clk or posedge rst)`
458			`begin`
459			`if (rst)`
460			`rx_dlc <= 1'b0;`
461	24	mohor	`else if (reset_mode \| go_rx_data \| go_rx_crc \| error_frame)`
462	10	mohor	`rx_dlc <=#Tp 1'b0;`
463			`else if (go_rx_dlc)`
464			`rx_dlc <=#Tp 1'b1;`
465			`end`
466
467
468			`// Rx data state`
469			`always @ (posedge clk or posedge rst)`
470			`begin`
471			`if (rst)`
472			`rx_data <= 1'b0;`
473	24	mohor	`else if (reset_mode \| go_rx_crc \| error_frame)`
474	10	mohor	`rx_data <=#Tp 1'b0;`
475			`else if (go_rx_data)`
476			`rx_data <=#Tp 1'b1;`
477			`end`
478
479
480			`// Rx crc state`
481			`always @ (posedge clk or posedge rst)`
482			`begin`
483			`if (rst)`
484			`rx_crc <= 1'b0;`
485	24	mohor	`else if (reset_mode \| go_rx_crc_lim \| error_frame)`
486	10	mohor	`rx_crc <=#Tp 1'b0;`
487			`else if (go_rx_crc)`
488			`rx_crc <=#Tp 1'b1;`
489			`end`
490
491
492	11	mohor	`// Rx crc delimiter state`
493			`always @ (posedge clk or posedge rst)`
494			`begin`
495			`if (rst)`
496			`rx_crc_lim <= 1'b0;`
497	24	mohor	`else if (reset_mode \| go_rx_ack \| error_frame)`
498	11	mohor	`rx_crc_lim <=#Tp 1'b0;`
499			`else if (go_rx_crc_lim)`
500			`rx_crc_lim <=#Tp 1'b1;`

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