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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_defines.v                                               ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2003/08/14 16:04:52  simons
// Artisan ram instances added.
//
// Revision 1.9  2003/06/27 20:56:15  simons
// Virtual silicon ram instances added.
//
// Revision 1.8  2003/06/09 11:32:36  mohor
// Ports added for the CAN_BIST.
//
// Revision 1.7  2003/03/20 16:51:55  mohor
// *** empty log message ***
//
// Revision 1.6  2003/03/12 04:19:13  mohor
// 8051 interface added (besides WISHBONE interface). Selection is made in
// can_defines.v file.
//
// Revision 1.5  2003/03/05 15:03:20  mohor
// Xilinx RAM added.
//
// Revision 1.4  2003/03/01 22:52:47  mohor
// Actel APA ram supported.
//
// Revision 1.3  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
 
// Uncomment following line if you want to use WISHBONE interface. Otherwise
// 8051 interface is used.
// `define   CAN_WISHBONE_IF
 
// Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)
 `define   ACTEL_APA_RAM
 
// Uncomment following line if you want to use CAN in Altera devices (embedded memory used)
// `define   ALTERA_RAM
 
// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
// `define   XILINX_RAM
 
// Uncomment the line for the ram used in ASIC implementation
// `define   VIRTUALSILICON_RAM
// `define   ARTISAN_RAM
 
// Uncomment the following line when RAM BIST is needed (ASIC implementation)
//`define CAN_BIST                    // Bist (for ASIC implementation)

Line No.	Rev	Author	Line
1	71	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002, 2003 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	124	mohor	`// Revision 1.10 2003/08/14 16:04:52 simons`
54			`// Artisan ram instances added.`
55			`//`
56	115	simons	`// Revision 1.9 2003/06/27 20:56:15 simons`
57			`// Virtual silicon ram instances added.`
58			`//`
59	95	simons	`// Revision 1.8 2003/06/09 11:32:36 mohor`
60			`// Ports added for the CAN_BIST.`
61			`//`
62	71	mohor	`// Revision 1.7 2003/03/20 16:51:55 mohor`
63			`// * empty log message *`
64			`//`
65			`// Revision 1.6 2003/03/12 04:19:13 mohor`
66			`// 8051 interface added (besides WISHBONE interface). Selection is made in`
67			`// can_defines.v file.`
68			`//`
69			`// Revision 1.5 2003/03/05 15:03:20 mohor`
70			`// Xilinx RAM added.`
71			`//`
72			`// Revision 1.4 2003/03/01 22:52:47 mohor`
73			`// Actel APA ram supported.`
74			`//`
75			`// Revision 1.3 2003/02/09 02:24:33 mohor`
76			`// Bosch license warning added. Error counters finished. Overload frames`
77			`// still need to be fixed.`
78			`//`
79			`// Revision 1.2 2002/12/27 00:12:52 mohor`
80			`// Header changed, testbench improved to send a frame (crc still missing).`
81			`//`
82			`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
83			`// Initial`
84			`//`
85			`//`
86			`//`
87
88
89			`// Uncomment following line if you want to use WISHBONE interface. Otherwise`
90			`// 8051 interface is used.`
91			// `define CAN_WISHBONE_IF
92
93			`// Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)`
94			`define ACTEL_APA_RAM
95
96	124	mohor	`// Uncomment following line if you want to use CAN in Altera devices (embedded memory used)`
97			// `define ALTERA_RAM
98
99	71	mohor	`// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)`
100			// `define XILINX_RAM
101
102	115	simons	`// Uncomment the line for the ram used in ASIC implementation`
103	95	simons	// `define VIRTUALSILICON_RAM
104	115	simons	// `define ARTISAN_RAM
105	95	simons
106	71	mohor	`// Uncomment the following line when RAM BIST is needed (ASIC implementation)`
107			//`define CAN_BIST // Bist (for ASIC implementation)

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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_defines.v] - Blame information for rev 124