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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_defines.v] - Blame information for rev 59

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_defines.v                                               ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2003/03/05 15:03:20  mohor
// Xilinx RAM added.
//
// Revision 1.4  2003/03/01 22:52:47  mohor
// Actel APA ram supported.
//
// Revision 1.3  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
 
// Uncomment following line if you want to use WISHBONE interface. Otherwise
// 8051 interface is used.
// `define   CAN_WISHBONE_IF
 
// Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)
// `define   ACTEL_APA_RAM
 
// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
// `define   XILINX_RAM

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_defines.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	2	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	59	mohor	`// Revision 1.5 2003/03/05 15:03:20 mohor`
54			`// Xilinx RAM added.`
55			`//`
56	51	mohor	`// Revision 1.4 2003/03/01 22:52:47 mohor`
57			`// Actel APA ram supported.`
58			`//`
59	48	mohor	`// Revision 1.3 2003/02/09 02:24:33 mohor`
60			`// Bosch license warning added. Error counters finished. Overload frames`
61			`// still need to be fixed.`
62			`//`
63	28	mohor	`// Revision 1.2 2002/12/27 00:12:52 mohor`
64			`// Header changed, testbench improved to send a frame (crc still missing).`
65			`//`
66	9	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
67			`// Initial`
68	2	mohor	`//`
69			`//`
70	9	mohor	`//`
71	2	mohor
72	48	mohor
73	59	mohor	`// Uncomment following line if you want to use WISHBONE interface. Otherwise`
74			`// 8051 interface is used.`
75			// `define CAN_WISHBONE_IF
76
77	48	mohor	`// Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)`
78	51	mohor	// `define ACTEL_APA_RAM
79
80			`// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)`
81			// `define XILINX_RAM

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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_defines.v] - Blame information for rev 59