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[/] [can/] [tags/] [rel_22/] [sim/] [rtl_sim/] [run/] [run_sim.scr] - Blame information for rev 161

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Line No. Rev Author Line
1 2 mohor
#!/bin/csh -f
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if ( $# < 1 ) then
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    echo "First argument must be a top level module name!"
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    exit
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else
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    set SIM_TOP = $1
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endif
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set current_par = 1
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set output_waveform = 0
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while ( $current_par < $# )
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    @ current_par = $current_par + 1
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    case wave:
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        @ output_waveform = 1
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        breaksw
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    default:
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        echo 'Unknown option "'$argv[$current_par]'"!'
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        exit
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        breaksw
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    endsw
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end
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echo "-CDSLIB ../bin/cds.lib"          > ncvlog.args
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echo "-HDLVAR ../bin/hdl.var"         >> ncvlog.args
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echo "-MESSAGES"                      >> ncvlog.args
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echo "-INCDIR ../../../bench/verilog" >> ncvlog.args
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echo "-INCDIR ../../../rtl/verilog"   >> ncvlog.args
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echo "-NOCOPYRIGHT"                   >> ncvlog.args
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echo "-LOGFILE ../log/ncvlog.log"     >> ncvlog.args
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foreach filename ( `cat ../bin/rtl_file_list` )
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    echo "../../../rtl/verilog/"$filename >> ncvlog.args
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end
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36 141 igorm
#foreach filename ( `cat ../bin/memory_file_list` )
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#    echo "../../../bench/verilog/"$filename >> ncvlog.args
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#end
39 48 mohor
 
40 2 mohor
foreach filename ( `cat ../bin/sim_file_list` )
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    echo "../../../bench/verilog/"$filename >> ncvlog.args
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end
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44 141 igorm
#echo "../../../../bist/rtl/verilog/bist.v" >> ncvlog.args
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#echo "../../../../bist/rtl/verilog/bist_dp_top.v" >> ncvlog.args
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#echo "../../../../bist/rtl/verilog/bist_sp_top.v" >> ncvlog.args
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#echo "../../../../bist/rtl/verilog/bist_tp_top.v" >> ncvlog.args
48 119 mohor
 
49 2 mohor
ncvlog -f ncvlog.args
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echo "-MESSAGES"                             > ncelab.args
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echo "-NOCOPYRIGHT"                         >> ncelab.args
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echo "-CDSLIB ../bin/cds.lib"               >> ncelab.args
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echo "-HDLVAR ../bin/hdl.var"               >> ncelab.args
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echo "-LOGFILE ../log/ncelab.log"           >> ncelab.args
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echo "-SNAPSHOT worklib.bench:rtl"          >> ncelab.args
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echo "-NO_TCHK_MSG"                         >> ncelab.args
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echo "-ACCESS +RWC"                         >> ncelab.args
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echo worklib.$SIM_TOP                       >> ncelab.args
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ncelab -f ncelab.args
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echo "-MESSAGES"                   > ncsim.args
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echo "-NOCOPYRIGHT"               >> ncsim.args
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echo "-CDSLIB ../bin/cds.lib"     >> ncsim.args
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echo "-HDLVAR ../bin/hdl.var"     >> ncsim.args
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echo "-INPUT ncsim.tcl"           >> ncsim.args
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echo "-LOGFILE ../log/ncsim.log"  >> ncsim.args
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echo "worklib.bench:rtl"          >> ncsim.args
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if ( $output_waveform ) then
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    echo "database -open waves -shm -into ../out/waves.shm"             > ./ncsim.tcl
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    echo "probe -create -database waves $SIM_TOP -shm -all -depth all" >> ./ncsim.tcl
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    echo "run"                                                         >> ./ncsim.tcl
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else
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    echo "run"  > ./ncsim.tcl
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endif
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echo "quit" >> ncsim.tcl
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ncsim -LICQUEUE -f ./ncsim.args

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