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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_testbench.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2002/12/28 04:13:53  mohor
// Backup version.
//
// Revision 1.6  2002/12/27 00:12:48  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.5  2002/12/26 16:00:29  mohor
// Testbench define file added. Clock divider register added.
//
// Revision 1.4  2002/12/26 01:33:01  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:12  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:16:54  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
`include "can_testbench_defines.v"
 
module can_testbench();
 
 
 
parameter Tp = 1;
parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
 
 
 
reg         clk;
reg         rst;
reg   [7:0] data_in;
wire  [7:0] data_out;
reg         cs, rw;
reg   [7:0] addr;
reg         rx;
integer     start_tb;
 
// Instantiate can_top module
can_top i_can_top
(
  .clk(clk),
  .rst(rst),
  .data_in(data_in),
  .data_out(data_out),
  .cs(cs),
  .rw(rw),
  .addr(addr),
  .rx(rx)
);
 
 
// Generate clock signal 24 MHz
initial
begin
  clk=0;
  forever #20 clk = ~clk;
end
 
initial
begin
  start_tb = 0;
  data_in = 'hz;
  cs = 0;
  rw = 'hz;
  addr = 'hz;
  rx = 1;
  rst = 1;
  #200 rst = 0;
  #200 start_tb = 1;
end
 
 
// Main testbench
initial
begin
  wait(start_tb);
 
  // Set bus timing register 0
  write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
 
  // Set bus timing register 1
  write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
 
  // Set Clock Divider register
  write_register(8'h31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0});    // Setting the normal mode (not extended)
 
  // Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
  if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
    begin
      // Set Acceptance Code and Acceptance Mask registers
      write_register(8'h16, 8'ha6); // acceptance code 0
      write_register(8'h17, 8'hb0); // acceptance code 1
      write_register(8'h18, 8'h12); // acceptance code 2
      write_register(8'h19, 8'h34); // acceptance code 3
      write_register(8'h20, 8'h0); // acceptance mask 0
      write_register(8'h21, 8'h0); // acceptance mask 1
      write_register(8'h22, 8'h0); // acceptance mask 2
      write_register(8'h23, 8'h0); // acceptance mask 3
    end
  else
    begin
      // Set Acceptance Code and Acceptance Mask registers
      write_register(8'h4, 8'ha6); // acceptance code
      write_register(8'h5, 8'h00); // acceptance mask
    end
 
  #10;
  repeat (1000) @ (posedge clk);
 
  // Switch-off reset mode
  write_register(8'h0, {7'h0, ~(`CAN_MODE_RESET)});
 
  repeat (BRP) @ (posedge clk);   // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
                                  // This difference is resynchronized later.
  repeat (7) send_bit(1);         // Sending EOF
 
//  test_synchronization;
 
 
 
  if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
    begin
      send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
//      send_frame(0, 1, 29'h12567635, 2, 15'h75b4); // mode, rtr, id, length, crc
    end
  else
    begin
      send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
    end
 
 
  repeat (50000) @ (posedge clk);
  $display("CAN Testbench finished.");
  $stop;
end
 
 
 
 
task write_register;
  input [7:0] reg_addr;
  input [7:0] reg_data;
 
  begin
    @ (posedge clk);
    #1;
    addr = reg_addr;
    data_in = reg_data;
    cs = 1;
    rw = 0;
    @ (posedge clk);
    #1;
    addr = 'hz;
    data_in = 'hz;
    cs = 0;
    rw = 'hz;
  end
endtask
 
 
task test_synchronization;
  begin
    // Hard synchronization
    #1 rx=0;
    repeat (2*BRP) @ (posedge clk);
    repeat (8*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
 
    // Resynchronization on time
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
 
    // Resynchronization late
    repeat (BRP) @ (posedge clk);
    repeat (BRP) @ (posedge clk);
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
 
    // Resynchronization early
    repeat (8*BRP) @ (posedge clk);   // two frames too early
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
  end
endtask
 
 
task send_bit;
  input bit;
  integer cnt;
  begin
    #1 rx=bit;
    repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
  end
endtask
 
 
task send_frame;
  input mode;
  input remote_trans_req;
  input [28:0] id;
  input  [3:0] length;
  input [14:0] crc;
  integer cnt;
 
  reg [28:0] data;
  reg  [3:0] len;
  begin
 
    data = id;
    len  = length;
 
    send_bit(0);                        // SOF
 
    if(mode)      // Extended format
      begin
        for (cnt=0; cnt<11; cnt=cnt+1)  // 11 bit ID
          begin
            send_bit(data[28]);
            data=data<<1;
          end
        send_bit(1);                    // SRR
        send_bit(1);                    // IDE
 
        for (cnt=11; cnt<29; cnt=cnt+1)  // 18 bit ID
          begin
            send_bit(data[28]);
            data=data<<1;
          end
 
        send_bit(remote_trans_req);
        send_bit(0);                    // r1 (reserved 1)
        send_bit(0);                    // r0 (reserved 0)
 
        for (cnt=0; cnt<4; cnt=cnt+1)   // DLC (length)
          begin
            send_bit(len[3]);
            len=len<<1;
          end
      end
    else                  // Standard format
      begin
        for (cnt=0; cnt<11; cnt=cnt+1)  // 11 bit ID
          begin
            send_bit(data[10]);
            data=data<<1;
          end
        send_bit(remote_trans_req);
        send_bit(0);                    // IDE
        send_bit(0);                    // r0 (reserved 0)
 
        for (cnt=0; cnt<4; cnt=cnt+1)   // DLC (length)
          begin
            send_bit(len[3]);
            len=len<<1;
          end
      end                 // End header
 
 
    if(length)    // Send data if length is > 0
      begin
        for (cnt=1; cnt<=(2*length); cnt=cnt+1)  // data   (we are sending nibbles)
          begin
            send_bit(cnt[3]);
            send_bit(cnt[2]);
            send_bit(cnt[1]);
            send_bit(cnt[0]);
          end
      end
 
    // Send CRC
    data[14:0] = crc[14:0];
    for (cnt=0; cnt<15; cnt=cnt+1)  // 15 bit CRC
      begin
        send_bit(data[14]);
        data=data<<1;
      end
 
    // Send CRC delimiter
    send_bit(1);
 
    // Send ACK slot
    send_bit(1);
 
    // Send Ack delimiter
    send_bit(1);
 
 
    // Nothing send after the data (just recessive bit)
    send_bit(1);
 
 
 
  end
endtask
 
 
// State machine monitor (btl)
always @ (posedge clk)
begin
  if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
     can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
    begin
      $display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);
      #1000;
      $stop;
    end
 
  if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
     can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
    begin
      $display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);
      #1000;
      $stop;
    end
end
 
/* stuff_error monitor (bsp)
always @ (posedge clk)
begin
  if(can_testbench.i_can_top.i_can_bsp.stuff_error)
    begin
      $display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);
      $stop;                                      After everything is finished add another condition (something like & (~idle)) and enable stop
    end
end
*/
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_testbench.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	11	mohor	`// Revision 1.7 2002/12/28 04:13:53 mohor`
49			`// Backup version.`
50			`//`
51	10	mohor	`// Revision 1.6 2002/12/27 00:12:48 mohor`
52			`// Header changed, testbench improved to send a frame (crc still missing).`
53			`//`
54	9	mohor	`// Revision 1.5 2002/12/26 16:00:29 mohor`
55			`// Testbench define file added. Clock divider register added.`
56			`//`
57	8	mohor	`// Revision 1.4 2002/12/26 01:33:01 mohor`
58			`// Tripple sampling supported.`
59			`//`
60	7	mohor	`// Revision 1.3 2002/12/25 23:44:12 mohor`
61			`// Commented lines removed.`
62			`//`
63	6	mohor	`// Revision 1.2 2002/12/25 14:16:54 mohor`
64			`// Synchronization working.`
65			`//`
66	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
67			`// Initial`
68	2	mohor	`//`
69			`//`
70	5	mohor	`//`
71	2	mohor
72			`// synopsys translate_off`
73			`include "timescale.v"
74			`// synopsys translate_on`
75			`include "can_defines.v"
76	8	mohor	`include "can_testbench_defines.v"
77	2	mohor
78			`module can_testbench();`
79
80
81
82			`parameter Tp = 1;`
83	8	mohor	parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
84	2	mohor
85
86
87			`reg clk;`
88			`reg rst;`
89			`reg [7:0] data_in;`
90			`wire [7:0] data_out;`
91			`reg cs, rw;`
92			`reg [7:0] addr;`
93			`reg rx;`
94			`integer start_tb;`
95
96	11	mohor	`// Instantiate can_top module`
97	2	mohor	`can_top i_can_top`
98			`(`
99			`.clk(clk),`
100			`.rst(rst),`
101			`.data_in(data_in),`
102			`.data_out(data_out),`
103			`.cs(cs),`
104			`.rw(rw),`
105			`.addr(addr),`
106	10	mohor	`.rx(rx)`
107	2	mohor	`);`
108
109
110			`// Generate clock signal 24 MHz`
111			`initial`
112			`begin`
113			`clk=0;`
114			`forever #20 clk = ~clk;`
115			`end`
116
117			`initial`
118			`begin`
119			`start_tb = 0;`
120			`data_in = 'hz;`
121			`cs = 0;`
122			`rw = 'hz;`
123			`addr = 'hz;`
124			`rx = 1;`
125			`rst = 1;`
126			`#200 rst = 0;`
127			`#200 start_tb = 1;`
128			`end`
129
130
131			`// Main testbench`
132			`initial`
133			`begin`
134			`wait(start_tb);`
135
136	11	mohor	`// Set bus timing register 0`
137	8	mohor	write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
138
139	11	mohor	`// Set bus timing register 1`
140	8	mohor	write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
141	11	mohor
142			`// Set Clock Divider register`
143			write_register(8'h31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
144
145			`// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode`
146			if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
147			`begin`
148			`// Set Acceptance Code and Acceptance Mask registers`
149			`write_register(8'h16, 8'ha6); // acceptance code 0`
150			`write_register(8'h17, 8'hb0); // acceptance code 1`
151			`write_register(8'h18, 8'h12); // acceptance code 2`
152			`write_register(8'h19, 8'h34); // acceptance code 3`
153			`write_register(8'h20, 8'h0); // acceptance mask 0`
154			`write_register(8'h21, 8'h0); // acceptance mask 1`
155			`write_register(8'h22, 8'h0); // acceptance mask 2`
156			`write_register(8'h23, 8'h0); // acceptance mask 3`
157			`end`
158			`else`
159			`begin`
160			`// Set Acceptance Code and Acceptance Mask registers`
161			`write_register(8'h4, 8'ha6); // acceptance code`
162			`write_register(8'h5, 8'h00); // acceptance mask`
163			`end`
164	2	mohor
165			`#10;`
166			`repeat (1000) @ (posedge clk);`
167
168	11	mohor	`// Switch-off reset mode`
169	10	mohor	write_register(8'h0, {7'h0, ~(`CAN_MODE_RESET)});
170
171			`repeat (BRP) @ (posedge clk); // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible`
172			`// This difference is resynchronized later.`
173	11	mohor	`repeat (7) send_bit(1); // Sending EOF`
174	10	mohor
175	9	mohor	`// test_synchronization;`
176	10	mohor
177
178
179	11	mohor	if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
180			`begin`
181			`send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc`
182			`// send_frame(0, 1, 29'h12567635, 2, 15'h75b4); // mode, rtr, id, length, crc`
183			`end`
184			`else`
185			`begin`
186			`send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc`
187			`end`
188	9	mohor
189	5	mohor
190	2	mohor	`repeat (50000) @ (posedge clk);`
191			`$display("CAN Testbench finished.");`
192			`$stop;`
193			`end`
194
195
196
197
198			`task write_register;`
199			`input [7:0] reg_addr;`
200			`input [7:0] reg_data;`
201
202			`begin`
203			`@ (posedge clk);`
204			`#1;`
205			`addr = reg_addr;`
206			`data_in = reg_data;`
207			`cs = 1;`
208			`rw = 0;`
209			`@ (posedge clk);`
210			`#1;`
211			`addr = 'hz;`
212			`data_in = 'hz;`
213			`cs = 0;`
214			`rw = 'hz;`
215			`end`
216			`endtask`
217	7	mohor
218
219	8	mohor	`task test_synchronization;`
220			`begin`
221			`// Hard synchronization`
222			`#1 rx=0;`
223			`repeat (2*BRP) @ (posedge clk);`
224			`repeat (8*BRP) @ (posedge clk);`
225			`#1 rx=1;`
226			`repeat (10*BRP) @ (posedge clk);`
227
228			`// Resynchronization on time`
229			`#1 rx=0;`
230			`repeat (10*BRP) @ (posedge clk);`
231			`#1 rx=1;`
232			`repeat (10*BRP) @ (posedge clk);`
233
234			`// Resynchronization late`
235			`repeat (BRP) @ (posedge clk);`
236			`repeat (BRP) @ (posedge clk);`
237			`#1 rx=0;`
238			`repeat (10*BRP) @ (posedge clk);`
239			`#1 rx=1;`
240
241			`// Resynchronization early`
242			`repeat (8*BRP) @ (posedge clk); // two frames too early`
243			`#1 rx=0;`
244			`repeat (10*BRP) @ (posedge clk);`
245			`#1 rx=1;`
246			`repeat (10*BRP) @ (posedge clk);`
247			`end`
248			`endtask`
249	7	mohor
250	8	mohor
251	9	mohor	`task send_bit;`
252			`input bit;`
253			`integer cnt;`
254			`begin`
255			`#1 rx=bit;`
256			repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
257			`end`
258			`endtask`
259
260
261	8	mohor	`task send_frame;`
262			`input mode;`
263	11	mohor	`input remote_trans_req;`
264	9	mohor	`input [28:0] id;`
265			`input [3:0] length;`
266	11	mohor	`input [14:0] crc;`
267	9	mohor	`integer cnt;`
268
269			`reg [28:0] data;`
270			`reg [3:0] len;`
271	8	mohor	`begin`
272	9	mohor
273			`data = id;`
274			`len = length;`
275
276			`send_bit(0); // SOF`
277
278			`if(mode) // Extended format`
279			`begin`
280			`for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID`
281			`begin`
282			`send_bit(data[28]);`
283			`data=data<<1;`
284			`end`
285			`send_bit(1); // SRR`
286			`send_bit(1); // IDE`
287
288			`for (cnt=11; cnt<29; cnt=cnt+1) // 18 bit ID`
289			`begin`
290			`send_bit(data[28]);`
291			`data=data<<1;`
292			`end`
293
294	11	mohor	`send_bit(remote_trans_req);`
295	9	mohor	`send_bit(0); // r1 (reserved 1)`
296			`send_bit(0); // r0 (reserved 0)`
297
298			`for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)`
299			`begin`
300			`send_bit(len[3]);`
301			`len=len<<1;`
302			`end`
303			`end`
304			`else // Standard format`
305			`begin`
306			`for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID`
307			`begin`
308			`send_bit(data[10]);`
309			`data=data<<1;`
310			`end`
311	11	mohor	`send_bit(remote_trans_req);`
312	9	mohor	`send_bit(0); // IDE`
313			`send_bit(0); // r0 (reserved 0)`
314
315			`for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)`
316			`begin`
317			`send_bit(len[3]);`
318			`len=len<<1;`
319			`end`
320			`end // End header`
321
322
323	11	mohor	`if(length) // Send data if length is > 0`
324			`begin`
325			`for (cnt=1; cnt<=(2*length); cnt=cnt+1) // data (we are sending nibbles)`
326			`begin`
327			`send_bit(cnt[3]);`
328			`send_bit(cnt[2]);`
329			`send_bit(cnt[1]);`
330			`send_bit(cnt[0]);`
331			`end`
332			`end`
333
334			`// Send CRC`
335			`data[14:0] = crc[14:0];`
336			`for (cnt=0; cnt<15; cnt=cnt+1) // 15 bit CRC`
337			`begin`
338			`send_bit(data[14]);`
339			`data=data<<1;`
340			`end`
341	9	mohor
342	11	mohor	`// Send CRC delimiter`
343			`send_bit(1);`
344
345			`// Send ACK slot`
346			`send_bit(1);`
347
348			`// Send Ack delimiter`
349			`send_bit(1);`
350
351
352			`// Nothing send after the data (just recessive bit)`
353			`send_bit(1);`
354	9	mohor
355
356
357	8	mohor	`end`
358			`endtask`
359
360
361	11	mohor	`// State machine monitor (btl)`
362	7	mohor	`always @ (posedge clk)`
363			`begin`
364			`if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 \| can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 \|`
365			`can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)`
366	10	mohor	`begin`
367			`$display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);`
368			`#1000;`
369			`$stop;`
370			`end`
371	7	mohor
372			`if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 \| can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 \|`
373			`can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)`
374	10	mohor	`begin`
375			`$display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);`
376			`#1000;`
377			`$stop;`
378			`end`
379	7	mohor	`end`
380
381	10	mohor	`/* stuff_error monitor (bsp)`
382			`always @ (posedge clk)`
383			`begin`
384			`if(can_testbench.i_can_top.i_can_bsp.stuff_error)`
385			`begin`
386			`$display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);`
387			`$stop; After everything is finished add another condition (something like & (~idle)) and enable stop`
388			`end`
389			`end`
390			`*/`
391
392
393	2	mohor	`endmodule`

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