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1 83 mohor 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  can_testbench.v                                             ////
4 
////                                                              ////
5 
////                                                              ////
6 
////  This file is part of the CAN Protocol Controller            ////
7 
////  http://www.opencores.org/projects/can/                      ////
8 
////                                                              ////
9 
////                                                              ////
10 
////  Author(s):                                                  ////
11 
////       Igor Mohor                                             ////
12 
////       igorm@opencores.org                                    ////
13 
////                                                              ////
14 
////                                                              ////
15 
////  All additional information is available in the README.txt   ////
16 
////  file.                                                       ////
17 
////                                                              ////
18 
//////////////////////////////////////////////////////////////////////
19 
////                                                              ////
20 
//// Copyright (C) 2002, 2003 Authors                             ////
21 
////                                                              ////
22 
//// This source file may be used and distributed without         ////
23 
//// restriction provided that this copyright statement is not    ////
24 
//// removed from the file and that any derivative work contains  ////
25 
//// the original copyright notice and the associated disclaimer. ////
26 
////                                                              ////
27 
//// This source file is free software; you can redistribute it   ////
28 
//// and/or modify it under the terms of the GNU Lesser General   ////
29 
//// Public License as published by the Free Software Foundation; ////
30 
//// either version 2.1 of the License, or (at your option) any   ////
31 
//// later version.                                               ////
32 
////                                                              ////
33 
//// This source is distributed in the hope that it will be       ////
34 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37 
//// details.                                                     ////
38 
////                                                              ////
39 
//// You should have received a copy of the GNU Lesser General    ////
40 
//// Public License along with this source; if not, download it   ////
41 
//// from http://www.opencores.org/lgpl.shtml                     ////
42 
////                                                              ////
43 
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
44 
//// protected by patents. Anybody who wants to implement this    ////
45 
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
46 
//// from Bosch.                                                  ////
47 
////                                                              ////
48 
//////////////////////////////////////////////////////////////////////
49 
//
50 
// CVS Revision History
51 
//
52 
// $Log: not supported by cvs2svn $
53 140 igorm 
// Revision 1.39  2004/03/18 17:15:26  igorm
54 
// Signal bus_off_on added.
55 
//
56 139 igorm 
// Revision 1.38  2003/10/17 05:55:18  markom
57 
// mbist signals updated according to newest convention
58 
//
59 130 markom 
// Revision 1.37  2003/09/30 20:53:58  mohor
60 
// Fixing the core to be Bosch VHDL Reference compatible.
61 
//
62 127 mohor 
// Revision 1.36  2003/08/20 10:03:20  mohor
63 
// Artisan RAMs added.
64 
//
65 119 mohor 
// Revision 1.35  2003/06/17 15:14:48  mohor
66 
// cs_can_i is used only when WISHBONE interface is not used.
67 
//
68 83 mohor 
// Revision 1.34  2003/03/26 11:25:39  mohor
69 
// CAN inturrupt is active low.
70 
//
71 
// Revision 1.33  2003/03/14 19:37:30  mohor
72 
// ALE changes on negedge of clk.
73 
//
74 
// Revision 1.32  2003/03/12 05:57:36  mohor
75 
// Bidirectional port_0_i changed to port_0_io.
76 
// input cs_can changed to cs_can_i.
77 
//
78 
// Revision 1.31  2003/03/12 04:40:00  mohor
79 
// rd_i and wr_i are active high signals. If 8051 is connected, these two signals
80 
// need to be negated one level higher.
81 
//
82 
// Revision 1.30  2003/03/12 04:16:40  mohor
83 
// 8051 interface added (besides WISHBONE interface). Selection is made in
84 
// can_defines.v file.
85 
//
86 
// Revision 1.29  2003/03/05 15:33:37  mohor
87 
// tx_o is now tristated signal. tx_oen and tx_o combined together.
88 
//
89 
// Revision 1.28  2003/03/05 15:00:49  mohor
90 
// Top level signal names changed.
91 
//
92 
// Revision 1.27  2003/03/01 22:48:26  mohor
93 
// Actel APA ram supported.
94 
//
95 
// Revision 1.26  2003/02/19 14:43:17  mohor
96 
// CAN core finished. Host interface added. Registers finished.
97 
// Synchronization to the wishbone finished.
98 
//
99 
// Revision 1.25  2003/02/18 00:19:39  mohor
100 
// Temporary backup version (still fully operable).
101 
//
102 
// Revision 1.24  2003/02/14 20:16:53  mohor
103 
// Several registers added. Not finished, yet.
104 
//
105 
// Revision 1.23  2003/02/12 14:28:30  mohor
106 
// Errors monitoring improved. arbitration_lost improved.
107 
//
108 
// Revision 1.22  2003/02/11 00:57:19  mohor
109 
// Wishbone interface added.
110 
//
111 
// Revision 1.21  2003/02/09 18:40:23  mohor
112 
// Overload fixed. Hard synchronization also enabled at the last bit of
113 
// interframe.
114 
//
115 
// Revision 1.20  2003/02/09 02:24:11  mohor
116 
// Bosch license warning added. Error counters finished. Overload frames
117 
// still need to be fixed.
118 
//
119 
// Revision 1.19  2003/02/04 17:24:33  mohor
120 
// Backup.
121 
//
122 
// Revision 1.18  2003/02/04 14:34:45  mohor
123 
// *** empty log message ***
124 
//
125 
// Revision 1.17  2003/01/31 01:13:31  mohor
126 
// backup.
127 
//
128 
// Revision 1.16  2003/01/16 13:36:14  mohor
129 
// Form error supported. When receiving messages, last bit of the end-of-frame
130 
// does not generate form error. Receiver goes to the idle mode one bit sooner.
131 
// (CAN specification ver 2.0, part B, page 57).
132 
//
133 
// Revision 1.15  2003/01/15 21:05:06  mohor
134 
// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
135 
//
136 
// Revision 1.14  2003/01/15 14:40:16  mohor
137 
// RX state machine fixed to receive "remote request" frames correctly. No
138 
// data bytes are written to fifo when such frames are received.
139 
//
140 
// Revision 1.13  2003/01/15 13:16:42  mohor
141 
// When a frame with "remote request" is received, no data is stored to
142 
// fifo, just the frame information (identifier, ...). Data length that
143 
// is stored is the received data length and not the actual data length
144 
// that is stored to fifo.
145 
//
146 
// Revision 1.12  2003/01/14 17:25:03  mohor
147 
// Addresses corrected to decimal values (previously hex).
148 
//
149 
// Revision 1.11  2003/01/14 12:19:29  mohor
150 
// rx_fifo is now working.
151 
//
152 
// Revision 1.10  2003/01/10 17:51:28  mohor
153 
// Temporary version (backup).
154 
//
155 
// Revision 1.9  2003/01/09 21:54:39  mohor
156 
// rx fifo added. Not 100 % verified, yet.
157 
//
158 
// Revision 1.8  2003/01/08 02:09:43  mohor
159 
// Acceptance filter added.
160 
//
161 
// Revision 1.7  2002/12/28 04:13:53  mohor
162 
// Backup version.
163 
//
164 
// Revision 1.6  2002/12/27 00:12:48  mohor
165 
// Header changed, testbench improved to send a frame (crc still missing).
166 
//
167 
// Revision 1.5  2002/12/26 16:00:29  mohor
168 
// Testbench define file added. Clock divider register added.
169 
//
170 
// Revision 1.4  2002/12/26 01:33:01  mohor
171 
// Tripple sampling supported.
172 
//
173 
// Revision 1.3  2002/12/25 23:44:12  mohor
174 
// Commented lines removed.
175 
//
176 
// Revision 1.2  2002/12/25 14:16:54  mohor
177 
// Synchronization working.
178 
//
179 
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
180 
// Initial
181 
//
182 
//
183 
//
184 
 
185 
// synopsys translate_off
186 
`include "timescale.v"
187 
// synopsys translate_on
188 
`include "can_defines.v"
189 
`include "can_testbench_defines.v"
190 
 
191 
module can_testbench();
192 
 
193 
 
194 
 
195 
parameter Tp = 1;
196 
parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
197 
 
198 
 
199 
`ifdef CAN_WISHBONE_IF
200 
  reg         wb_clk_i;
201 
  reg         wb_rst_i;
202 
  reg   [7:0] wb_dat_i;
203 
  wire  [7:0] wb_dat_o;
204 
  reg         wb_cyc_i;
205 
  reg         wb_stb_i;
206 
  reg         wb_we_i;
207 
  reg   [7:0] wb_adr_i;
208 
  wire        wb_ack_o;
209 
  reg         wb_free;
210 
`else
211 
  reg         rst_i;
212 
  reg         ale_i;
213 
  reg         rd_i;
214 
  reg         wr_i;
215 
  wire  [7:0] port_0;
216 
  wire  [7:0] port_0_i;
217 
  reg   [7:0] port_0_o;
218 
  reg         port_0_en;
219 
  reg         port_free;
220 
`endif
221 
 
222 
 
223 
reg         cs_can;
224 
reg         clk;
225 
reg         rx;
226 
wire        tx;
227 119 mohor 
wire        tx_i;
228 139 igorm 
wire        bus_off_on;
229 83 mohor 
wire        irq;
230 
wire        clkout;
231 
 
232 
wire        rx_and_tx;
233 
 
234 
integer     start_tb;
235 
reg   [7:0] tmp_data;
236 
reg         delayed_tx;
237 
reg         tx_bypassed;
238 
reg         extended_mode;
239 
 
240 
 
241 
// Instantiate can_top module
242 
can_top i_can_top
243 
(
244 
`ifdef CAN_WISHBONE_IF
245 
  .wb_clk_i(wb_clk_i),
246 
  .wb_rst_i(wb_rst_i),
247 
  .wb_dat_i(wb_dat_i),
248 
  .wb_dat_o(wb_dat_o),
249 
  .wb_cyc_i(wb_cyc_i),
250 
  .wb_stb_i(wb_stb_i),
251 
  .wb_we_i(wb_we_i),
252 
  .wb_adr_i(wb_adr_i),
253 
  .wb_ack_o(wb_ack_o),
254 
`else
255 
  .cs_can_i(cs_can),
256 
  .rst_i(rst_i),
257 
  .ale_i(ale_i),
258 
  .rd_i(rd_i),
259 
  .wr_i(wr_i),
260 
  .port_0_io(port_0),
261 
`endif
262 
  .clk_i(clk),
263 
  .rx_i(rx_and_tx),
264 119 mohor 
  .tx_o(tx_i),
265 139 igorm 
  .bus_off_on(bus_off_on),
266 83 mohor 
  .irq_on(irq),
267 
  .clkout_o(clkout)
268 119 mohor 
 
269 
  // Bist
270 
`ifdef CAN_BIST
271 
  ,
272 
  // debug chain signals
273 130 markom 
  .mbist_si_i(1'b0),       // bist scan serial in
274 
  .mbist_so_o(),           // bist scan serial out
275 
  .mbist_ctrl_i(3'b001)    // mbist scan {enable, clock, reset}
276 119 mohor 
`endif
277 83 mohor 
);
278 
 
279 
 
280 119 mohor 
// Combining tx with the output enable signal.
281 140 igorm 
assign tx = bus_off_on? tx_i : 1'bz;
282 119 mohor 
 
283 83 mohor 
`ifdef CAN_WISHBONE_IF
284 
  // Generate wishbone clock signal 10 MHz
285 
  initial
286 
  begin
287 
    wb_clk_i=0;
288 
    forever #50 wb_clk_i = ~wb_clk_i;
289 
  end
290 
`endif
291 
 
292 
 
293 
`ifdef CAN_WISHBONE_IF
294 
`else
295 
  assign port_0_i = port_0;
296 
  assign port_0 = port_0_en? port_0_o : 8'hz;
297 
`endif
298 
 
299 
 
300 127 mohor 
// Generate clock signal 25 MHz
301 83 mohor 
initial
302 
begin
303 
  clk=0;
304 127 mohor 
  forever #20 clk = ~clk;
305 83 mohor 
end
306 
 
307 
 
308 
initial
309 
begin
310 
  start_tb = 0;
311 
  cs_can = 0;
312 
  rx = 1;
313 
  extended_mode = 0;
314 
  tx_bypassed = 0;
315 
 
316 
  `ifdef CAN_WISHBONE_IF
317 
    wb_dat_i = 'hz;
318 
    wb_cyc_i = 0;
319 
    wb_stb_i = 0;
320 
    wb_we_i = 'hz;
321 
    wb_adr_i = 'hz;
322 
    wb_free = 1;
323 
    wb_rst_i = 1;
324 
    #200 wb_rst_i = 0;
325 
    #200 start_tb = 1;
326 
  `else
327 
    rst_i = 1'b0;
328 
    ale_i = 1'b0;
329 
    rd_i  = 1'b0;
330 
    wr_i  = 1'b0;
331 
    port_0_o = 8'h0;
332 
    port_0_en = 0;
333 
    port_free = 1;
334 
    rst_i = 1;
335 
    #200 rst_i = 0;
336 
    #200 start_tb = 1;
337 
  `endif
338 
end
339 
 
340 
 
341 
 
342 
 
343 
// Generating delayed tx signal (CAN transciever delay)
344 
always
345 
begin
346 
  wait (tx);
347 
  repeat (4*BRP) @ (posedge clk);   // 4 time quants delay
348 
  #1 delayed_tx = tx;
349 
  wait (~tx);
350 
  repeat (4*BRP) @ (posedge clk);   // 4 time quants delay
351 
  #1 delayed_tx = tx;
352 
end
353 
 
354 
//assign rx_and_tx = rx & delayed_tx;   FIX ME !!!
355 
assign rx_and_tx = rx & (delayed_tx | tx_bypassed);   // When this signal is on, tx is not looped back to the rx.
356 
 
357 
 
358 
// Main testbench
359 
initial
360 
begin
361 
  wait(start_tb);
362 
 
363 
  // Set bus timing register 0
364 
  write_register(8'd6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
365 
 
366 
  // Set bus timing register 1
367 
  write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
368 
 
369 
 
370 
  // Set Clock Divider register
371 
  extended_mode = 1'b0;
372 
  write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0});   // Setting the normal mode (not extended)
373 
 
374 
 
375 
  // Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
376 
/*
377 
  // Set Acceptance Code and Acceptance Mask registers
378 
  write_register(8'd16, 8'ha6); // acceptance code 0
379 
  write_register(8'd17, 8'hb0); // acceptance code 1
380 
  write_register(8'd18, 8'h12); // acceptance code 2
381 
  write_register(8'd19, 8'h30); // acceptance code 3
382 
  write_register(8'd20, 8'h0); // acceptance mask 0
383 
  write_register(8'd21, 8'h0); // acceptance mask 1
384 
  write_register(8'd22, 8'h00); // acceptance mask 2
385 
  write_register(8'd23, 8'h00); // acceptance mask 3
386 
*/
387 
 
388 
  // Set Acceptance Code and Acceptance Mask registers
389 
  write_register(8'd4, 8'he8); // acceptance code
390 
  write_register(8'd5, 8'h0f); // acceptance mask
391 
 
392 
  #10;
393 
  repeat (1000) @ (posedge clk);
394 
 
395 
  // Switch-off reset mode
396 
  write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
397 
 
398 
  repeat (BRP) @ (posedge clk);   // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
399 
                                  // This difference is resynchronized later.
400 
 
401 
  // After exiting the reset mode sending bus free
402 
  repeat (11) send_bit(1);
403 
 
404 127 mohor 
  test_synchronization;       // test currently switched off
405 83 mohor 
//  test_empty_fifo_ext;        // test currently switched off
406 
//  test_full_fifo_ext;         // test currently switched off
407 
//  send_frame_ext;             // test currently switched off
408 
//  test_empty_fifo;            // test currently switched off
409 127 mohor 
//  test_full_fifo;             // test currently switched on
410 83 mohor 
//  bus_off_test;               // test currently switched off
411 
//  forced_bus_off;             // test currently switched off
412 
//  send_frame_basic;           // test currently switched off
413 
//  send_frame_extended;        // test currently switched off
414 
//  self_reception_request;       // test currently switched off
415 
//  manual_frame_basic;         // test currently switched off
416 
//  manual_frame_ext;           // test currently switched off
417 
 
418 
  $display("CAN Testbench finished !");
419 
  $stop;
420 
end
421 
 
422 
 
423 
task forced_bus_off;    // Forcing bus-off by writinf to tx_err_cnt register
424 
  begin
425 
 
426 
    // Switch-on reset mode
427 
    write_register(8'd0, {7'h0, `CAN_MODE_RESET});
428 
 
429 
    // Set Clock Divider register
430 
    write_register(8'd31, {1'b1, 7'h0});    // Setting the extended mode (not normal)
431 
 
432 
    // Write 255 to tx_err_cnt register - Forcing bus-off
433 
    write_register(8'd15, 255);
434 
 
435 
    // Switch-off reset mode
436 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
437 
 
438 
//    #1000000;
439 
    #2500000;
440 
 
441 
 
442 
    // Switch-on reset mode
443 
    write_register(8'd0, {7'h0, `CAN_MODE_RESET});
444 
 
445 
    // Write 245 to tx_err_cnt register
446 
    write_register(8'd15, 245);
447 
 
448 
    // Switch-off reset mode
449 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
450 
 
451 
    #1000000;
452 
 
453 
 
454 
  end
455 
endtask   // forced_bus_off
456 
 
457 
 
458 
task manual_frame_basic;    // Testbench sends a basic format frame
459 
  begin
460 
 
461 
 
462 
    // Switch-on reset mode
463 
    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
464 
 
465 
    // Set Acceptance Code and Acceptance Mask registers
466 
    write_register(8'd4, 8'h28); // acceptance code
467 
    write_register(8'd5, 8'hff); // acceptance mask
468 
 
469 
    repeat (100) @ (posedge clk);
470 
 
471 
    // Switch-off reset mode
472 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
473 
 
474 
    // After exiting the reset mode sending bus free
475 
    repeat (11) send_bit(1);
476 
 
477 
 
478 
    write_register(8'd10, 8'h55); // Writing ID[10:3] = 0x55
479 
    write_register(8'd11, 8'h57); // Writing ID[2:0] = 0x2, rtr = 1, length = 7
480 
    write_register(8'd12, 8'h00); // data byte 1
481 
    write_register(8'd13, 8'h00); // data byte 2
482 
    write_register(8'd14, 8'h00); // data byte 3
483 
    write_register(8'd15, 8'h00); // data byte 4
484 
    write_register(8'd16, 8'h00); // data byte 5
485 
    write_register(8'd17, 8'h00); // data byte 6
486 
    write_register(8'd18, 8'h00); // data byte 7
487 
    write_register(8'd19, 8'h00); // data byte 8
488 
 
489 
    tx_bypassed = 1;    // When this signal is on, tx is not looped back to the rx.
490 
 
491 
    fork
492 
      begin
493 
//        tx_request_command;
494 
        self_reception_request_command;
495 
      end
496 
 
497 
      begin
498 
        #2200;
499 
 
500 
 
501 
        repeat (1)
502 
        begin
503 
          send_bit(0);  // SOF
504 
          send_bit(0);  // ID
505 
          send_bit(1);  // ID
506 
          send_bit(0);  // ID
507 
          send_bit(1);  // ID
508 
          send_bit(0);  // ID
509 
          send_bit(1);  // ID
510 
          send_bit(0);  // ID
511 
          send_bit(1);  // ID
512 
          send_bit(0);  // ID
513 
          send_bit(1);  // ID
514 
          send_bit(0);  // ID
515 
          send_bit(1);  // RTR
516 
          send_bit(0);  // IDE
517 
          send_bit(0);  // r0
518 
          send_bit(0);  // DLC
519 
          send_bit(1);  // DLC
520 
          send_bit(1);  // DLC
521 
          send_bit(1);  // DLC
522 
          send_bit(1);  // CRC
523 
          send_bit(1);  // CRC
524 
          send_bit(0);  // CRC stuff
525 
          send_bit(0);  // CRC 6
526 
          send_bit(0);  // CRC
527 
          send_bit(0);  // CRC
528 
          send_bit(0);  // CRC
529 
          send_bit(1);  // CRC  stuff
530 
          send_bit(0);  // CRC 0
531 
          send_bit(0);  // CRC
532 
          send_bit(1);  // CRC
533 
          send_bit(0);  // CRC
534 
          send_bit(1);  // CRC 5
535 
          send_bit(1);  // CRC
536 
          send_bit(0);  // CRC
537 
          send_bit(1);  // CRC
538 
          send_bit(1);  // CRC b
539 
          send_bit(1);  // CRC DELIM
540 
          send_bit(0);  // ACK
541 
          send_bit(1);  // ACK DELIM
542 
          send_bit(1);  // EOF
543 
          send_bit(1);  // EOF
544 
          send_bit(1);  // EOF
545 
          send_bit(1);  // EOF
546 
          send_bit(1);  // EOF
547 
          send_bit(1);  // EOF
548 
          send_bit(1);  // EOF
549 
          send_bit(1);  // INTER
550 
          send_bit(1);  // INTER
551 
          send_bit(1);  // INTER
552 
        end // repeat
553 
 
554 
 
555 
 
556 
      end
557 
 
558 
 
559 
    join
560 
 
561 
 
562 
 
563 
    read_receive_buffer;
564 
    release_rx_buffer_command;
565 
 
566 
    read_receive_buffer;
567 
    release_rx_buffer_command;
568 
    read_receive_buffer;
569 
 
570 
    #4000000;
571 
 
572 
  end
573 
endtask   //  manual_frame_basic
574 
 
575 
 
576 
 
577 
task manual_frame_ext;    // Testbench sends an extended format frame
578 
  begin
579 
 
580 
 
581 
    // Switch-on reset mode
582 
    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
583 
 
584 
    // Set Clock Divider register
585 
    extended_mode = 1'b1;
586 
    write_register(8'd31, {extended_mode, 7'h0});    // Setting the extended mode
587 
 
588 
    // Set Acceptance Code and Acceptance Mask registers
589 
    write_register(8'd16, 8'ha6); // acceptance code 0
590 
    write_register(8'd17, 8'h00); // acceptance code 1
591 
    write_register(8'd18, 8'h5a); // acceptance code 2
592 
    write_register(8'd19, 8'hac); // acceptance code 3
593 
    write_register(8'd20, 8'h00); // acceptance mask 0
594 
    write_register(8'd21, 8'h00); // acceptance mask 1
595 
    write_register(8'd22, 8'h00); // acceptance mask 2
596 
    write_register(8'd23, 8'h00); // acceptance mask 3
597 
 
598 
    repeat (100) @ (posedge clk);
599 
 
600 
    // Switch-off reset mode
601 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
602 
 
603 
    // After exiting the reset mode sending bus free
604 
    repeat (11) send_bit(1);
605 
 
606 
 
607 
    // Extended frame format
608 
    // Writing TX frame information + identifier + data
609 
    write_register(8'd16, 8'hc5);   // Frame format = 1, Remote transmision request = 1, DLC = 5
610 
    write_register(8'd17, 8'ha6);   // ID[28:21] = a6
611 
    write_register(8'd18, 8'h00);   // ID[20:13] = 00
612 
    write_register(8'd19, 8'h5a);   // ID[12:5]  = 5a
613 
    write_register(8'd20, 8'ha8);   // ID[4:0]   = 15
614 
    // write_register(8'd21, 8'h78); RTR does not send any data
615 
    // write_register(8'd22, 8'h9a);
616 
    // write_register(8'd23, 8'hbc);
617 
    // write_register(8'd24, 8'hde);
618 
    // write_register(8'd25, 8'hf0);
619 
    // write_register(8'd26, 8'h0f);
620 
    // write_register(8'd27, 8'hed);
621 
    // write_register(8'd28, 8'hcb);
622 
 
623 
 
624 
    // Enabling IRQ's (extended mode)
625 
    write_register(8'd4, 8'hff);
626 
 
627 
    // tx_bypassed = 1;    // When this signal is on, tx is not looped back to the rx.
628 
 
629 
    fork
630 
      begin
631 
        tx_request_command;
632 
//        self_reception_request_command;
633 
      end
634 
 
635 
      begin
636 
        #2400;
637 
 
638 
        repeat (1)
639 
        begin
640 
          send_bit(0);  // SOF
641 
          send_bit(1);  // ID
642 
          send_bit(0);  // ID
643 
          send_bit(1);  // ID
644 
          send_bit(0);  // ID a
645 
          send_bit(0);  // ID
646 
          send_bit(1);  // ID
647 
          send_bit(1);  // ID
648 
          send_bit(0);  // ID 6
649 
          send_bit(0);  // ID
650 
          send_bit(0);  // ID
651 
          send_bit(0);  // ID
652 
          send_bit(1);  // RTR
653 
          send_bit(1);  // IDE
654 
          send_bit(0);  // ID 0
655 
          send_bit(0);  // ID
656 
          send_bit(0);  // ID
657 
          send_bit(0);  // ID
658 
          send_bit(0);  // ID 0
659 
          send_bit(1);  // ID stuff
660 
          send_bit(0);  // ID
661 
          send_bit(1);  // ID
662 
          send_bit(0);  // ID
663 
          send_bit(1);  // ID 6
664 
          send_bit(1);  // ID
665 
          send_bit(0);  // ID
666 
          send_bit(1);  // ID
667 
          send_bit(0);  // ID a
668 
          send_bit(1);  // ID 1
669 
          send_bit(0);  // ID
670 
          send_bit(1);  // ID
671 
          send_bit(0);  // ID
672 
          send_bit(1);  // ID 5
673 
          send_bit(1);  // RTR
674 
          send_bit(0);  // r1
675 
          send_bit(0);  // r0
676 
          send_bit(0);  // DLC
677 
          send_bit(1);  // DLC
678 
          send_bit(0);  // DLC
679 
          send_bit(1);  // DLC
680 
          send_bit(1);  // CRC
681 
          send_bit(0);  // CRC
682 
          send_bit(0);  // CRC 4
683 
          send_bit(1);  // CRC
684 
          send_bit(1);  // CRC
685 
          send_bit(0);  // CRC
686 
          send_bit(1);  // CRC d
687 
          send_bit(0);  // CRC
688 
          send_bit(0);  // CRC
689 
          send_bit(1);  // CRC
690 
          send_bit(1);  // CRC 3
691 
          send_bit(1);  // CRC
692 
          send_bit(0);  // CRC
693 
          send_bit(0);  // CRC
694 
          send_bit(1);  // CRC 9
695 
          send_bit(1);  // CRC DELIM
696 
          send_bit(0);  // ACK
697 
          send_bit(1);  // ACK DELIM
698 
          send_bit(1);  // EOF
699 
          send_bit(1);  // EOF
700 
          send_bit(1);  // EOF
701 
          send_bit(1);  // EOF
702 
          send_bit(1);  // EOF
703 
          send_bit(1);  // EOF
704 
          send_bit(1);  // EOF
705 
          send_bit(1);  // INTER
706 
          send_bit(1);  // INTER
707 
          send_bit(1);  // INTER
708 
        end // repeat
709 
 
710 
 
711 
      end
712 
 
713 
    join
714 
 
715 
 
716 
 
717 
    read_receive_buffer;
718 
    release_rx_buffer_command;
719 
 
720 
    read_receive_buffer;
721 
    release_rx_buffer_command;
722 
    read_receive_buffer;
723 
 
724 
    // Read irq register
725 
    #1 read_register(8'd3);
726 
 
727 
    // Read error code capture register
728 
    read_register(8'd12);
729 
 
730 
    // Read error capture code register
731 
//    read_register(8'd12);
732 
 
733 
    #4000000;
734 
 
735 
  end
736 
endtask   //  manual_frame_ext
737 
 
738 
 
739 
 
740 
task bus_off_test;    // Testbench sends a frame
741 
  begin
742 
 
743 
    write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8
744 
    write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7
745 
    write_register(8'd12, 8'h00); // data byte 1
746 
    write_register(8'd13, 8'h00); // data byte 2
747 
    write_register(8'd14, 8'h00); // data byte 3
748 
    write_register(8'd15, 8'h00); // data byte 4
749 
    write_register(8'd16, 8'h00); // data byte 5
750 
    write_register(8'd17, 8'h00); // data byte 6
751 
    write_register(8'd18, 8'h00); // data byte 7
752 
    write_register(8'd19, 8'h00); // data byte 8
753 
 
754 
    fork
755 
      begin
756 
        tx_request_command;
757 
      end
758 
 
759 
      begin
760 
        #2000;
761 
 
762 
        repeat (16)
763 
        begin
764 
          send_bit(0);  // SOF
765 
          send_bit(1);  // ID
766 
          send_bit(1);  // ID
767 
          send_bit(1);  // ID
768 
          send_bit(0);  // ID
769 
          send_bit(1);  // ID
770 
          send_bit(0);  // ID
771 
          send_bit(0);  // ID
772 
          send_bit(0);  // ID
773 
          send_bit(1);  // ID
774 
          send_bit(0);  // ID
775 
          send_bit(1);  // ID
776 
          send_bit(1);  // RTR
777 
          send_bit(0);  // IDE
778 
          send_bit(0);  // r0
779 
          send_bit(0);  // DLC
780 
          send_bit(1);  // DLC
781 
          send_bit(1);  // DLC
782 
          send_bit(1);  // DLC
783 
          send_bit(1);  // CRC
784 
          send_bit(0);  // CRC
785 
          send_bit(0);  // CRC
786 
          send_bit(1);  // CRC
787 
          send_bit(1);  // CRC
788 
          send_bit(1);  // CRC
789 
          send_bit(0);  // CRC
790 
          send_bit(1);  // CRC
791 
          send_bit(0);  // CRC
792 
          send_bit(0);  // CRC
793 
          send_bit(1);  // CRC
794 
          send_bit(1);  // CRC
795 
          send_bit(1);  // CRC
796 
          send_bit(1);  // CRC
797 
          send_bit(1);  // CRC
798 
          send_bit(1);  // CRC DELIM
799 
          send_bit(1);  // ACK            ack error
800 
          send_bit(0);  // ERROR
801 
          send_bit(0);  // ERROR
802 
          send_bit(0);  // ERROR
803 
          send_bit(0);  // ERROR
804 
          send_bit(0);  // ERROR
805 
          send_bit(0);  // ERROR
806 
          send_bit(1);  // ERROR DELIM
807 
          send_bit(1);  // ERROR DELIM
808 
          send_bit(1);  // ERROR DELIM
809 
          send_bit(1);  // ERROR DELIM
810 
          send_bit(1);  // ERROR DELIM
811 
          send_bit(1);  // ERROR DELIM
812 
          send_bit(1);  // ERROR DELIM
813 
          send_bit(1);  // ERROR DELIM
814 
          send_bit(1);  // INTER
815 
          send_bit(1);  // INTER
816 
          send_bit(1);  // INTER
817 
        end // repeat
818 
 
819 
        // Node is error passive now.
820 
 
821 
        // Read irq register (error interrupt should be cleared now.
822 
        read_register(8'd3);
823 
 
824 
        repeat (20)
825 
 
826 
        begin
827 
          send_bit(0);  // SOF
828 
          send_bit(1);  // ID
829 
          send_bit(1);  // ID
830 
          send_bit(1);  // ID
831 
          send_bit(0);  // ID
832 
          send_bit(1);  // ID
833 
          send_bit(0);  // ID
834 
          send_bit(0);  // ID
835 
          send_bit(0);  // ID
836 
          send_bit(1);  // ID
837 
          send_bit(0);  // ID
838 
          send_bit(1);  // ID
839 
          send_bit(1);  // RTR
840 
          send_bit(0);  // IDE
841 
          send_bit(0);  // r0
842 
          send_bit(0);  // DLC
843 
          send_bit(1);  // DLC
844 
          send_bit(1);  // DLC
845 
          send_bit(1);  // DLC
846 
          send_bit(1);  // CRC
847 
          send_bit(0);  // CRC
848 
          send_bit(0);  // CRC
849 
          send_bit(1);  // CRC
850 
          send_bit(1);  // CRC
851 
          send_bit(1);  // CRC
852 
          send_bit(0);  // CRC
853 
          send_bit(1);  // CRC
854 
          send_bit(0);  // CRC
855 
          send_bit(0);  // CRC
856 
          send_bit(1);  // CRC
857 
          send_bit(1);  // CRC
858 
          send_bit(1);  // CRC
859 
          send_bit(1);  // CRC
860 
          send_bit(1);  // CRC
861 
          send_bit(1);  // CRC DELIM
862 
          send_bit(1);  // ACK            ack error
863 
          send_bit(0);  // ERROR
864 
          send_bit(0);  // ERROR
865 
          send_bit(0);  // ERROR
866 
          send_bit(0);  // ERROR
867 
          send_bit(0);  // ERROR
868 
          send_bit(0);  // ERROR
869 
          send_bit(1);  // ERROR DELIM
870 
          send_bit(1);  // ERROR DELIM
871 
          send_bit(1);  // ERROR DELIM
872 
          send_bit(1);  // ERROR DELIM
873 
          send_bit(1);  // ERROR DELIM
874 
          send_bit(1);  // ERROR DELIM
875 
          send_bit(1);  // ERROR DELIM
876 
          send_bit(1);  // ERROR DELIM
877 
          send_bit(1);  // INTER
878 
          send_bit(1);  // INTER
879 
          send_bit(1);  // INTER
880 
          send_bit(1);  // SUSPEND
881 
          send_bit(1);  // SUSPEND
882 
          send_bit(1);  // SUSPEND
883 
          send_bit(1);  // SUSPEND
884 
          send_bit(1);  // SUSPEND
885 
          send_bit(1);  // SUSPEND
886 
          send_bit(1);  // SUSPEND
887 
          send_bit(1);  // SUSPEND
888 
        end // repeat
889 
 
890 
        // Node is bus-off now
891 
 
892 
 
893 
        // Read irq register (error interrupt should be cleared now.
894 
        read_register(8'd3);
895 
 
896 
 
897 
 
898 
        #100000;
899 
 
900 
        // Switch-off reset mode
901 
        write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
902 
 
903 
        repeat (64 * 11)
904 
        begin
905 
          send_bit(1);
906 
        end // repeat
907 
 
908 
        // Read irq register (error interrupt should be cleared now.
909 
        read_register(8'd3);
910 
 
911 
        repeat (64 * 11)
912 
        begin
913 
          send_bit(1);
914 
        end // repeat
915 
 
916 
 
917 
 
918 
        // Read irq register (error interrupt should be cleared now.
919 
        read_register(8'd3);
920 
 
921 
      end
922 
 
923 
 
924 
 
925 
    join
926 
 
927 
 
928 
 
929 
    fork
930 
      begin
931 
        tx_request_command;
932 
      end
933 
 
934 
      begin
935 
        #1100;
936 
 
937 
        send_bit(1);    // To spend some time before transmitter is ready.
938 
 
939 
        repeat (1)
940 
        begin
941 
          send_bit(0);  // SOF
942 
          send_bit(1);  // ID
943 
          send_bit(1);  // ID
944 
          send_bit(1);  // ID
945 
          send_bit(0);  // ID
946 
          send_bit(1);  // ID
947 
          send_bit(0);  // ID
948 
          send_bit(0);  // ID
949 
          send_bit(0);  // ID
950 
          send_bit(1);  // ID
951 
          send_bit(0);  // ID
952 
          send_bit(1);  // ID
953 
          send_bit(1);  // RTR
954 
          send_bit(0);  // IDE
955 
          send_bit(0);  // r0
956 
          send_bit(0);  // DLC
957 
          send_bit(1);  // DLC
958 
          send_bit(1);  // DLC
959 
          send_bit(1);  // DLC
960 
          send_bit(1);  // CRC
961 
          send_bit(0);  // CRC
962 
          send_bit(0);  // CRC
963 
          send_bit(1);  // CRC
964 
          send_bit(1);  // CRC
965 
          send_bit(1);  // CRC
966 
          send_bit(0);  // CRC
967 
          send_bit(1);  // CRC
968 
          send_bit(0);  // CRC
969 
          send_bit(0);  // CRC
970 
          send_bit(1);  // CRC
971 
          send_bit(1);  // CRC
972 
          send_bit(1);  // CRC
973 
          send_bit(1);  // CRC
974 
          send_bit(1);  // CRC
975 
          send_bit(1);  // CRC DELIM
976 
          send_bit(0);  // ACK
977 
          send_bit(1);  // ACK DELIM
978 
          send_bit(1);  // EOF
979 
          send_bit(1);  // EOF
980 
          send_bit(1);  // EOF
981 
          send_bit(1);  // EOF
982 
          send_bit(1);  // EOF
983 
          send_bit(1);  // EOF
984 
          send_bit(1);  // EOF
985 
          send_bit(1);  // INTER
986 
          send_bit(1);  // INTER
987 
          send_bit(1);  // INTER
988 
        end // repeat
989 
      end
990 
 
991 
    join
992 
 
993 
    read_receive_buffer;
994 
    release_rx_buffer_command;
995 
    read_receive_buffer;
996 
    release_rx_buffer_command;
997 
    read_receive_buffer;
998 
 
999 
    #4000000;
1000 
 
1001 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
1002 
 
1003 
    #1000000;
1004 
 
1005 
  end
1006 
endtask   // bus_off_test
1007 
 
1008 
 
1009 
 
1010 
task send_frame_basic;    // CAN IP core sends frames
1011 
  begin
1012 
 
1013 
    write_register(8'd10, 8'hea); // Writing ID[10:3] = 0xea
1014 
    write_register(8'd11, 8'h28); // Writing ID[2:0] = 0x1, rtr = 0, length = 8
1015 
    write_register(8'd12, 8'h56); // data byte 1
1016 
    write_register(8'd13, 8'h78); // data byte 2
1017 
    write_register(8'd14, 8'h9a); // data byte 3
1018 
    write_register(8'd15, 8'hbc); // data byte 4
1019 
    write_register(8'd16, 8'hde); // data byte 5
1020 
    write_register(8'd17, 8'hf0); // data byte 6
1021 
    write_register(8'd18, 8'h0f); // data byte 7
1022 
    write_register(8'd19, 8'hed); // data byte 8
1023 
 
1024 
 
1025 
    // Enable irqs (basic mode)
1026 
    write_register(8'd0, 8'h1e);
1027 
 
1028 
 
1029 
 
1030 
    fork
1031 
 
1032 
      begin
1033 127 mohor 
        #1100;
1034 83 mohor 
        $display("\n\nStart receiving data from CAN bus");
1035 
        receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
1036 
        receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
1037 
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc
1038 127 mohor 
        receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
1039 83 mohor 
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc
1040 
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc
1041 
      end
1042 
 
1043 
      begin
1044 
        tx_request_command;
1045 
      end
1046 
 
1047 
      begin
1048 127 mohor 
        wait (can_testbench.i_can_top.i_can_bsp.go_tx)        // waiting for tx to start
1049 
        wait (~can_testbench.i_can_top.i_can_bsp.need_to_tx)  // waiting for tx to finish
1050 
        tx_request_command;                                   // start another tx
1051 
      end
1052 
 
1053 
      begin
1054 
        // Transmitting acknowledge (for first packet)
1055 
        wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack & can_testbench.i_can_top.i_can_bsp.tx_point);
1056 83 mohor 
        #1 rx = 0;
1057 127 mohor 
        wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim & can_testbench.i_can_top.i_can_bsp.tx_point);
1058 83 mohor 
        #1 rx = 1;
1059 127 mohor 
 
1060 
        // Transmitting acknowledge (for second packet)
1061 
        wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack & can_testbench.i_can_top.i_can_bsp.tx_point);
1062 
        #1 rx = 0;
1063 
        wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim & can_testbench.i_can_top.i_can_bsp.tx_point);
1064 
        #1 rx = 1;
1065 83 mohor 
      end
1066 
 
1067 
 
1068 
    join
1069 
 
1070 
    read_receive_buffer;
1071 
    release_rx_buffer_command;
1072 
    release_rx_buffer_command;
1073 
    read_receive_buffer;
1074 
    release_rx_buffer_command;
1075 
    read_receive_buffer;
1076 
 
1077 
    #200000;
1078 
 
1079 
    read_receive_buffer;
1080 
 
1081 
    // Read irq register
1082 
    read_register(8'd3);
1083 
    #1000;
1084 
 
1085 
  end
1086 
endtask   // send_frame_basic
1087 
 
1088 
 
1089 
 
1090 
task send_frame_extended;    // CAN IP core sends basic or extended frames in extended mode
1091 
  begin
1092 
 
1093 
    // Switch-on reset mode
1094 
    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
1095 
 
1096 
    // Set Clock Divider register
1097 
    extended_mode = 1'b1;
1098 
    write_register(8'd31, {extended_mode, 7'h0});    // Setting the extended mode
1099 
 
1100 
    // Set Acceptance Code and Acceptance Mask registers
1101 
    write_register(8'd16, 8'ha6); // acceptance code 0
1102 
    write_register(8'd17, 8'hb0); // acceptance code 1
1103 
    write_register(8'd18, 8'h12); // acceptance code 2
1104 
    write_register(8'd19, 8'h30); // acceptance code 3
1105 
    write_register(8'd20, 8'h00); // acceptance mask 0
1106 
    write_register(8'd21, 8'h00); // acceptance mask 1
1107 
    write_register(8'd22, 8'h00); // acceptance mask 2
1108 
    write_register(8'd23, 8'h00); // acceptance mask 3
1109 
 
1110 
    // Switch-off reset mode
1111 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
1112 
 
1113 
    // After exiting the reset mode sending bus free
1114 
    repeat (11) send_bit(1);
1115 
 
1116 
 
1117 
/*  Basic frame format
1118 
    // Writing TX frame information + identifier + data
1119 
    write_register(8'd16, 8'h45);   // Frame format = 0, Remote transmision request = 1, DLC = 5
1120 
    write_register(8'd17, 8'ha6);   // ID[28:21] = a6
1121 
    write_register(8'd18, 8'ha0);   // ID[20:18] = 5
1122 
    // write_register(8'd19, 8'h78); RTR does not send any data
1123 
    // write_register(8'd20, 8'h9a);
1124 
    // write_register(8'd21, 8'hbc);
1125 
    // write_register(8'd22, 8'hde);
1126 
    // write_register(8'd23, 8'hf0);
1127 
    // write_register(8'd24, 8'h0f);
1128 
    // write_register(8'd25, 8'hed);
1129 
    // write_register(8'd26, 8'hcb);
1130 
    // write_register(8'd27, 8'ha9);
1131 
    // write_register(8'd28, 8'h87);
1132 
*/
1133 
 
1134 
    // Extended frame format
1135 
    // Writing TX frame information + identifier + data
1136 
    write_register(8'd16, 8'hc5);   // Frame format = 1, Remote transmision request = 1, DLC = 5
1137 
    write_register(8'd17, 8'ha6);   // ID[28:21] = a6
1138 
    write_register(8'd18, 8'h00);   // ID[20:13] = 00
1139 
    write_register(8'd19, 8'h5a);   // ID[12:5]  = 5a
1140 
    write_register(8'd20, 8'ha8);   // ID[4:0]   = 15
1141 
    // write_register(8'd21, 8'h78); RTR does not send any data
1142 
    // write_register(8'd22, 8'h9a);
1143 
    // write_register(8'd23, 8'hbc);
1144 
    // write_register(8'd24, 8'hde);
1145 
    // write_register(8'd25, 8'hf0);
1146 
    // write_register(8'd26, 8'h0f);
1147 
    // write_register(8'd27, 8'hed);
1148 
    // write_register(8'd28, 8'hcb);
1149 
 
1150 
 
1151 
    // Enabling IRQ's (extended mode)
1152 
    write_register(8'd4, 8'hff);
1153 
 
1154 
 
1155 
    fork
1156 
      begin
1157 
        #2700;
1158 
        $display("\n\nStart receiving data from CAN bus");
1159 
        /* Standard frame format
1160 
        receive_frame(0, 0, {26'h00000a0, 3'h1}, 4'h1, 15'h2d9c); // mode, rtr, id, length, crc
1161 
        receive_frame(0, 0, {26'h00000a0, 3'h1}, 4'h2, 15'h46b4); // mode, rtr, id, length, crc
1162 
        receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h0, 15'h42cd); // mode, rtr, id, length, crc
1163 
        receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h1, 15'h555f); // mode, rtr, id, length, crc
1164 
        receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h2, 15'h6742); // mode, rtr, id, length, crc
1165 
        */
1166 
 
1167 
        // Extended frame format
1168 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h1, 15'h2d22); // mode, rtr, id, length, crc
1169 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h2, 15'h3d2d); // mode, rtr, id, length, crc
1170 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h0, 15'h23aa); // mode, rtr, id, length, crc
1171 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h1, 15'h2d22); // mode, rtr, id, length, crc
1172 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h2, 15'h3d2d); // mode, rtr, id, length, crc
1173 
 
1174 
      end
1175 
 
1176 
      begin
1177 
        tx_request_command;
1178 
      end
1179 
 
1180 
      begin
1181 
        // Transmitting acknowledge
1182 127 mohor 
        wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack & can_testbench.i_can_top.i_can_bsp.tx_point);
1183 83 mohor 
        #1 rx = 0;
1184 127 mohor 
        wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim & can_testbench.i_can_top.i_can_bsp.tx_point);
1185 83 mohor 
        #1 rx = 1;
1186 
      end
1187 
 
1188 
      begin   // Reading irq and arbitration lost capture register
1189 
 
1190 
        repeat(1)
1191 
          begin
1192 
            while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
1193 
              begin
1194 
                @ (posedge clk);
1195 
              end
1196 
 
1197 
            // Read irq register
1198 
            #1 read_register(8'd3);
1199 
 
1200 
            // Read arbitration lost capture register
1201 
            read_register(8'd11);
1202 
          end
1203 
 
1204 
 
1205 
        repeat(1)
1206 
          begin
1207 
            while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
1208 
              begin
1209 
                @ (posedge clk);
1210 
              end
1211 
 
1212 
            // Read irq register
1213 
            #1 read_register(8'd3);
1214 
          end
1215 
 
1216 
        repeat(1)
1217 
          begin
1218 
            while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
1219 
              begin
1220 
                @ (posedge clk);
1221 
              end
1222 
 
1223 
            // Read arbitration lost capture register
1224 
            read_register(8'd11);
1225 
          end
1226 
 
1227 
      end
1228 
 
1229 
    join
1230 
 
1231 
    read_receive_buffer;
1232 
    release_rx_buffer_command;
1233 
    release_rx_buffer_command;
1234 
    read_receive_buffer;
1235 
    release_rx_buffer_command;
1236 
    read_receive_buffer;
1237 
    release_rx_buffer_command;
1238 
    read_receive_buffer;
1239 
    release_rx_buffer_command;
1240 
    read_receive_buffer;
1241 
 
1242 
    #200000;
1243 
 
1244 
    read_receive_buffer;
1245 
 
1246 
    // Read irq register
1247 
    read_register(8'd3);
1248 
    #1000;
1249 
 
1250 
  end
1251 
endtask   // send_frame_extended
1252 
 
1253 
 
1254 
 
1255 
task self_reception_request;    // CAN IP core sends sets self reception mode and transmits a msg. This test runs in EXTENDED mode
1256 
  begin
1257 
 
1258 
    // Switch-on reset mode
1259 
    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
1260 
 
1261 
    // Set Clock Divider register
1262 
    extended_mode = 1'b1;
1263 
    write_register(8'd31, {extended_mode, 7'h0});    // Setting the extended mode
1264 
 
1265 
    // Set Acceptance Code and Acceptance Mask registers
1266 
    write_register(8'd16, 8'ha6); // acceptance code 0
1267 
    write_register(8'd17, 8'hb0); // acceptance code 1
1268 
    write_register(8'd18, 8'h12); // acceptance code 2
1269 
    write_register(8'd19, 8'h30); // acceptance code 3
1270 
    write_register(8'd20, 8'h00); // acceptance mask 0
1271 
    write_register(8'd21, 8'h00); // acceptance mask 1
1272 
    write_register(8'd22, 8'h00); // acceptance mask 2
1273 
    write_register(8'd23, 8'h00); // acceptance mask 3
1274 
 
1275 
    // Setting the "self test mode"
1276 
    write_register(8'd0, 8'h4);
1277 
 
1278 
    // Switch-off reset mode
1279 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
1280 
 
1281 
    // After exiting the reset mode sending bus free
1282 
    repeat (11) send_bit(1);
1283 
 
1284 
 
1285 
    // Writing TX frame information + identifier + data
1286 
    write_register(8'd16, 8'h45);   // Frame format = 0, Remote transmision request = 1, DLC = 5
1287 
    write_register(8'd17, 8'ha6);   // ID[28:21] = a6
1288 
    write_register(8'd18, 8'ha0);   // ID[20:18] = 5
1289 
    // write_register(8'd19, 8'h78); RTR does not send any data
1290 
    // write_register(8'd20, 8'h9a);
1291 
    // write_register(8'd21, 8'hbc);
1292 
    // write_register(8'd22, 8'hde);
1293 
    // write_register(8'd23, 8'hf0);
1294 
    // write_register(8'd24, 8'h0f);
1295 
    // write_register(8'd25, 8'hed);
1296 
    // write_register(8'd26, 8'hcb);
1297 
    // write_register(8'd27, 8'ha9);
1298 
    // write_register(8'd28, 8'h87);
1299 
 
1300 
 
1301 
    // Enabling IRQ's (extended mode)
1302 
    write_register(8'd4, 8'hff);
1303 
 
1304 
    self_reception_request_command;
1305 
 
1306 
    #400000;
1307 
 
1308 
    read_receive_buffer;
1309 
    release_rx_buffer_command;
1310 
    release_rx_buffer_command;
1311 
    read_receive_buffer;
1312 
    release_rx_buffer_command;
1313 
    read_receive_buffer;
1314 
    release_rx_buffer_command;
1315 
    read_receive_buffer;
1316 
    release_rx_buffer_command;
1317 
    read_receive_buffer;
1318 
 
1319 
 
1320 
    read_receive_buffer;
1321 
 
1322 
    // Read irq register
1323 
    read_register(8'd3);
1324 
    #1000;
1325 
 
1326 
  end
1327 
endtask   // self_reception_request
1328 
 
1329 
 
1330 
 
1331 
task test_empty_fifo;
1332 
  begin
1333 
 
1334 
    // Enable irqs (basic mode)
1335 
    write_register(8'd0, 8'h1e);
1336 
 
1337 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h3, 15'h56a9); // mode, rtr, id, length, crc
1338 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h7, 15'h391d); // mode, rtr, id, length, crc
1339 
 
1340 
    read_receive_buffer;
1341 
    fifo_info;
1342 
 
1343 
    release_rx_buffer_command;
1344 
    $display("\n\n");
1345 
    read_receive_buffer;
1346 
    fifo_info;
1347 
 
1348 
    release_rx_buffer_command;
1349 
    $display("\n\n");
1350 
    read_receive_buffer;
1351 
    fifo_info;
1352 
 
1353 
    release_rx_buffer_command;
1354 
    $display("\n\n");
1355 
    read_receive_buffer;
1356 
    fifo_info;
1357 
 
1358 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1359 
 
1360 
    $display("\n\n");
1361 
    read_receive_buffer;
1362 
    fifo_info;
1363 
 
1364 
    release_rx_buffer_command;
1365 
    $display("\n\n");
1366 
    read_receive_buffer;
1367 
    fifo_info;
1368 
 
1369 
    release_rx_buffer_command;
1370 
    $display("\n\n");
1371 
    read_receive_buffer;
1372 
    fifo_info;
1373 
  end
1374 
endtask
1375 
 
1376 
 
1377 
 
1378 
task test_empty_fifo_ext;
1379 
  begin
1380 
    receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
1381 
    receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
1382 
 
1383 
    read_receive_buffer;
1384 
    fifo_info;
1385 
 
1386 
    release_rx_buffer_command;
1387 
    $display("\n\n");
1388 
    read_receive_buffer;
1389 
    fifo_info;
1390 
 
1391 
    release_rx_buffer_command;
1392 
    $display("\n\n");
1393 
    read_receive_buffer;
1394 
    fifo_info;
1395 
 
1396 
    release_rx_buffer_command;
1397 
    $display("\n\n");
1398 
    read_receive_buffer;
1399 
    fifo_info;
1400 
 
1401 
    receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
1402 
 
1403 
    $display("\n\n");
1404 
    read_receive_buffer;
1405 
    fifo_info;
1406 
 
1407 
    release_rx_buffer_command;
1408 
    $display("\n\n");
1409 
    read_receive_buffer;
1410 
    fifo_info;
1411 
 
1412 
    release_rx_buffer_command;
1413 
    $display("\n\n");
1414 
    read_receive_buffer;
1415 
    fifo_info;
1416 
  end
1417 
endtask
1418 
 
1419 
 
1420 
 
1421 
task test_full_fifo;
1422 
  begin
1423 
 
1424 
    // Enable irqs (basic mode)
1425 
    write_register(8'd0, 8'h1e);
1426 
 
1427 
    $display("\n\n");
1428 
 
1429 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
1430 
    fifo_info;
1431 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
1432 
    fifo_info;
1433 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
1434 
    fifo_info;
1435 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h3, 15'h56a9); // mode, rtr, id, length, crc
1436 
    fifo_info;
1437 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h4, 15'h3124); // mode, rtr, id, length, crc
1438 
    fifo_info;
1439 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h5, 15'h6944); // mode, rtr, id, length, crc
1440 
    fifo_info;
1441 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h6, 15'h5182); // mode, rtr, id, length, crc
1442 
    fifo_info;
1443 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h7, 15'h391d); // mode, rtr, id, length, crc
1444 
    fifo_info;
1445 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1446 
    fifo_info;
1447 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1448 
    fifo_info;
1449 
    $display("FIFO should be full now");
1450 
 
1451 
    // Following one is accepted with overrun
1452 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1453 
    fifo_info;
1454 
 
1455 
    release_rx_buffer_command;
1456 
    fifo_info;
1457 
 
1458 
    // Space just enough for the following frame.
1459 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
1460 
    fifo_info;
1461 
 
1462 
    // Following accepted with overrun
1463 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1464 
    fifo_info;
1465 
//    read_overrun_info(0, 15);
1466 
 
1467 
    release_rx_buffer_command;
1468 
    release_rx_buffer_command;
1469 
 
1470 
    release_rx_buffer_command;
1471 
    read_receive_buffer;
1472 
    fifo_info;
1473 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1474 
    fifo_info;
1475 
//    read_overrun_info(0, 15);
1476 
    $display("\n\n");
1477 
 
1478 
    release_rx_buffer_command;
1479 
    read_receive_buffer;
1480 
    fifo_info;
1481 
 
1482 
    release_rx_buffer_command;
1483 
    read_receive_buffer;
1484 
    fifo_info;
1485 
 
1486 
    release_rx_buffer_command;
1487 
    read_receive_buffer;
1488 
    fifo_info;
1489 
 
1490 
    release_rx_buffer_command;
1491 
    read_receive_buffer;
1492 
    fifo_info;
1493 
 
1494 
    release_rx_buffer_command;
1495 
    read_receive_buffer;
1496 
    fifo_info;
1497 
 
1498 
    release_rx_buffer_command;
1499 
    read_receive_buffer;
1500 
    fifo_info;
1501 
 
1502 
    clear_data_overrun_command;
1503 
 
1504 
    release_rx_buffer_command;
1505 
    read_receive_buffer;
1506 
    fifo_info;
1507 
 
1508 
    release_rx_buffer_command;
1509 
    read_receive_buffer;
1510 
    fifo_info;
1511 
 
1512 
    clear_data_overrun_command;
1513 
 
1514 
    release_rx_buffer_command;
1515 
    read_receive_buffer;
1516 
    fifo_info;
1517 
 
1518 
    release_rx_buffer_command;
1519 
    read_receive_buffer;
1520 
    fifo_info;
1521 
 
1522 
    release_rx_buffer_command;
1523 
    read_receive_buffer;
1524 
    fifo_info;
1525 
 
1526 
    release_rx_buffer_command;
1527 
    read_receive_buffer;
1528 
    fifo_info;
1529 
 
1530 
    release_rx_buffer_command;
1531 
    read_receive_buffer;
1532 
    fifo_info;
1533 
 
1534 
    // Read irq register
1535 
    read_register(8'd3);
1536 
 
1537 
    // Read irq register
1538 
    read_register(8'd3);
1539 
    #1000;
1540 
 
1541 
  end
1542 
endtask
1543 
 
1544 
 
1545 
 
1546 
task test_full_fifo_ext;
1547 
  begin
1548 
    release_rx_buffer_command;
1549 
    $display("\n\n");
1550 
    read_receive_buffer;
1551 
    fifo_info;
1552 
 
1553 
    receive_frame(1, 0, 29'h14d60246, 4'h0, 15'h6f54); // mode, rtr, id, length, crc
1554 
    read_receive_buffer;
1555 
    fifo_info;
1556 
    receive_frame(1, 0, 29'h14d60246, 4'h1, 15'h6d38); // mode, rtr, id, length, crc
1557 
    read_receive_buffer;
1558 
    fifo_info;
1559 
    receive_frame(1, 0, 29'h14d60246, 4'h2, 15'h053e); // mode, rtr, id, length, crc
1560 
    fifo_info;
1561 
    read_receive_buffer;
1562 
    receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
1563 
    fifo_info;
1564 
    receive_frame(1, 0, 29'h14d60246, 4'h4, 15'h4bba); // mode, rtr, id, length, crc
1565 
    fifo_info;
1566 
    receive_frame(1, 0, 29'h14d60246, 4'h5, 15'h4d7d); // mode, rtr, id, length, crc
1567 
    fifo_info;
1568 
    receive_frame(1, 0, 29'h14d60246, 4'h6, 15'h6f40); // mode, rtr, id, length, crc
1569 
    fifo_info;
1570 
    receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
1571 
    fifo_info;
1572 
//    read_overrun_info(0, 10);
1573 
 
1574 
    release_rx_buffer_command;
1575 
    release_rx_buffer_command;
1576 
    fifo_info;
1577 
    receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
1578 
    fifo_info;
1579 
//    read_overrun_info(0, 15);
1580 
    $display("\n\n");
1581 
 
1582 
    release_rx_buffer_command;
1583 
    read_receive_buffer;
1584 
    fifo_info;
1585 
 
1586 
    release_rx_buffer_command;
1587 
    read_receive_buffer;
1588 
    fifo_info;
1589 
 
1590 
    release_rx_buffer_command;
1591 
    read_receive_buffer;
1592 
    fifo_info;
1593 
 
1594 
    release_rx_buffer_command;
1595 
    read_receive_buffer;
1596 
    fifo_info;
1597 
 
1598 
    release_rx_buffer_command;
1599 
    read_receive_buffer;
1600 
    fifo_info;
1601 
 
1602 
    release_rx_buffer_command;
1603 
    read_receive_buffer;
1604 
    fifo_info;
1605 
 
1606 
    release_rx_buffer_command;
1607 
    read_receive_buffer;
1608 
    fifo_info;
1609 
 
1610 
  end
1611 
endtask
1612 
 
1613 
 
1614 
/*
1615 
task initialize_fifo;
1616 
  integer i;
1617 
  begin
1618 
    for (i=0; i<32; i=i+1)
1619 
      begin
1620 
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i] = 0;
1621 
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i] = 0;
1622 
      end
1623 
 
1624 
    for (i=0; i<64; i=i+1)
1625 
      begin
1626 
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo[i] = 0;
1627 
      end
1628 
 
1629 
    $display("(%0t) Fifo initialized", $time);
1630 
  end
1631 
endtask
1632 
*/
1633 
/*
1634 
task read_overrun_info;
1635 
  input [4:0] start_addr;
1636 
  input [4:0] end_addr;
1637 
  integer i;
1638 
  begin
1639 
    for (i=start_addr; i<=end_addr; i=i+1)
1640 
      begin
1641 
        $display("len[0x%0x]=0x%0x", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i]);
1642 
        $display("overrun[0x%0x]=0x%0x\n", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i]);
1643 
      end
1644 
  end
1645 
endtask
1646 
*/
1647 
 
1648 
task fifo_info;   // Displaying how many packets and how many bytes are in fifo. Not working when wr_info_pointer is smaller than rd_info_pointer.
1649 
  begin
1650 
      $display("(%0t) Currently %0d bytes in fifo (%0d packets)", $time, can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_cnt,
1651 
      (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_info_pointer - can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer));
1652 
end
1653 
endtask
1654 
 
1655 
 
1656 
task read_register;
1657 
  input [7:0] reg_addr;
1658 
 
1659 
  `ifdef CAN_WISHBONE_IF
1660 
    begin
1661 
      wait (wb_free);
1662 
      wb_free = 0;
1663 
      @ (posedge wb_clk_i);
1664 
      #1;
1665 
      cs_can = 1;
1666 
      wb_adr_i = reg_addr;
1667 
      wb_cyc_i = 1;
1668 
      wb_stb_i = 1;
1669 
      wb_we_i = 0;
1670 
      wait (wb_ack_o);
1671 
      $display("(%0t) Reading register [%0d] = 0x%0x", $time, wb_adr_i, wb_dat_o);
1672 
      @ (posedge wb_clk_i);
1673 
      #1;
1674 
      wb_adr_i = 'hz;
1675 
      wb_cyc_i = 0;
1676 
      wb_stb_i = 0;
1677 
      wb_we_i = 'hz;
1678 
      cs_can = 0;
1679 
      wb_free = 1;
1680 
    end
1681 
  `else
1682 
    begin
1683 
      wait (port_free);
1684 
      port_free = 0;
1685 
      @ (posedge clk);
1686 
      #1;
1687 
      cs_can = 1;
1688 
      @ (negedge clk);
1689 
      #1;
1690 
      ale_i = 1;
1691 
      port_0_en = 1;
1692 
      port_0_o = reg_addr;
1693 
      @ (negedge clk);
1694 
      #1;
1695 
      ale_i = 0;
1696 
      #90;            // 73 - 103 ns
1697 
      port_0_en = 0;
1698 
      rd_i = 1;
1699 
      #158;
1700 
      $display("(%0t) Reading register [%0d] = 0x%0x", $time, can_testbench.i_can_top.addr_latched, port_0_i);
1701 
      #1;
1702 
      rd_i = 0;
1703 
      cs_can = 0;
1704 
      port_free = 1;
1705 
    end
1706 
  `endif
1707 
endtask
1708 
 
1709 
 
1710 
task write_register;
1711 
  input [7:0] reg_addr;
1712 
  input [7:0] reg_data;
1713 
 
1714 
  `ifdef CAN_WISHBONE_IF
1715 
    begin
1716 
      wait (wb_free);
1717 
      wb_free = 0;
1718 
      @ (posedge wb_clk_i);
1719 
      #1;
1720 
      cs_can = 1;
1721 
      wb_adr_i = reg_addr;
1722 
      wb_dat_i = reg_data;
1723 
      wb_cyc_i = 1;
1724 
      wb_stb_i = 1;
1725 
      wb_we_i = 1;
1726 
      wait (wb_ack_o);
1727 
      @ (posedge wb_clk_i);
1728 
      #1;
1729 
      wb_adr_i = 'hz;
1730 
      wb_dat_i = 'hz;
1731 
      wb_cyc_i = 0;
1732 
      wb_stb_i = 0;
1733 
      wb_we_i = 'hz;
1734 
      cs_can = 0;
1735 
      wb_free = 1;
1736 
    end
1737 
  `else
1738 
    begin
1739 
      wait (port_free);
1740 
      port_free = 0;
1741 
      @ (posedge clk);
1742 
      #1;
1743 
      cs_can = 1;
1744 
      @ (negedge clk);
1745 
      #1;
1746 
      ale_i = 1;
1747 
      port_0_en = 1;
1748 
      port_0_o = reg_addr;
1749 
      @ (negedge clk);
1750 
      #1;
1751 
      ale_i = 0;
1752 
      #90;            // 73 - 103 ns
1753 
      port_0_o = reg_data;
1754 
      wr_i = 1;
1755 
      #158;
1756 
      wr_i = 0;
1757 
      port_0_en = 0;
1758 
      cs_can = 0;
1759 
      port_free = 1;
1760 
    end
1761 
  `endif
1762 
endtask
1763 
 
1764 
 
1765 
task read_receive_buffer;
1766 
  integer i;
1767 
  begin
1768 
    $display("\n\n(%0t)", $time);
1769 
    if(extended_mode)   // Extended mode
1770 
      begin
1771 
        for (i=8'd16; i<=8'd28; i=i+1)
1772 
          read_register(i);
1773 
        if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun)
1774 
          $display("\nWARNING: Above packet was received with overrun.");
1775 
      end
1776 
    else
1777 
      begin
1778 
        for (i=8'd20; i<=8'd29; i=i+1)
1779 
          read_register(i);
1780 
        if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun)
1781 
          $display("\nWARNING: Above packet was received with overrun.");
1782 
      end
1783 
  end
1784 
endtask
1785 
 
1786 
 
1787 
task release_rx_buffer_command;
1788 
  begin
1789 
    write_register(8'd1, 8'h4);
1790 
    $display("(%0t) Rx buffer released.", $time);
1791 
  end
1792 
endtask
1793 
 
1794 
 
1795 
task tx_request_command;
1796 
  begin
1797 
    write_register(8'd1, 8'h1);
1798 
    $display("(%0t) Tx requested.", $time);
1799 
  end
1800 
endtask
1801 
 
1802 
 
1803 
task tx_abort_command;
1804 
  begin
1805 
    write_register(8'd1, 8'h2);
1806 
    $display("(%0t) Tx abort requested.", $time);
1807 
  end
1808 
endtask
1809 
 
1810 
 
1811 
task clear_data_overrun_command;
1812 
  begin
1813 
    write_register(8'd1, 8'h8);
1814 
    $display("(%0t) Data overrun cleared.", $time);
1815 
  end
1816 
endtask
1817 
 
1818 
 
1819 
task self_reception_request_command;
1820 
  begin
1821 
    write_register(8'd1, 8'h10);
1822 
    $display("(%0t) Self reception requested.", $time);
1823 
  end
1824 
endtask
1825 
 
1826 
 
1827 
task test_synchronization;
1828 
  begin
1829 
    // Hard synchronization
1830 
    #1 rx=0;
1831 
    repeat (2*BRP) @ (posedge clk);
1832 
    repeat (8*BRP) @ (posedge clk);
1833 
    #1 rx=1;
1834 
    repeat (10*BRP) @ (posedge clk);
1835 
 
1836 
    // Resynchronization on time
1837 
    #1 rx=0;
1838 
    repeat (10*BRP) @ (posedge clk);
1839 
    #1 rx=1;
1840 
    repeat (10*BRP) @ (posedge clk);
1841 
 
1842 
    // Resynchronization late
1843 
    repeat (BRP) @ (posedge clk);
1844 
    repeat (BRP) @ (posedge clk);
1845 
    #1 rx=0;
1846 
    repeat (10*BRP) @ (posedge clk);
1847 
    #1 rx=1;
1848 
 
1849 
    // Resynchronization early
1850 
    repeat (8*BRP) @ (posedge clk);   // two frames too early
1851 
    #1 rx=0;
1852 
    repeat (10*BRP) @ (posedge clk);
1853 
    #1 rx=1;
1854 127 mohor 
    // Resynchronization early
1855 
    repeat (11*BRP) @ (posedge clk);   // one frames too late
1856 
    #1 rx=0;
1857 83 mohor 
    repeat (10*BRP) @ (posedge clk);
1858 127 mohor 
    #1 rx=1;
1859 
 
1860 
    repeat (10*BRP) @ (posedge clk);
1861 
    #1 rx=0;
1862 
    repeat (10*BRP) @ (posedge clk);
1863 83 mohor 
  end
1864 
endtask
1865 
 
1866 
 
1867 
task send_bit;
1868 
  input bit;
1869 
  integer cnt;
1870 
  begin
1871 
    #1 rx=bit;
1872 
    repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
1873 
  end
1874 
endtask
1875 
 
1876 
 
1877 
task receive_frame;           // CAN IP core receives frames
1878 
  input mode;
1879 
  input remote_trans_req;
1880 
  input [28:0] id;
1881 
  input  [3:0] length;
1882 
  input [14:0] crc;
1883 
 
1884 
  reg [117:0] data;
1885 
  reg         previous_bit;
1886 
  reg         stuff;
1887 
  reg         tmp;
1888 
  reg         arbitration_lost;
1889 
  integer     pointer;
1890 
  integer     cnt;
1891 
  integer     total_bits;
1892 
  integer     stuff_cnt;
1893 
 
1894 
  begin
1895 
 
1896 
    stuff_cnt = 1;
1897 
    stuff = 0;
1898 
 
1899 
    if(mode)          // Extended format
1900 
      data = {id[28:18], 1'b1, 1'b1, id[17:0], remote_trans_req, 2'h0, length};
1901 
    else              // Standard format
1902 
      data = {id[10:0], remote_trans_req, 1'b0, 1'b0, length};
1903 
 
1904 
    if (~remote_trans_req)
1905 
      begin
1906 
        if(length)    // Send data if length is > 0
1907 
          begin
1908 
            for (cnt=1; cnt<=(2*length); cnt=cnt+1)  // data   (we are sending nibbles)
1909 
              data = {data[113:0], cnt[3:0]};
1910 
          end
1911 
      end
1912 
 
1913 
    // Adding CRC
1914 
    data = {data[104:0], crc[14:0]};
1915 
 
1916 
 
1917 
    // Calculating pointer that points to the bit that will be send
1918 
    if (remote_trans_req)
1919 
      begin
1920 
        if(mode)          // Extended format
1921 
          pointer = 52;
1922 
        else              // Standard format
1923 
          pointer = 32;
1924 
      end
1925 
    else
1926 
      begin
1927 
        if(mode)          // Extended format
1928 
          pointer = 52 + 8 * length;
1929 
        else              // Standard format
1930 
          pointer = 32 + 8 * length;
1931 
      end
1932 
 
1933 
    // This is how many bits we need to shift
1934 
    total_bits = pointer;
1935 
 
1936 
    // Waiting until previous msg is finished before sending another one
1937 
    if (arbitration_lost)           //  Arbitration lost. Another node is transmitting. We have to wait until it is finished.
1938 
      wait ( (~can_testbench.i_can_top.i_can_bsp.error_frame) &
1939 
             (~can_testbench.i_can_top.i_can_bsp.rx_inter   ) &
1940 
             (~can_testbench.i_can_top.i_can_bsp.tx_state   )
1941 
           );
1942 
    else                            // We were transmitter of the previous frame. No need to wait for another node to finish transmission.
1943 
      wait ( (~can_testbench.i_can_top.i_can_bsp.error_frame) &
1944 
             (~can_testbench.i_can_top.i_can_bsp.rx_inter   )
1945 
           );
1946 
    arbitration_lost = 0;
1947 
 
1948 
    send_bit(0);                        // SOF
1949 
    previous_bit = 0;
1950 
 
1951 
    fork
1952 
 
1953 
    begin
1954 
      for (cnt=0; cnt<=total_bits; cnt=cnt+1)
1955 
        begin
1956 
          if (stuff_cnt == 5)
1957 
            begin
1958 
              stuff_cnt = 1;
1959 
              total_bits = total_bits + 1;
1960 
              stuff = 1;
1961 
              tmp = ~data[pointer+1];
1962 
              send_bit(~data[pointer+1]);
1963 
              previous_bit = ~data[pointer+1];
1964 
            end
1965 
          else
1966 
            begin
1967 
              if (data[pointer] == previous_bit)
1968 
                stuff_cnt <= stuff_cnt + 1;
1969 
              else
1970 
                stuff_cnt <= 1;
1971 
 
1972 
              stuff = 0;
1973 
              tmp = data[pointer];
1974 
              send_bit(data[pointer]);
1975 
              previous_bit = data[pointer];
1976 
              pointer = pointer - 1;
1977 
            end
1978 
          if (arbitration_lost)
1979 
            cnt=total_bits+1;         // Exit the for loop
1980 
        end
1981 
 
1982 
        // Nothing send after the data (just recessive bit)
1983 
        repeat (13) send_bit(1);         // CRC delimiter + ack + ack delimiter + EOF + intermission= 1 + 1 + 1 + 7 + 3
1984 
    end
1985 
 
1986 
    begin
1987 
      while (mode ? (cnt<32) : (cnt<12))
1988 
        begin
1989 
          #1 wait (can_testbench.i_can_top.sample_point);
1990 
          if (mode)
1991 
            begin
1992 
              if (cnt<32 & tmp & (~rx_and_tx))
1993 
                begin
1994 
                  arbitration_lost = 1;
1995 
                  rx = 1;       // Only recessive is send from now on.
1996 
                end
1997 
            end
1998 
          else
1999 
            begin
2000 
              if (cnt<12 & tmp & (~rx_and_tx))
2001 
                begin
2002 
                  arbitration_lost = 1;
2003 
                  rx = 1;       // Only recessive is send from now on.
2004 
                end
2005 
            end
2006 
        end
2007 
    end
2008 
 
2009 
    join
2010 
 
2011 
  end
2012 
endtask
2013 
 
2014 
 
2015 
 
2016 
// State machine monitor (btl)
2017 
always @ (posedge clk)
2018 
begin
2019 
  if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
2020 
     can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
2021 
    begin
2022 
      $display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);
2023 
      #1000;
2024 
      $stop;
2025 
    end
2026 
 
2027 
  if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
2028 
     can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
2029 
    begin
2030 
      $display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);
2031 
      #1000;
2032 
      $stop;
2033 
    end
2034 
end
2035 
 
2036 
/* stuff_error monitor (bsp)
2037 
always @ (posedge clk)
2038 
begin
2039 
  if(can_testbench.i_can_top.i_can_bsp.stuff_error)
2040 
    begin
2041 
      $display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);
2042 
      $stop;                                      After everything is finished add another condition (something like & (~idle)) and enable stop
2043 
    end
2044 
end
2045 
*/
2046 
 
2047 
//
2048 
// CRC monitor (used until proper CRC generation is used in testbench
2049 
always @ (posedge clk)
2050 
begin
2051 
  if (can_testbench.i_can_top.i_can_bsp.rx_ack       &
2052 
      can_testbench.i_can_top.i_can_bsp.sample_point &
2053 
      can_testbench.i_can_top.i_can_bsp.crc_err
2054 
     )
2055 
    $display("*E (%0t) ERROR: CRC error (Calculated crc = 0x%0x, crc_in = 0x%0x)", $time, can_testbench.i_can_top.i_can_bsp.calculated_crc, can_testbench.i_can_top.i_can_bsp.crc_in);
2056 
end
2057 
 
2058 
 
2059 
 
2060 
 
2061 
 
2062 
/*
2063 
// overrun monitor
2064 
always @ (posedge clk)
2065 
begin
2066 
  if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr & can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_full)
2067 
    $display("(%0t)overrun", $time);
2068 
end
2069 
*/
2070 
 
2071 
 
2072 
// form error monitor
2073 
always @ (posedge clk)
2074 
begin
2075 
  if (can_testbench.i_can_top.i_can_bsp.form_err)
2076 
    $display("*E (%0t) ERROR: form_error", $time);
2077 
end
2078 
 
2079 
 
2080 
 
2081 
// acknowledge error monitor
2082 
always @ (posedge clk)
2083 
begin
2084 
  if (can_testbench.i_can_top.i_can_bsp.ack_err)
2085 
    $display("*E (%0t) ERROR: acknowledge_error", $time);
2086 
end
2087 
 
2088 
/*
2089 
// bit error monitor
2090 
always @ (posedge clk)
2091 
begin
2092 
  if (can_testbench.i_can_top.i_can_bsp.bit_err)
2093 
    $display("*E (%0t) ERROR: bit_error", $time);
2094 
end
2095 
*/
2096 
 
2097 
endmodule
2098 
 

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