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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_testbench.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11  2003/01/14 12:19:29  mohor
// rx_fifo is now working.
//
// Revision 1.10  2003/01/10 17:51:28  mohor
// Temporary version (backup).
//
// Revision 1.9  2003/01/09 21:54:39  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.8  2003/01/08 02:09:43  mohor
// Acceptance filter added.
//
// Revision 1.7  2002/12/28 04:13:53  mohor
// Backup version.
//
// Revision 1.6  2002/12/27 00:12:48  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.5  2002/12/26 16:00:29  mohor
// Testbench define file added. Clock divider register added.
//
// Revision 1.4  2002/12/26 01:33:01  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:12  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:16:54  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
`include "can_testbench_defines.v"
 
module can_testbench();
 
 
 
parameter Tp = 1;
parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
 
 
 
reg         clk;
reg         rst;
reg   [7:0] data_in;
wire  [7:0] data_out;
reg         cs, rw;
reg   [7:0] addr;
reg         rx;
integer     start_tb;
reg   [7:0] tmp_data;
 
// Instantiate can_top module
can_top i_can_top
(
  .clk(clk),
  .rst(rst),
  .data_in(data_in),
  .data_out(data_out),
  .cs(cs),
  .rw(rw),
  .addr(addr),
  .rx(rx)
);
 
 
// Generate clock signal 24 MHz
initial
begin
  clk=0;
  forever #20 clk = ~clk;
end
 
initial
begin
  start_tb = 0;
  data_in = 'hz;
  cs = 0;
  rw = 'hz;
  addr = 'hz;
  rx = 1;
  rst = 1;
  #200 rst = 0;
  #200 initialize_fifo;
  #200 start_tb = 1;
end
 
 
// Main testbench
initial
begin
  wait(start_tb);
 
  // Set bus timing register 0
  write_register(8'd6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
 
  // Set bus timing register 1
  write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
 
 
 
  // Set Clock Divider register
  write_register(8'd31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0});    // Setting the normal mode (not extended)
 
  // Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
  if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
    begin
      // Set Acceptance Code and Acceptance Mask registers
      write_register(8'd16, 8'ha6); // acceptance code 0
      write_register(8'd17, 8'hb0); // acceptance code 1
      write_register(8'd18, 8'h12); // acceptance code 2
      write_register(8'd19, 8'h34); // acceptance code 3
      write_register(8'd20, 8'h0); // acceptance mask 0
      write_register(8'd21, 8'h0); // acceptance mask 1
      write_register(8'd22, 8'h0); // acceptance mask 2
      write_register(8'd23, 8'h0); // acceptance mask 3
    end
  else
    begin
      // Set Acceptance Code and Acceptance Mask registers
//      write_register(8'd4, 8'ha6); // acceptance code
      write_register(8'd4, 8'h08); // acceptance code
      write_register(8'd5, 8'h00); // acceptance mask
    end
 
  #10;
  repeat (1000) @ (posedge clk);
 
  // Switch-off reset mode
  write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
 
  repeat (BRP) @ (posedge clk);   // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
                                  // This difference is resynchronized later.
  repeat (7) send_bit(1);         // Sending EOF
 
//  test_synchronization;
 
 
 
  if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
    begin
//      send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
//      send_frame(0, 1, 29'h12567635, 2, 15'h75b4); // mode, rtr, id, length, crc
      send_frame(0, 1, {26'h00000a6, 3'h5}, 4'h2, 15'h2a11); // mode, rtr, id, length, crc
    end
  else
    begin
//      test_empty_fifo;    test currently switched off
      test_full_fifo;
    end
 
 
 
  $display("CAN Testbench finished !");
  $stop;
end
 
 
 
 
task test_empty_fifo;
  begin
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h3, 15'h6231); // mode, rtr, id, length, crc
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h7, 15'h6047); // mode, rtr, id, length, crc
 
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc
 
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
  end
endtask
 
 
 
task test_full_fifo;
  begin
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    read_overrun_info(0, 31);
 
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h0, 15'h3d18); // mode, rtr, id, length, crc
    read_receive_buffer;
    fifo_info;
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h1, 15'h00ca); // mode, rtr, id, length, crc
    read_receive_buffer;
    fifo_info;
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h2, 15'h744a); // mode, rtr, id, length, crc
    fifo_info;
    read_receive_buffer;
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h3, 15'h6231); // mode, rtr, id, length, crc
    fifo_info;
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h4, 15'h3051); // mode, rtr, id, length, crc
    fifo_info;
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h5, 15'h52ef); // mode, rtr, id, length, crc
    fifo_info;
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h6, 15'h2c03); // mode, rtr, id, length, crc
    fifo_info;
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h7, 15'h6047); // mode, rtr, id, length, crc
    fifo_info;
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc
    fifo_info;
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc
    fifo_info;
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc
    fifo_info;
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc
    fifo_info;
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc
    fifo_info;
    read_overrun_info(0, 15);
 
    release_rx_buffer;
    release_rx_buffer;
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
    send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc
    fifo_info;
    read_overrun_info(0, 15);
    $display("\n\n");
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
 
  end
endtask
 
 
 
task initialize_fifo;
  integer i;
  begin
    for (i=0; i<32; i=i+1)
      begin
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i] = 0;
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i] = 0;
      end
 
    for (i=0; i<64; i=i+1)
      begin
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo[i] = 0;
      end
 
    $display("(%0t) Fifo initialized", $time);
  end
endtask
 
 
task read_overrun_info;
  input [4:0] start_addr;
  input [4:0] end_addr;
  integer i;
  begin
    for (i=start_addr; i<=end_addr; i=i+1)
      begin
        $display("len[0x%0x]=0x%0x", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i]);
        $display("overrun[0x%0x]=0x%0x\n", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i]);
      end
  end
endtask
 
 
task fifo_info;   // displaying how many packets and how many bytes are in fifo
  begin
    $display("(%0t) Currently %0d bytes in fifo (%0d packets)", $time, can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_cnt,
    (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_info_pointer - can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer));
end
endtask
 
 
task read_register;
  input [7:0] reg_addr;
 
  begin
    @ (posedge clk);
    #1;
    addr = reg_addr;
    cs = 1;
    rw = 1;
    @ (posedge clk);
    $display("(%0t) Reading register [%0d] = 0x%0x", $time, addr, data_out);
    #1;
    addr = 'hz;
    cs = 0;
    rw = 'hz;
  end
endtask
 
 
task write_register;
  input [7:0] reg_addr;
  input [7:0] reg_data;
 
  begin
    @ (posedge clk);
    #1;
    addr = reg_addr;
    data_in = reg_data;
    cs = 1;
    rw = 0;
    @ (posedge clk);
    #1;
    addr = 'hz;
    data_in = 'hz;
    cs = 0;
    rw = 'hz;
  end
endtask
 
 
task read_receive_buffer;
  integer i;
  begin
    if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
      begin
        for (i=8'd16; i<=8'd28; i=i+1)
          read_register(i);
        if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])
          $display("\nWARNING: This packet was received with overrun.");
      end
    else
      begin
        for (i=8'd20; i<=8'd29; i=i+1)
          read_register(i);
        if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])
          $display("\nWARNING: This packet was received with overrun.");
      end
  end
endtask
 
 
task release_rx_buffer;
  begin
    write_register(8'd1, 8'h4);
    $display("(%0t) Rx buffer released.", $time);
    repeat (2) @ (posedge clk);   // Time to decrement all the counters
  end
endtask
 
 
task test_synchronization;
  begin
    // Hard synchronization
    #1 rx=0;
    repeat (2*BRP) @ (posedge clk);
    repeat (8*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
 
    // Resynchronization on time
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
 
    // Resynchronization late
    repeat (BRP) @ (posedge clk);
    repeat (BRP) @ (posedge clk);
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
 
    // Resynchronization early
    repeat (8*BRP) @ (posedge clk);   // two frames too early
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
  end
endtask
 
 
task send_bit;
  input bit;
  integer cnt;
  begin
    #1 rx=bit;
    repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
  end
endtask
 
 
task send_frame;
  input mode;
  input remote_trans_req;
  input [28:0] id;
  input  [3:0] length;
  input [14:0] crc;
  integer pointer;
  integer cnt;
  integer total_bits;
  integer stuff_cnt;
  reg [117:0] data;
  reg         previous_bit;
  reg stuff;
  begin
 
    stuff_cnt = 1;
    stuff = 0;
 
    if(mode)          // Extended format
      data = {id[28:18], 1'b1, 1'b1, 1'b0, id[17:0], remote_trans_req, 2'h0, length};
    else              // Standard format
      data = {id[10:0], remote_trans_req, 1'b0, 1'b0, length};
 
    if(length)    // Send data if length is > 0
      begin
        for (cnt=1; cnt<=(2*length); cnt=cnt+1)  // data   (we are sending nibbles)
          data = {data[113:0], cnt[3:0]};
      end
 
    // Adding CRC
    data = {data[104:0], crc[14:0]};
 
 
    // Calculating pointer that points to the bit that will be send
    if(mode)          // Extended format
      pointer = 53 + 8 * length;
    else              // Standard format
      pointer = 32 + 8 * length;
 
    // This is how many bits we need to shift
    total_bits = pointer;
 
 
    send_bit(0);                        // SOF
    previous_bit = 0;
 
    for (cnt=0; cnt<=total_bits; cnt=cnt+1)
      begin
        if (stuff_cnt == 5)
          begin
            stuff_cnt = 1;
            total_bits = total_bits + 1;      //    ??????   Check this
            stuff = 1;
            send_bit(~data[pointer+1]);
            previous_bit = ~data[pointer+1];
          end
//        else if (data[pointer] == previous_bit)
//          stuff_cnt <= stuff_cnt + 1;
        else
          begin
            if (data[pointer] == previous_bit)
              stuff_cnt <= stuff_cnt + 1;
            else
              stuff_cnt <= 1;
 
            stuff = 0;
            send_bit(data[pointer]);        // Bit stuffing comes here !!!
            previous_bit = data[pointer];
            pointer = pointer - 1;
          end
      end
 
 
    // Nothing send after the data (just recessive bit)
    repeat (13) send_bit(1);         // CRC delimiter + ack + ack delimiter + EOF   !!! Check what is the minimum value for which core works ok
 
 
 
  end
endtask
 
 
 
 
// State machine monitor (btl)
always @ (posedge clk)
begin
  if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
     can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
    begin
      $display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);
      #1000;
      $stop;
    end
 
  if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
     can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
    begin
      $display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);
      #1000;
      $stop;
    end
end
 
/* stuff_error monitor (bsp)
always @ (posedge clk)
begin
  if(can_testbench.i_can_top.i_can_bsp.stuff_error)
    begin
      $display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);
      $stop;                                      After everything is finished add another condition (something like & (~idle)) and enable stop
    end
end
*/
 
/*
// CRC monitor (used until proper CRC generation is used in testbench
always @ (posedge clk)
begin
  if (can_testbench.i_can_top.i_can_bsp.crc_error)
    $display("Calculated crc = 0x%0x, crc_in = 0x%0x", can_testbench.i_can_top.i_can_bsp.calculated_crc, can_testbench.i_can_top.i_can_bsp.crc_in);
end
*/
 
 
 
 
/*
// overrun monitor
always @ (posedge clk)
begin
  if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr & can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_full)
    $display("(%0t)overrun", $time);
end
*/
 
 
endmodule
 

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_testbench.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	17	mohor	`// Revision 1.11 2003/01/14 12:19:29 mohor`
49			`// rx_fifo is now working.`
50			`//`
51	16	mohor	`// Revision 1.10 2003/01/10 17:51:28 mohor`
52			`// Temporary version (backup).`
53			`//`
54	15	mohor	`// Revision 1.9 2003/01/09 21:54:39 mohor`
55			`// rx fifo added. Not 100 % verified, yet.`
56			`//`
57	14	mohor	`// Revision 1.8 2003/01/08 02:09:43 mohor`
58			`// Acceptance filter added.`
59			`//`
60	11	mohor	`// Revision 1.7 2002/12/28 04:13:53 mohor`
61			`// Backup version.`
62			`//`
63	10	mohor	`// Revision 1.6 2002/12/27 00:12:48 mohor`
64			`// Header changed, testbench improved to send a frame (crc still missing).`
65			`//`
66	9	mohor	`// Revision 1.5 2002/12/26 16:00:29 mohor`
67			`// Testbench define file added. Clock divider register added.`
68			`//`
69	8	mohor	`// Revision 1.4 2002/12/26 01:33:01 mohor`
70			`// Tripple sampling supported.`
71			`//`
72	7	mohor	`// Revision 1.3 2002/12/25 23:44:12 mohor`
73			`// Commented lines removed.`
74			`//`
75	6	mohor	`// Revision 1.2 2002/12/25 14:16:54 mohor`
76			`// Synchronization working.`
77			`//`
78	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
79			`// Initial`
80	2	mohor	`//`
81			`//`
82	5	mohor	`//`
83	2	mohor
84			`// synopsys translate_off`
85			`include "timescale.v"
86			`// synopsys translate_on`
87			`include "can_defines.v"
88	8	mohor	`include "can_testbench_defines.v"
89	2	mohor
90			`module can_testbench();`
91
92
93
94			`parameter Tp = 1;`
95	8	mohor	parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
96	2	mohor
97
98
99			`reg clk;`
100			`reg rst;`
101			`reg [7:0] data_in;`
102			`wire [7:0] data_out;`
103			`reg cs, rw;`
104			`reg [7:0] addr;`
105			`reg rx;`
106			`integer start_tb;`
107	14	mohor	`reg [7:0] tmp_data;`
108	2	mohor
109	11	mohor	`// Instantiate can_top module`
110	2	mohor	`can_top i_can_top`
111			`(`
112			`.clk(clk),`
113			`.rst(rst),`
114			`.data_in(data_in),`
115			`.data_out(data_out),`
116			`.cs(cs),`
117			`.rw(rw),`
118			`.addr(addr),`
119	10	mohor	`.rx(rx)`
120	2	mohor	`);`
121
122
123			`// Generate clock signal 24 MHz`
124			`initial`
125			`begin`
126			`clk=0;`
127			`forever #20 clk = ~clk;`
128			`end`
129
130			`initial`
131			`begin`
132			`start_tb = 0;`
133			`data_in = 'hz;`
134			`cs = 0;`
135			`rw = 'hz;`
136			`addr = 'hz;`
137			`rx = 1;`
138			`rst = 1;`
139			`#200 rst = 0;`
140	16	mohor	`#200 initialize_fifo;`
141	2	mohor	`#200 start_tb = 1;`
142			`end`
143
144
145			`// Main testbench`
146			`initial`
147			`begin`
148			`wait(start_tb);`
149
150	11	mohor	`// Set bus timing register 0`
151	17	mohor	write_register(8'd6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
152	8	mohor
153	11	mohor	`// Set bus timing register 1`
154	17	mohor	write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
155	11	mohor
156	14	mohor
157
158	11	mohor	`// Set Clock Divider register`
159	17	mohor	write_register(8'd31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
160	16	mohor
161	11	mohor	`// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode`
162			if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
163			`begin`
164			`// Set Acceptance Code and Acceptance Mask registers`
165	17	mohor	`write_register(8'd16, 8'ha6); // acceptance code 0`
166			`write_register(8'd17, 8'hb0); // acceptance code 1`
167			`write_register(8'd18, 8'h12); // acceptance code 2`
168			`write_register(8'd19, 8'h34); // acceptance code 3`
169			`write_register(8'd20, 8'h0); // acceptance mask 0`
170			`write_register(8'd21, 8'h0); // acceptance mask 1`
171			`write_register(8'd22, 8'h0); // acceptance mask 2`
172			`write_register(8'd23, 8'h0); // acceptance mask 3`
173	11	mohor	`end`
174			`else`
175			`begin`
176			`// Set Acceptance Code and Acceptance Mask registers`
177	17	mohor	`// write_register(8'd4, 8'ha6); // acceptance code`
178			`write_register(8'd4, 8'h08); // acceptance code`
179			`write_register(8'd5, 8'h00); // acceptance mask`
180	11	mohor	`end`
181	2	mohor
182			`#10;`
183			`repeat (1000) @ (posedge clk);`
184
185	11	mohor	`// Switch-off reset mode`
186	17	mohor	write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
187	10	mohor
188			`repeat (BRP) @ (posedge clk); // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible`
189			`// This difference is resynchronized later.`
190	11	mohor	`repeat (7) send_bit(1); // Sending EOF`
191	10	mohor
192	9	mohor	`// test_synchronization;`
193	10	mohor
194
195
196	11	mohor	if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
197			`begin`
198	15	mohor	`// send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc`
199	11	mohor	`// send_frame(0, 1, 29'h12567635, 2, 15'h75b4); // mode, rtr, id, length, crc`
200	15	mohor	`send_frame(0, 1, {26'h00000a6, 3'h5}, 4'h2, 15'h2a11); // mode, rtr, id, length, crc`
201	11	mohor	`end`
202			`else`
203			`begin`
204	16	mohor	`// test_empty_fifo; test currently switched off`
205			`test_full_fifo;`
206			`end`
207	15	mohor
208
209
210	16	mohor	`$display("CAN Testbench finished !");`
211			`$stop;`
212			`end`
213	5	mohor
214	14	mohor
215
216
217	16	mohor	`task test_empty_fifo;`
218			`begin`
219			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h3, 15'h6231); // mode, rtr, id, length, crc`
220			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h7, 15'h6047); // mode, rtr, id, length, crc`
221	15	mohor
222	16	mohor	`read_receive_buffer;`
223			`fifo_info;`
224	15	mohor
225	16	mohor	`release_rx_buffer;`
226			`$display("\n\n");`
227			`read_receive_buffer;`
228			`fifo_info;`
229	15	mohor
230	16	mohor	`release_rx_buffer;`
231			`$display("\n\n");`
232			`read_receive_buffer;`
233			`fifo_info;`
234	15	mohor
235	16	mohor	`release_rx_buffer;`
236			`$display("\n\n");`
237			`read_receive_buffer;`
238			`fifo_info;`
239	15	mohor
240	16	mohor	`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc`
241	15	mohor
242	16	mohor	`$display("\n\n");`
243			`read_receive_buffer;`
244			`fifo_info;`
245	2	mohor
246	16	mohor	`release_rx_buffer;`
247			`$display("\n\n");`
248			`read_receive_buffer;`
249			`fifo_info;`
250	2	mohor
251	16	mohor	`release_rx_buffer;`
252			`$display("\n\n");`
253			`read_receive_buffer;`
254			`fifo_info;`
255			`end`
256			`endtask`
257	2	mohor
258
259	16	mohor
260			`task test_full_fifo;`
261			`begin`
262			`release_rx_buffer;`
263			`$display("\n\n");`
264			`read_receive_buffer;`
265			`fifo_info;`
266
267			`read_overrun_info(0, 31);`
268
269			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h0, 15'h3d18); // mode, rtr, id, length, crc`
270			`read_receive_buffer;`
271			`fifo_info;`
272			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h1, 15'h00ca); // mode, rtr, id, length, crc`
273			`read_receive_buffer;`
274			`fifo_info;`
275			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h2, 15'h744a); // mode, rtr, id, length, crc`
276			`fifo_info;`
277			`read_receive_buffer;`
278			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h3, 15'h6231); // mode, rtr, id, length, crc`
279			`fifo_info;`
280			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h4, 15'h3051); // mode, rtr, id, length, crc`
281			`fifo_info;`
282			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h5, 15'h52ef); // mode, rtr, id, length, crc`
283			`fifo_info;`
284			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h6, 15'h2c03); // mode, rtr, id, length, crc`
285			`fifo_info;`
286			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h7, 15'h6047); // mode, rtr, id, length, crc`
287			`fifo_info;`
288			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc`
289			`fifo_info;`
290			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc`
291			`fifo_info;`
292			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc`
293			`fifo_info;`
294			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc`
295			`fifo_info;`
296			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc`
297			`fifo_info;`
298			`read_overrun_info(0, 15);`
299
300			`release_rx_buffer;`
301			`release_rx_buffer;`
302			`release_rx_buffer;`
303			`read_receive_buffer;`
304			`fifo_info;`
305			`send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc`
306			`fifo_info;`
307			`read_overrun_info(0, 15);`
308			`$display("\n\n");`
309
310			`release_rx_buffer;`
311			`read_receive_buffer;`
312			`fifo_info;`
313
314			`release_rx_buffer;`
315			`read_receive_buffer;`
316			`fifo_info;`
317
318			`release_rx_buffer;`
319			`read_receive_buffer;`
320			`fifo_info;`
321
322			`release_rx_buffer;`
323			`read_receive_buffer;`
324			`fifo_info;`
325
326			`release_rx_buffer;`
327			`read_receive_buffer;`
328			`fifo_info;`
329
330			`release_rx_buffer;`
331			`read_receive_buffer;`
332			`fifo_info;`
333
334			`release_rx_buffer;`
335			`read_receive_buffer;`
336			`fifo_info;`
337
338			`release_rx_buffer;`
339			`read_receive_buffer;`
340			`fifo_info;`
341
342			`release_rx_buffer;`
343			`read_receive_buffer;`
344			`fifo_info;`
345
346			`release_rx_buffer;`
347			`read_receive_buffer;`
348			`fifo_info;`
349
350			`release_rx_buffer;`
351			`read_receive_buffer;`
352			`fifo_info;`
353
354			`release_rx_buffer;`
355			`read_receive_buffer;`
356			`fifo_info;`
357
358			`release_rx_buffer;`
359			`read_receive_buffer;`
360			`fifo_info;`
361
362
363			`end`
364			`endtask`
365
366
367
368			`task initialize_fifo;`
369			`integer i;`
370			`begin`
371			`for (i=0; i<32; i=i+1)`
372			`begin`
373			`can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i] = 0;`
374			`can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i] = 0;`
375			`end`
376
377			`for (i=0; i<64; i=i+1)`
378			`begin`
379			`can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo[i] = 0;`
380			`end`
381
382			`$display("(%0t) Fifo initialized", $time);`
383			`end`
384			`endtask`
385
386
387			`task read_overrun_info;`
388			`input [4:0] start_addr;`
389			`input [4:0] end_addr;`
390			`integer i;`
391			`begin`
392			`for (i=start_addr; i<=end_addr; i=i+1)`
393			`begin`
394			`$display("len[0x%0x]=0x%0x", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i]);`
395			`$display("overrun[0x%0x]=0x%0x\n", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i]);`
396			`end`
397			`end`
398			`endtask`
399
400
401			`task fifo_info; // displaying how many packets and how many bytes are in fifo`
402			`begin`
403			`$display("(%0t) Currently %0d bytes in fifo (%0d packets)", $time, can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_cnt,`
404			`(can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_info_pointer - can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer));`
405			`end`
406			`endtask`
407
408
409	14	mohor	`task read_register;`
410			`input [7:0] reg_addr;`
411
412			`begin`
413			`@ (posedge clk);`
414			`#1;`
415			`addr = reg_addr;`
416			`cs = 1;`
417			`rw = 1;`
418			`@ (posedge clk);`
419	17	mohor	`$display("(%0t) Reading register [%0d] = 0x%0x", $time, addr, data_out);`
420	14	mohor	`#1;`
421			`addr = 'hz;`
422			`cs = 0;`
423			`rw = 'hz;`
424			`end`
425			`endtask`
426
427
428	2	mohor	`task write_register;`
429			`input [7:0] reg_addr;`
430			`input [7:0] reg_data;`
431
432			`begin`
433			`@ (posedge clk);`
434			`#1;`
435			`addr = reg_addr;`
436			`data_in = reg_data;`
437			`cs = 1;`
438			`rw = 0;`
439			`@ (posedge clk);`
440			`#1;`
441			`addr = 'hz;`
442			`data_in = 'hz;`
443			`cs = 0;`
444			`rw = 'hz;`
445			`end`
446			`endtask`
447	7	mohor
448
449	15	mohor	`task read_receive_buffer;`
450			`integer i;`
451			`begin`
452			if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
453			`begin`
454	17	mohor	`for (i=8'd16; i<=8'd28; i=i+1)`
455	15	mohor	`read_register(i);`
456	16	mohor	`if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])`
457			`$display("\nWARNING: This packet was received with overrun.");`
458	15	mohor	`end`
459			`else`
460			`begin`
461	17	mohor	`for (i=8'd20; i<=8'd29; i=i+1)`
462	15	mohor	`read_register(i);`
463	16	mohor	`if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])`
464			`$display("\nWARNING: This packet was received with overrun.");`
465	15	mohor	`end`
466			`end`
467			`endtask`
468
469
470			`task release_rx_buffer;`
471			`begin`
472	17	mohor	`write_register(8'd1, 8'h4);`
473	16	mohor	`$display("(%0t) Rx buffer released.", $time);`
474			`repeat (2) @ (posedge clk); // Time to decrement all the counters`
475	15	mohor	`end`
476			`endtask`
477
478
479	8	mohor	`task test_synchronization;`
480			`begin`
481			`// Hard synchronization`
482			`#1 rx=0;`
483			`repeat (2*BRP) @ (posedge clk);`
484			`repeat (8*BRP) @ (posedge clk);`
485			`#1 rx=1;`
486			`repeat (10*BRP) @ (posedge clk);`
487
488			`// Resynchronization on time`
489			`#1 rx=0;`
490			`repeat (10*BRP) @ (posedge clk);`
491			`#1 rx=1;`
492			`repeat (10*BRP) @ (posedge clk);`
493
494			`// Resynchronization late`
495			`repeat (BRP) @ (posedge clk);`
496			`repeat (BRP) @ (posedge clk);`
497			`#1 rx=0;`
498			`repeat (10*BRP) @ (posedge clk);`
499			`#1 rx=1;`
500

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