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mohor |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// can_testbench.v ////
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//// ////
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//// ////
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mohor |
//// This file is part of the CAN Protocol Controller ////
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2 |
mohor |
//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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mohor |
//// All additional information is available in the README.txt ////
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mohor |
//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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mohor |
//// Copyright (C) 2002, 2003 Authors ////
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mohor |
//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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mohor |
// Revision 1.18 2003/02/04 14:34:45 mohor
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// *** empty log message ***
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//
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mohor |
// Revision 1.17 2003/01/31 01:13:31 mohor
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// backup.
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//
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mohor |
// Revision 1.16 2003/01/16 13:36:14 mohor
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// Form error supported. When receiving messages, last bit of the end-of-frame
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// does not generate form error. Receiver goes to the idle mode one bit sooner.
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// (CAN specification ver 2.0, part B, page 57).
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//
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mohor |
// Revision 1.15 2003/01/15 21:05:06 mohor
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// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
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//
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mohor |
// Revision 1.14 2003/01/15 14:40:16 mohor
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// RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.
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//
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mohor |
// Revision 1.13 2003/01/15 13:16:42 mohor
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// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.
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//
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mohor |
// Revision 1.12 2003/01/14 17:25:03 mohor
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// Addresses corrected to decimal values (previously hex).
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//
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mohor |
// Revision 1.11 2003/01/14 12:19:29 mohor
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// rx_fifo is now working.
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//
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mohor |
// Revision 1.10 2003/01/10 17:51:28 mohor
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// Temporary version (backup).
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//
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mohor |
// Revision 1.9 2003/01/09 21:54:39 mohor
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// rx fifo added. Not 100 % verified, yet.
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//
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mohor |
// Revision 1.8 2003/01/08 02:09:43 mohor
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// Acceptance filter added.
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//
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mohor |
// Revision 1.7 2002/12/28 04:13:53 mohor
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// Backup version.
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//
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mohor |
// Revision 1.6 2002/12/27 00:12:48 mohor
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// Header changed, testbench improved to send a frame (crc still missing).
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//
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mohor |
// Revision 1.5 2002/12/26 16:00:29 mohor
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// Testbench define file added. Clock divider register added.
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//
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mohor |
// Revision 1.4 2002/12/26 01:33:01 mohor
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// Tripple sampling supported.
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//
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mohor |
// Revision 1.3 2002/12/25 23:44:12 mohor
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// Commented lines removed.
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//
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mohor |
// Revision 1.2 2002/12/25 14:16:54 mohor
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// Synchronization working.
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//
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mohor |
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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// Initial
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mohor |
//
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//
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mohor |
//
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mohor |
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "can_defines.v"
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mohor |
`include "can_testbench_defines.v"
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mohor |
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module can_testbench();
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parameter Tp = 1;
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mohor |
parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
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mohor |
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reg clk;
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reg rst;
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reg [7:0] data_in;
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wire [7:0] data_out;
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reg cs, rw;
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reg [7:0] addr;
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reg rx;
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mohor |
wire tx;
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wire rx_and_tx;
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mohor |
integer start_tb;
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mohor |
reg [7:0] tmp_data;
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mohor |
reg delayed_tx;
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2 |
mohor |
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24 |
mohor |
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mohor |
// Instantiate can_top module
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mohor |
can_top i_can_top
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(
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.clk(clk),
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.rst(rst),
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.data_in(data_in),
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.data_out(data_out),
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.cs(cs),
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.rw(rw),
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.addr(addr),
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mohor |
.rx(rx_and_tx),
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.tx(tx)
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mohor |
);
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mohor |
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mohor |
// Generate clock signal 24 MHz
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initial
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begin
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clk=0;
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forever #20 clk = ~clk;
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end
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initial
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begin
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start_tb = 0;
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data_in = 'hz;
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cs = 0;
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rw = 'hz;
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addr = 'hz;
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rx = 1;
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rst = 1;
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#200 rst = 0;
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mohor |
#200 initialize_fifo;
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mohor |
#200 start_tb = 1;
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end
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mohor |
// Generating delayed tx signal (CAN transciever delay)
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always
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begin
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wait (tx);
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repeat (4*BRP) @ (posedge clk); // 4 time quants delay
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#1 delayed_tx = tx;
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wait (~tx);
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repeat (4*BRP) @ (posedge clk); // 4 time quants delay
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#1 delayed_tx = tx;
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end
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assign rx_and_tx = rx & delayed_tx;
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mohor |
// Main testbench
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initial
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begin
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wait(start_tb);
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mohor |
// Set bus timing register 0
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mohor |
write_register(8'd6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
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mohor |
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// Set bus timing register 1
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write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
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mohor |
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14 |
mohor |
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mohor |
// Set Clock Divider register
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mohor |
write_register(8'd31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
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mohor |
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mohor |
// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
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if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
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begin
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// Set Acceptance Code and Acceptance Mask registers
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mohor |
write_register(8'd16, 8'ha6); // acceptance code 0
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write_register(8'd17, 8'hb0); // acceptance code 1
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write_register(8'd18, 8'h12); // acceptance code 2
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write_register(8'd19, 8'h30); // acceptance code 3
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write_register(8'd20, 8'h0); // acceptance mask 0
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write_register(8'd21, 8'h0); // acceptance mask 1
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mohor |
write_register(8'd22, 8'h00); // acceptance mask 2
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write_register(8'd23, 8'h00); // acceptance mask 3
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mohor |
end
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else
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begin
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// Set Acceptance Code and Acceptance Mask registers
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mohor |
// write_register(8'd4, 8'ha6); // acceptance code
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write_register(8'd4, 8'he8); // acceptance code
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write_register(8'd5, 8'h0f); // acceptance mask
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mohor |
end
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mohor |
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#10;
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repeat (1000) @ (posedge clk);
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mohor |
// Switch-off reset mode
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mohor |
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
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mohor |
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repeat (BRP) @ (posedge clk); // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
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// This difference is resynchronized later.
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mohor |
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// After exiting the reset mode
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mohor |
repeat (7) send_bit(1); // Sending EOF
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mohor |
repeat (3) send_bit(1); // Sending Interframe
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mohor |
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mohor |
// test_synchronization;
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10 |
mohor |
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mohor |
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
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begin
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mohor |
// test_empty_fifo_ext; // test currently switched off
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test_full_fifo_ext; // test currently switched on
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// send_frame_ext; // test currently switched off
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mohor |
end
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else
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begin
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mohor |
// test_empty_fifo; // test currently switched off
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mohor |
// test_full_fifo; // test currently switched off
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send_frame; // test currently switched on
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mohor |
end
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15 |
mohor |
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mohor |
$display("CAN Testbench finished !");
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$stop;
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end
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mohor |
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14 |
mohor |
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18 |
mohor |
task send_frame; // CAN IP core sends frames
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begin
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14 |
mohor |
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18 |
mohor |
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
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begin
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// Writing TX frame information + identifier + data
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write_register(8'd16, 8'h12);
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write_register(8'd17, 8'h34);
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write_register(8'd18, 8'h56);
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write_register(8'd19, 8'h78);
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write_register(8'd20, 8'h9a);
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write_register(8'd21, 8'hbc);
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write_register(8'd22, 8'hde);
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write_register(8'd23, 8'hf0);
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write_register(8'd24, 8'h0f);
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write_register(8'd25, 8'hed);
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write_register(8'd26, 8'hcb);
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write_register(8'd27, 8'ha9);
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write_register(8'd28, 8'h87);
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end
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else
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begin
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25 |
mohor |
write_register(8'd10, 8'hea); // Writing ID[10:3] = 0xea
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26 |
mohor |
write_register(8'd11, 8'h28); // Writing ID[3:0] = 0x1, rtr = 0, length = 8
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18 |
mohor |
write_register(8'd12, 8'h56); // data byte 1
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write_register(8'd13, 8'h78); // data byte 2
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write_register(8'd14, 8'h9a); // data byte 3
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write_register(8'd15, 8'hbc); // data byte 4
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write_register(8'd16, 8'hde); // data byte 5
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write_register(8'd17, 8'hf0); // data byte 6
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write_register(8'd18, 8'h0f); // data byte 7
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write_register(8'd19, 8'hed); // data byte 8
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end
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25 |
mohor |
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fork
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begin
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$display("\n\nStart receiving data from CAN bus");
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receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
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receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
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receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
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receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc
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receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc
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receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc
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end
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| 310 |
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begin
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tx_request;
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end
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| 315 |
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begin
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| 316 |
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// Transmitting acknowledge
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| 317 |
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wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
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| 318 |
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rx = 0;
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| 319 |
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wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim);
|
| 320 |
|
|
rx = 1;
|
| 321 |
|
|
end
|
| 322 |
|
|
|
| 323 |
|
|
join
|
| 324 |
|
|
|
| 325 |
|
|
read_receive_buffer;
|
| 326 |
|
|
release_rx_buffer;
|
| 327 |
|
|
release_rx_buffer;
|
| 328 |
|
|
read_receive_buffer;
|
| 329 |
|
|
release_rx_buffer;
|
| 330 |
|
|
read_receive_buffer;
|
| 331 |
|
|
release_rx_buffer;
|
| 332 |
|
|
read_receive_buffer;
|
| 333 |
|
|
release_rx_buffer;
|
| 334 |
|
|
read_receive_buffer;
|
| 335 |
|
|
|
| 336 |
|
|
#200000;
|
| 337 |
|
|
|
| 338 |
|
|
read_receive_buffer;
|
| 339 |
|
|
|
| 340 |
18 |
mohor |
end
|
| 341 |
|
|
endtask
|
| 342 |
|
|
|
| 343 |
|
|
|
| 344 |
|
|
|
| 345 |
16 |
mohor |
task test_empty_fifo;
|
| 346 |
|
|
begin
|
| 347 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h3, 15'h7bcb); // mode, rtr, id, length, crc
|
| 348 |
|
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h7, 15'h085c); // mode, rtr, id, length, crc
|
| 349 |
15 |
mohor |
|
| 350 |
16 |
mohor |
read_receive_buffer;
|
| 351 |
|
|
fifo_info;
|
| 352 |
15 |
mohor |
|
| 353 |
16 |
mohor |
release_rx_buffer;
|
| 354 |
|
|
$display("\n\n");
|
| 355 |
|
|
read_receive_buffer;
|
| 356 |
|
|
fifo_info;
|
| 357 |
15 |
mohor |
|
| 358 |
16 |
mohor |
release_rx_buffer;
|
| 359 |
|
|
$display("\n\n");
|
| 360 |
|
|
read_receive_buffer;
|
| 361 |
|
|
fifo_info;
|
| 362 |
15 |
mohor |
|
| 363 |
16 |
mohor |
release_rx_buffer;
|
| 364 |
|
|
$display("\n\n");
|
| 365 |
|
|
read_receive_buffer;
|
| 366 |
|
|
fifo_info;
|
| 367 |
15 |
mohor |
|
| 368 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
| 369 |
15 |
mohor |
|
| 370 |
16 |
mohor |
$display("\n\n");
|
| 371 |
|
|
read_receive_buffer;
|
| 372 |
|
|
fifo_info;
|
| 373 |
2 |
mohor |
|
| 374 |
16 |
mohor |
release_rx_buffer;
|
| 375 |
|
|
$display("\n\n");
|
| 376 |
|
|
read_receive_buffer;
|
| 377 |
|
|
fifo_info;
|
| 378 |
2 |
mohor |
|
| 379 |
16 |
mohor |
release_rx_buffer;
|
| 380 |
|
|
$display("\n\n");
|
| 381 |
|
|
read_receive_buffer;
|
| 382 |
|
|
fifo_info;
|
| 383 |
|
|
end
|
| 384 |
|
|
endtask
|
| 385 |
2 |
mohor |
|
| 386 |
|
|
|
| 387 |
16 |
mohor |
|
| 388 |
20 |
mohor |
task test_empty_fifo_ext;
|
| 389 |
|
|
begin
|
| 390 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
|
| 391 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
|
| 392 |
|
|
|
| 393 |
|
|
read_receive_buffer;
|
| 394 |
|
|
fifo_info;
|
| 395 |
|
|
|
| 396 |
|
|
release_rx_buffer;
|
| 397 |
|
|
$display("\n\n");
|
| 398 |
|
|
read_receive_buffer;
|
| 399 |
|
|
fifo_info;
|
| 400 |
|
|
|
| 401 |
|
|
release_rx_buffer;
|
| 402 |
|
|
$display("\n\n");
|
| 403 |
|
|
read_receive_buffer;
|
| 404 |
|
|
fifo_info;
|
| 405 |
|
|
|
| 406 |
|
|
release_rx_buffer;
|
| 407 |
|
|
$display("\n\n");
|
| 408 |
|
|
read_receive_buffer;
|
| 409 |
|
|
fifo_info;
|
| 410 |
|
|
|
| 411 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
|
| 412 |
|
|
|
| 413 |
|
|
$display("\n\n");
|
| 414 |
|
|
read_receive_buffer;
|
| 415 |
|
|
fifo_info;
|
| 416 |
|
|
|
| 417 |
|
|
release_rx_buffer;
|
| 418 |
|
|
$display("\n\n");
|
| 419 |
|
|
read_receive_buffer;
|
| 420 |
|
|
fifo_info;
|
| 421 |
|
|
|
| 422 |
|
|
release_rx_buffer;
|
| 423 |
|
|
$display("\n\n");
|
| 424 |
|
|
read_receive_buffer;
|
| 425 |
|
|
fifo_info;
|
| 426 |
|
|
end
|
| 427 |
|
|
endtask
|
| 428 |
|
|
|
| 429 |
|
|
|
| 430 |
|
|
|
| 431 |
16 |
mohor |
task test_full_fifo;
|
| 432 |
|
|
begin
|
| 433 |
|
|
release_rx_buffer;
|
| 434 |
|
|
$display("\n\n");
|
| 435 |
|
|
read_receive_buffer;
|
| 436 |
|
|
fifo_info;
|
| 437 |
|
|
|
| 438 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h0, 15'h4edd); // mode, rtr, id, length, crc
|
| 439 |
16 |
mohor |
read_receive_buffer;
|
| 440 |
|
|
fifo_info;
|
| 441 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h1, 15'h1ccf); // mode, rtr, id, length, crc
|
| 442 |
16 |
mohor |
read_receive_buffer;
|
| 443 |
|
|
fifo_info;
|
| 444 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h2, 15'h73f4); // mode, rtr, id, length, crc
|
| 445 |
16 |
mohor |
fifo_info;
|
| 446 |
|
|
read_receive_buffer;
|
| 447 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h3, 15'h7bcb); // mode, rtr, id, length, crc
|
| 448 |
16 |
mohor |
fifo_info;
|
| 449 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h4, 15'h37da); // mode, rtr, id, length, crc
|
| 450 |
16 |
mohor |
fifo_info;
|
| 451 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h5, 15'h7e15); // mode, rtr, id, length, crc
|
| 452 |
16 |
mohor |
fifo_info;
|
| 453 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h6, 15'h39cf); // mode, rtr, id, length, crc
|
| 454 |
16 |
mohor |
fifo_info;
|
| 455 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h7, 15'h085c); // mode, rtr, id, length, crc
|
| 456 |
16 |
mohor |
fifo_info;
|
| 457 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
| 458 |
16 |
mohor |
fifo_info;
|
| 459 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
| 460 |
16 |
mohor |
fifo_info;
|
| 461 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
| 462 |
16 |
mohor |
fifo_info;
|
| 463 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
| 464 |
16 |
mohor |
fifo_info;
|
| 465 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
| 466 |
16 |
mohor |
fifo_info;
|
| 467 |
|
|
read_overrun_info(0, 15);
|
| 468 |
|
|
|
| 469 |
|
|
release_rx_buffer;
|
| 470 |
|
|
release_rx_buffer;
|
| 471 |
|
|
release_rx_buffer;
|
| 472 |
|
|
read_receive_buffer;
|
| 473 |
|
|
fifo_info;
|
| 474 |
18 |
mohor |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
| 475 |
16 |
mohor |
fifo_info;
|
| 476 |
|
|
read_overrun_info(0, 15);
|
| 477 |
|
|
$display("\n\n");
|
| 478 |
|
|
|
| 479 |
|
|
release_rx_buffer;
|
| 480 |
|
|
read_receive_buffer;
|
| 481 |
|
|
fifo_info;
|
| 482 |
|
|
|
| 483 |
|
|
release_rx_buffer;
|
| 484 |
|
|
read_receive_buffer;
|
| 485 |
|
|
fifo_info;
|
| 486 |
|
|
|
| 487 |
|
|
release_rx_buffer;
|
| 488 |
|
|
read_receive_buffer;
|
| 489 |
|
|
fifo_info;
|
| 490 |
|
|
|
| 491 |
|
|
release_rx_buffer;
|
| 492 |
|
|
read_receive_buffer;
|
| 493 |
|
|
fifo_info;
|
| 494 |
|
|
|
| 495 |
|
|
release_rx_buffer;
|
| 496 |
|
|
read_receive_buffer;
|
| 497 |
|
|
fifo_info;
|
| 498 |
|
|
|
| 499 |
|
|
release_rx_buffer;
|
| 500 |
|
|
read_receive_buffer;
|
| 501 |
|
|
fifo_info;
|
| 502 |
|
|
|
| 503 |
|
|
release_rx_buffer;
|
| 504 |
|
|
read_receive_buffer;
|
| 505 |
|
|
fifo_info;
|
| 506 |
|
|
|
| 507 |
|
|
release_rx_buffer;
|
| 508 |
|
|
read_receive_buffer;
|
| 509 |
|
|
fifo_info;
|
| 510 |
|
|
|
| 511 |
|
|
release_rx_buffer;
|
| 512 |
|
|
read_receive_buffer;
|
| 513 |
|
|
fifo_info;
|
| 514 |
|
|
|
| 515 |
|
|
release_rx_buffer;
|
| 516 |
|
|
read_receive_buffer;
|
| 517 |
|
|
fifo_info;
|
| 518 |
|
|
|
| 519 |
|
|
release_rx_buffer;
|
| 520 |
|
|
read_receive_buffer;
|
| 521 |
|
|
fifo_info;
|
| 522 |
|
|
|
| 523 |
|
|
release_rx_buffer;
|
| 524 |
|
|
read_receive_buffer;
|
| 525 |
|
|
fifo_info;
|
| 526 |
|
|
|
| 527 |
|
|
release_rx_buffer;
|
| 528 |
|
|
read_receive_buffer;
|
| 529 |
|
|
fifo_info;
|
| 530 |
|
|
|
| 531 |
|
|
end
|
| 532 |
|
|
endtask
|
| 533 |
|
|
|
| 534 |
|
|
|
| 535 |
|
|
|
| 536 |
20 |
mohor |
task test_full_fifo_ext;
|
| 537 |
|
|
begin
|
| 538 |
|
|
release_rx_buffer;
|
| 539 |
|
|
$display("\n\n");
|
| 540 |
|
|
read_receive_buffer;
|
| 541 |
|
|
fifo_info;
|
| 542 |
|
|
|
| 543 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h0, 15'h6f54); // mode, rtr, id, length, crc
|
| 544 |
|
|
read_receive_buffer;
|
| 545 |
|
|
fifo_info;
|
| 546 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h1, 15'h6d38); // mode, rtr, id, length, crc
|
| 547 |
|
|
read_receive_buffer;
|
| 548 |
|
|
fifo_info;
|
| 549 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h2, 15'h053e); // mode, rtr, id, length, crc
|
| 550 |
|
|
fifo_info;
|
| 551 |
|
|
read_receive_buffer;
|
| 552 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
|
| 553 |
|
|
fifo_info;
|
| 554 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h4, 15'h4bba); // mode, rtr, id, length, crc
|
| 555 |
|
|
fifo_info;
|
| 556 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h5, 15'h4d7d); // mode, rtr, id, length, crc
|
| 557 |
|
|
fifo_info;
|
| 558 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h6, 15'h6f40); // mode, rtr, id, length, crc
|
| 559 |
|
|
fifo_info;
|
| 560 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
|
| 561 |
|
|
fifo_info;
|
| 562 |
|
|
read_overrun_info(0, 10);
|
| 563 |
|
|
|
| 564 |
|
|
release_rx_buffer;
|
| 565 |
|
|
release_rx_buffer;
|
| 566 |
|
|
fifo_info;
|
| 567 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
|
| 568 |
|
|
fifo_info;
|
| 569 |
|
|
read_overrun_info(0, 15);
|
| 570 |
|
|
$display("\n\n");
|
| 571 |
|
|
|
| 572 |
|
|
release_rx_buffer;
|
| 573 |
|
|
read_receive_buffer;
|
| 574 |
|
|
fifo_info;
|
| 575 |
|
|
|
| 576 |
|
|
release_rx_buffer;
|
| 577 |
|
|
read_receive_buffer;
|
| 578 |
|
|
fifo_info;
|
| 579 |
|
|
|
| 580 |
|
|
release_rx_buffer;
|
| 581 |
|
|
read_receive_buffer;
|
| 582 |
|
|
fifo_info;
|
| 583 |
|
|
|
| 584 |
|
|
release_rx_buffer;
|
| 585 |
|
|
read_receive_buffer;
|
| 586 |
|
|
fifo_info;
|
| 587 |
|
|
|
| 588 |
|
|
release_rx_buffer;
|
| 589 |
|
|
read_receive_buffer;
|
| 590 |
|
|
fifo_info;
|
| 591 |
|
|
|
| 592 |
|
|
release_rx_buffer;
|
| 593 |
|
|
read_receive_buffer;
|
| 594 |
|
|
fifo_info;
|
| 595 |
|
|
|
| 596 |
|
|
release_rx_buffer;
|
| 597 |
|
|
read_receive_buffer;
|
| 598 |
|
|
fifo_info;
|
| 599 |
|
|
|
| 600 |
|
|
end
|
| 601 |
|
|
endtask
|
| 602 |
|
|
|
| 603 |
|
|
|
| 604 |
|
|
|
| 605 |
16 |
mohor |
task initialize_fifo;
|
| 606 |
|
|
integer i;
|
| 607 |
|
|
begin
|
| 608 |
|
|
for (i=0; i<32; i=i+1)
|
| 609 |
|
|
begin
|
| 610 |
|
|
can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i] = 0;
|
| 611 |
|
|
can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i] = 0;
|
| 612 |
|
|
end
|
| 613 |
|
|
|
| 614 |
|
|
for (i=0; i<64; i=i+1)
|
| 615 |
|
|
begin
|
| 616 |
|
|
can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo[i] = 0;
|
| 617 |
|
|
end
|
| 618 |
|
|
|
| 619 |
|
|
$display("(%0t) Fifo initialized", $time);
|
| 620 |
|
|
end
|
| 621 |
|
|
endtask
|
| 622 |
|
|
|
| 623 |
|
|
|
| 624 |
|
|
task read_overrun_info;
|
| 625 |
|
|
input [4:0] start_addr;
|
| 626 |
|
|
input [4:0] end_addr;
|
| 627 |
|
|
integer i;
|
| 628 |
|
|
begin
|
| 629 |
|
|
for (i=start_addr; i<=end_addr; i=i+1)
|
| 630 |
|
|
begin
|
| 631 |
|
|
$display("len[0x%0x]=0x%0x", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i]);
|
| 632 |
|
|
$display("overrun[0x%0x]=0x%0x\n", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i]);
|
| 633 |
|
|
end
|
| 634 |
|
|
end
|
| 635 |
|
|
endtask
|
| 636 |
|
|
|
| 637 |
|
|
|
| 638 |
24 |
mohor |
task fifo_info; // Displaying how many packets and how many bytes are in fifo. Not working when wr_info_pointer is smaller than rd_info_pointer.
|
| 639 |
16 |
mohor |
begin
|
| 640 |
24 |
mohor |
$display("(%0t) Currently %0d bytes in fifo (%0d packets)", $time, can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_cnt,
|
| 641 |
|
|
(can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_info_pointer - can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer));
|
| 642 |
16 |
mohor |
end
|
| 643 |
|
|
endtask
|
| 644 |
|
|
|
| 645 |
|
|
|
| 646 |
14 |
mohor |
task read_register;
|
| 647 |
|
|
input [7:0] reg_addr;
|
| 648 |
|
|
|
| 649 |
|
|
begin
|
| 650 |
|
|
@ (posedge clk);
|
| 651 |
|
|
#1;
|
| 652 |
|
|
addr = reg_addr;
|
| 653 |
|
|
cs = 1;
|
| 654 |
|
|
rw = 1;
|
| 655 |
|
|
@ (posedge clk);
|
| 656 |
17 |
mohor |
$display("(%0t) Reading register [%0d] = 0x%0x", $time, addr, data_out);
|
| 657 |
14 |
mohor |
#1;
|
| 658 |
|
|
addr = 'hz;
|
| 659 |
|
|
cs = 0;
|
| 660 |
|
|
rw = 'hz;
|
| 661 |
|
|
end
|
| 662 |
|
|
endtask
|
| 663 |
|
|
|
| 664 |
|
|
|
| 665 |
2 |
mohor |
task write_register;
|
| 666 |
|
|
input [7:0] reg_addr;
|
| 667 |
|
|
input [7:0] reg_data;
|
| 668 |
|
|
|
| 669 |
|
|
begin
|
| 670 |
|
|
@ (posedge clk);
|
| 671 |
|
|
#1;
|
| 672 |
|
|
addr = reg_addr;
|
| 673 |
|
|
data_in = reg_data;
|
| 674 |
|
|
cs = 1;
|
| 675 |
|
|
rw = 0;
|
| 676 |
|
|
@ (posedge clk);
|
| 677 |
|
|
#1;
|
| 678 |
|
|
addr = 'hz;
|
| 679 |
|
|
data_in = 'hz;
|
| 680 |
|
|
cs = 0;
|
| 681 |
|
|
rw = 'hz;
|
| 682 |
|
|
end
|
| 683 |
|
|
endtask
|
| 684 |
7 |
mohor |
|
| 685 |
|
|
|
| 686 |
15 |
mohor |
task read_receive_buffer;
|
| 687 |
|
|
integer i;
|
| 688 |
|
|
begin
|
| 689 |
|
|
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
|
| 690 |
|
|
begin
|
| 691 |
17 |
mohor |
for (i=8'd16; i<=8'd28; i=i+1)
|
| 692 |
15 |
mohor |
read_register(i);
|
| 693 |
16 |
mohor |
if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])
|
| 694 |
|
|
$display("\nWARNING: This packet was received with overrun.");
|
| 695 |
15 |
mohor |
end
|
| 696 |
|
|
else
|
| 697 |
|
|
begin
|
| 698 |
17 |
mohor |
for (i=8'd20; i<=8'd29; i=i+1)
|
| 699 |
15 |
mohor |
read_register(i);
|
| 700 |
16 |
mohor |
if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])
|
| 701 |
|
|
$display("\nWARNING: This packet was received with overrun.");
|
| 702 |
15 |
mohor |
end
|
| 703 |
|
|
end
|
| 704 |
|
|
endtask
|
| 705 |
|
|
|
| 706 |
|
|
|
| 707 |
|
|
task release_rx_buffer;
|
| 708 |
|
|
begin
|
| 709 |
17 |
mohor |
write_register(8'd1, 8'h4);
|
| 710 |
16 |
mohor |
$display("(%0t) Rx buffer released.", $time);
|
| 711 |
|
|
repeat (2) @ (posedge clk); // Time to decrement all the counters
|
| 712 |
15 |
mohor |
end
|
| 713 |
|
|
endtask
|
| 714 |
|
|
|
| 715 |
|
|
|
| 716 |
25 |
mohor |
task tx_request;
|
| 717 |
|
|
begin
|
| 718 |
|
|
write_register(8'd1, 8'h1);
|
| 719 |
|
|
$display("(%0t) Tx requested.", $time);
|
| 720 |
|
|
repeat (2) @ (posedge clk); // Time to decrement all the counters, etc.
|
| 721 |
|
|
end
|
| 722 |
|
|
endtask
|
| 723 |
|
|
|
| 724 |
|
|
|
| 725 |
8 |
mohor |
task test_synchronization;
|
| 726 |
|
|
begin
|
| 727 |
|
|
// Hard synchronization
|
| 728 |
|
|
#1 rx=0;
|
| 729 |
|
|
repeat (2*BRP) @ (posedge clk);
|
| 730 |
|
|
repeat (8*BRP) @ (posedge clk);
|
| 731 |
|
|
#1 rx=1;
|
| 732 |
|
|
repeat (10*BRP) @ (posedge clk);
|
| 733 |
|
|
|
| 734 |
|
|
// Resynchronization on time
|
| 735 |
|
|
#1 rx=0;
|
| 736 |
|
|
repeat (10*BRP) @ (posedge clk);
|
| 737 |
|
|
#1 rx=1;
|
| 738 |
|
|
repeat (10*BRP) @ (posedge clk);
|
| 739 |
|
|
|
| 740 |
|
|
// Resynchronization late
|
| 741 |
|
|
repeat (BRP) @ (posedge clk);
|
| 742 |
|
|
repeat (BRP) @ (posedge clk);
|
| 743 |
|
|
#1 rx=0;
|
| 744 |
|
|
repeat (10*BRP) @ (posedge clk);
|
| 745 |
|
|
#1 rx=1;
|
| 746 |
|
|
|
| 747 |
|
|
// Resynchronization early
|
| 748 |
|
|
repeat (8*BRP) @ (posedge clk); // two frames too early
|
| 749 |
|
|
#1 rx=0;
|
| 750 |
|
|
repeat (10*BRP) @ (posedge clk);
|
| 751 |
|
|
#1 rx=1;
|
| 752 |
|
|
repeat (10*BRP) @ (posedge clk);
|
| 753 |
|
|
end
|
| 754 |
|
|
endtask
|
| 755 |
7 |
mohor |
|
| 756 |
8 |
mohor |
|
| 757 |
9 |
mohor |
task send_bit;
|
| 758 |
|
|
input bit;
|
| 759 |
|
|
integer cnt;
|
| 760 |
|
|
begin
|
| 761 |
|
|
#1 rx=bit;
|
| 762 |
|
|
repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
|
| 763 |
|
|
end
|
| 764 |
|
|
endtask
|
| 765 |
|
|
|
| 766 |
|
|
|
| 767 |
18 |
mohor |
task receive_frame; // CAN IP core receives frames
|
| 768 |
8 |
mohor |
input mode;
|
| 769 |
11 |
mohor |
input remote_trans_req;
|
| 770 |
9 |
mohor |
input [28:0] id;
|
| 771 |
|
|
input [3:0] length;
|
| 772 |
11 |
mohor |
input [14:0] crc;
|
| 773 |
25 |
mohor |
|
| 774 |
15 |
mohor |
reg [117:0] data;
|
| 775 |
16 |
mohor |
reg previous_bit;
|
| 776 |
25 |
mohor |
reg stuff;
|
| 777 |
|
|
reg tmp;
|
| 778 |
|
|
reg arbitration_lost;
|
| 779 |
|
|
integer pointer;
|
| 780 |
|
|
integer cnt;
|
| 781 |
|
|
integer total_bits;
|
| 782 |
|
|
integer stuff_cnt;
|
| 783 |
24 |
mohor |
|
| 784 |
15 |
mohor |
begin
|
| 785 |
9 |
mohor |
|
| 786 |
16 |
mohor |
stuff_cnt = 1;
|
| 787 |
|
|
stuff = 0;
|
| 788 |
15 |
mohor |
|
| 789 |
|
|
if(mode) // Extended format
|
| 790 |
20 |
mohor |
data = {id[28:18], 1'b1, 1'b1, id[17:0], remote_trans_req, 2'h0, length};
|
| 791 |
15 |
mohor |
else // Standard format
|
| 792 |
|
|
data = {id[10:0], remote_trans_req, 1'b0, 1'b0, length};
|
| 793 |
|
|
|
| 794 |
19 |
mohor |
if (~remote_trans_req)
|
| 795 |
15 |
mohor |
begin
|
| 796 |
19 |
mohor |
if(length) // Send data if length is > 0
|
| 797 |
|
|
begin
|
| 798 |
|
|
for (cnt=1; cnt<=(2*length); cnt=cnt+1) // data (we are sending nibbles)
|
| 799 |
|
|
data = {data[113:0], cnt[3:0]};
|
| 800 |
|
|
end
|
| 801 |
15 |
mohor |
end
|
| 802 |
|
|
|
| 803 |
|
|
// Adding CRC
|
| 804 |
|
|
data = {data[104:0], crc[14:0]};
|
| 805 |
|
|
|
| 806 |
|
|
|
| 807 |
|
|
// Calculating pointer that points to the bit that will be send
|
| 808 |
19 |
mohor |
if (remote_trans_req)
|
| 809 |
|
|
begin
|
| 810 |
|
|
if(mode) // Extended format
|
| 811 |
20 |
mohor |
pointer = 52;
|
| 812 |
19 |
mohor |
else // Standard format
|
| 813 |
|
|
pointer = 32;
|
| 814 |
|
|
end
|
| 815 |
|
|
else
|
| 816 |
|
|
begin
|
| 817 |
|
|
if(mode) // Extended format
|
| 818 |
20 |
mohor |
pointer = 52 + 8 * length;
|
| 819 |
19 |
mohor |
else // Standard format
|
| 820 |
|
|
pointer = 32 + 8 * length;
|
| 821 |
|
|
end
|
| 822 |
15 |
mohor |
|
| 823 |
|
|
// This is how many bits we need to shift
|
| 824 |
|
|
total_bits = pointer;
|
| 825 |
|
|
|
| 826 |
24 |
mohor |
// Waiting until previous msg is finished before sending another one
|
| 827 |
25 |
mohor |
wait (~can_testbench.i_can_top.i_can_bsp.error_frame & ~can_testbench.i_can_top.i_can_bsp.rx_inter & ~can_testbench.i_can_top.i_can_bsp.tx_state);
|
| 828 |
|
|
arbitration_lost = 0;
|
| 829 |
15 |
mohor |
|
| 830 |
9 |
mohor |
send_bit(0); // SOF
|
| 831 |
16 |
mohor |
previous_bit = 0;
|
| 832 |
9 |
mohor |
|
| 833 |
25 |
mohor |
fork
|
| 834 |
9 |
mohor |
|
| 835 |
25 |
mohor |
begin
|
| 836 |
|
|
while (~arbitration_lost)
|
| 837 |
|
|
begin
|
| 838 |
|
|
for (cnt=0; cnt<=total_bits; cnt=cnt+1)
|
| 839 |
|
|
begin
|
| 840 |
|
|
if (stuff_cnt == 5)
|
| 841 |
|
|
begin
|
| 842 |
|
|
stuff_cnt = 1;
|
| 843 |
|
|
total_bits = total_bits + 1;
|
| 844 |
|
|
stuff = 1;
|
| 845 |
|
|
tmp = ~data[pointer+1];
|
| 846 |
|
|
send_bit(~data[pointer+1]);
|
| 847 |
|
|
previous_bit = ~data[pointer+1];
|
| 848 |
|
|
end
|
| 849 |
|
|
else
|
| 850 |
|
|
begin
|
| 851 |
|
|
if (data[pointer] == previous_bit)
|
| 852 |
|
|
stuff_cnt <= stuff_cnt + 1;
|
| 853 |
|
|
else
|
| 854 |
|
|
stuff_cnt <= 1;
|
| 855 |
|
|
|
| 856 |
|
|
stuff = 0;
|
| 857 |
|
|
tmp = data[pointer];
|
| 858 |
|
|
send_bit(data[pointer]);
|
| 859 |
|
|
previous_bit = data[pointer];
|
| 860 |
|
|
pointer = pointer - 1;
|
| 861 |
|
|
end
|
| 862 |
|
|
if (arbitration_lost)
|
| 863 |
|
|
cnt=total_bits+1; // Exit the for loop
|
| 864 |
|
|
end
|
| 865 |
|
|
arbitration_lost = 1; // At the end we exit the while loop
|
| 866 |
|
|
|
| 867 |
|
|
// Nothing send after the data (just recessive bit)
|
| 868 |
|
|
repeat (13) send_bit(1); // CRC delimiter + ack + ack delimiter + EOF + intermission= 1 + 1 + 1 + 7 + 3
|
| 869 |
|
|
end
|
| 870 |
|
|
end
|
| 871 |
|
|
|
| 872 |
|
|
begin
|
| 873 |
|
|
while (~arbitration_lost)
|
| 874 |
|
|
begin
|
| 875 |
|
|
#1 wait (can_testbench.i_can_top.sample_point);
|
| 876 |
|
|
if (mode)
|
| 877 |
|
|
begin
|
| 878 |
|
|
if (cnt<32 & tmp & (~rx_and_tx))
|
| 879 |
|
|
begin
|
| 880 |
|
|
arbitration_lost = 1;
|
| 881 |
|
|
rx = 1; // Only recessive is send from now on.
|
| 882 |
|
|
end
|
| 883 |
|
|
end
|
| 884 |
|
|
else
|
| 885 |
|
|
begin
|
| 886 |
|
|
if (cnt<12 & tmp & (~rx_and_tx))
|
| 887 |
|
|
begin
|
| 888 |
|
|
arbitration_lost = 1;
|
| 889 |
|
|
rx = 1; // Only recessive is send from now on.
|
| 890 |
|
|
end
|
| 891 |
|
|
end
|
| 892 |
|
|
end
|
| 893 |
|
|
end
|
| 894 |
|
|
|
| 895 |
|
|
join
|
| 896 |
|
|
|
| 897 |
8 |
mohor |
end
|
| 898 |
|
|
endtask
|
| 899 |
|
|
|
| 900 |
|
|
|
| 901 |
16 |
mohor |
|
| 902 |
11 |
mohor |
// State machine monitor (btl)
|
| 903 |
7 |
mohor |
always @ (posedge clk)
|
| 904 |
|
|
begin
|
| 905 |
|
|
if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
|
| 906 |
|
|
can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
|
| 907 |
10 |
mohor |
begin
|
| 908 |
|
|
$display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);
|
| 909 |
|
|
#1000;
|
| 910 |
|
|
$stop;
|
| 911 |
|
|
end
|
| 912 |
7 |
mohor |
|
| 913 |
|
|
if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
|
| 914 |
|
|
can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
|
| 915 |
10 |
mohor |
begin
|
| 916 |
|
|
$display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);
|
| 917 |
|
|
#1000;
|
| 918 |
|
|
$stop;
|
| 919 |
|
|
end
|
| 920 |
7 |
mohor |
end
|
| 921 |
|
|
|
| 922 |
10 |
mohor |
/* stuff_error monitor (bsp)
|
| 923 |
|
|
always @ (posedge clk)
|
| 924 |
|
|
begin
|
| 925 |
|
|
if(can_testbench.i_can_top.i_can_bsp.stuff_error)
|
| 926 |
|
|
begin
|
| 927 |
|
|
$display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);
|
| 928 |
|
|
$stop; After everything is finished add another condition (something like & (~idle)) and enable stop
|
| 929 |
|
|
end
|
| 930 |
|
|
end
|
| 931 |
|
|
*/
|
| 932 |
|
|
|
| 933 |
18 |
mohor |
//
|
| 934 |
16 |
mohor |
// CRC monitor (used until proper CRC generation is used in testbench
|
| 935 |
|
|
always @ (posedge clk)
|
| 936 |
|
|
begin
|
| 937 |
|
|
if (can_testbench.i_can_top.i_can_bsp.crc_error)
|
| 938 |
|
|
$display("Calculated crc = 0x%0x, crc_in = 0x%0x", can_testbench.i_can_top.i_can_bsp.calculated_crc, can_testbench.i_can_top.i_can_bsp.crc_in);
|
| 939 |
|
|
end
|
| 940 |
18 |
mohor |
//
|
| 941 |
10 |
mohor |
|
| 942 |
16 |
mohor |
|
| 943 |
|
|
|
| 944 |
|
|
|
| 945 |
|
|
/*
|
| 946 |
|
|
// overrun monitor
|
| 947 |
|
|
always @ (posedge clk)
|
| 948 |
|
|
begin
|
| 949 |
|
|
if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr & can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_full)
|
| 950 |
|
|
$display("(%0t)overrun", $time);
|
| 951 |
|
|
end
|
| 952 |
|
|
*/
|
| 953 |
|
|
|
| 954 |
|
|
|
| 955 |
22 |
mohor |
// form error monitor
|
| 956 |
|
|
always @ (posedge clk)
|
| 957 |
|
|
begin
|
| 958 |
|
|
if (can_testbench.i_can_top.i_can_bsp.form_error)
|
| 959 |
|
|
$display("\n\n(%0t) ERROR: form_error\n\n", $time);
|
| 960 |
|
|
end
|
| 961 |
|
|
//
|
| 962 |
|
|
|
| 963 |
|
|
|
| 964 |
2 |
mohor |
endmodule
|
| 965 |
16 |
mohor |
|
