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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_testbench.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2002/12/26 16:00:29  mohor
// Testbench define file added. Clock divider register added.
//
// Revision 1.4  2002/12/26 01:33:01  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:12  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:16:54  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
`include "can_testbench_defines.v"
 
module can_testbench();
 
 
 
parameter Tp = 1;
parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
 
 
 
reg         clk;
reg         rst;
reg   [7:0] data_in;
wire  [7:0] data_out;
reg         cs, rw;
reg   [7:0] addr;
reg         rx;
reg         idle;
integer     start_tb;
 
/* Instantiate can_top module */
can_top i_can_top
(
  .clk(clk),
  .rst(rst),
  .data_in(data_in),
  .data_out(data_out),
  .cs(cs),
  .rw(rw),
  .addr(addr),
  .rx(rx),
  .idle(idle)
);
 
 
// Generate clock signal 24 MHz
initial
begin
  clk=0;
  forever #20 clk = ~clk;
end
 
initial
begin
  start_tb = 0;
  data_in = 'hz;
  cs = 0;
  rw = 'hz;
  addr = 'hz;
  rx = 1;
  rst = 1;
  idle = 1;
  #200 rst = 0;
  #200 start_tb = 1;
end
 
 
// Main testbench
initial
begin
  wait(start_tb);
 
  /* Set bus timing register 0 */
  write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
 
  /* Set bus timing register 1 */
  write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
 
  #10;
  repeat (1000) @ (posedge clk);
 
//  test_synchronization;
  repeat (2) @ (posedge clk);   // So we are not synchronized to anything
  send_frame(1, 29'h12345678, 1); // mode, id, length
 
 
  repeat (50000) @ (posedge clk);
  $display("CAN Testbench finished.");
  $stop;
end
 
 
 
 
task write_register;
  input [7:0] reg_addr;
  input [7:0] reg_data;
 
  begin
    @ (posedge clk);
    #1;
    addr = reg_addr;
    data_in = reg_data;
    cs = 1;
    rw = 0;
    @ (posedge clk);
    #1;
    addr = 'hz;
    data_in = 'hz;
    cs = 0;
    rw = 'hz;
  end
endtask
 
 
task test_synchronization;
  begin
    // Hard synchronization
    repeat (2) @ (posedge clk);   // So we are not synchronized to anything
    #1 rx=0;
    repeat (2*BRP) @ (posedge clk);
    #1 idle = 0;
    repeat (8*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
 
    // Resynchronization on time
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
    idle = 0;
    repeat (10*BRP) @ (posedge clk);
 
    // Resynchronization late
    repeat (BRP) @ (posedge clk);
    repeat (BRP) @ (posedge clk);
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
    idle = 0;
 
    // Resynchronization early
    repeat (8*BRP) @ (posedge clk);   // two frames too early
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
    idle = 0;
    repeat (10*BRP) @ (posedge clk);
  end
endtask
 
 
task send_bit;
  input bit;
  integer cnt;
  begin
    #1 rx=bit;
    repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
    idle=0;
  end
endtask
 
 
task send_frame;
  input mode;
  input [28:0] id;
  input  [3:0] length;
  integer cnt;
 
  reg [28:0] data;
  reg  [3:0] len;
  begin
 
    data = id;
    len  = length;
 
    send_bit(0);                        // SOF
 
    if(mode)      // Extended format
      begin
        for (cnt=0; cnt<11; cnt=cnt+1)  // 11 bit ID
          begin
            send_bit(data[28]);
            data=data<<1;
          end
        send_bit(1);                    // SRR
        send_bit(1);                    // IDE
 
        for (cnt=11; cnt<29; cnt=cnt+1)  // 18 bit ID
          begin
            send_bit(data[28]);
            data=data<<1;
          end
 
        send_bit(0);                    // RTR
        send_bit(0);                    // r1 (reserved 1)
        send_bit(0);                    // r0 (reserved 0)
 
        for (cnt=0; cnt<4; cnt=cnt+1)   // DLC (length)
          begin
            send_bit(len[3]);
            len=len<<1;
          end
      end
    else                  // Standard format
      begin
        for (cnt=0; cnt<11; cnt=cnt+1)  // 11 bit ID
          begin
            send_bit(data[10]);
            data=data<<1;
          end
        send_bit(0);                    // RTR
        send_bit(0);                    // IDE
        send_bit(0);                    // r0 (reserved 0)
 
        for (cnt=0; cnt<4; cnt=cnt+1)   // DLC (length)
          begin
            send_bit(len[3]);
            len=len<<1;
          end
      end                 // End header
 
 
      for (cnt=0; cnt<(8*length); cnt=cnt+4)  // data
        begin
          send_bit(cnt[3]);
          send_bit(cnt[2]);
          send_bit(cnt[1]);
          send_bit(cnt[0]);
        end
 
 
      // Nothing send after the data (just recessive bit)
      send_bit(1);
 
 
 
  end
endtask
 
 
/* State machine monitor (btl) */
always @ (posedge clk)
begin
  if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
     can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
     $display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance", $time);
 
  if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
     can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
     $display("(%0t) ERROR multiple sync, seg1 or seg2 occurance", $time);
end
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_testbench.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	9	mohor	`// Revision 1.5 2002/12/26 16:00:29 mohor`
49			`// Testbench define file added. Clock divider register added.`
50			`//`
51	8	mohor	`// Revision 1.4 2002/12/26 01:33:01 mohor`
52			`// Tripple sampling supported.`
53			`//`
54	7	mohor	`// Revision 1.3 2002/12/25 23:44:12 mohor`
55			`// Commented lines removed.`
56			`//`
57	6	mohor	`// Revision 1.2 2002/12/25 14:16:54 mohor`
58			`// Synchronization working.`
59			`//`
60	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
61			`// Initial`
62	2	mohor	`//`
63			`//`
64	5	mohor	`//`
65	2	mohor
66			`// synopsys translate_off`
67			`include "timescale.v"
68			`// synopsys translate_on`
69			`include "can_defines.v"
70	8	mohor	`include "can_testbench_defines.v"
71	2	mohor
72			`module can_testbench();`
73
74
75
76			`parameter Tp = 1;`
77	8	mohor	parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
78	2	mohor
79
80
81			`reg clk;`
82			`reg rst;`
83			`reg [7:0] data_in;`
84			`wire [7:0] data_out;`
85			`reg cs, rw;`
86			`reg [7:0] addr;`
87			`reg rx;`
88			`reg idle;`
89			`integer start_tb;`
90
91			`/* Instantiate can_top module */`
92			`can_top i_can_top`
93			`(`
94			`.clk(clk),`
95			`.rst(rst),`
96			`.data_in(data_in),`
97			`.data_out(data_out),`
98			`.cs(cs),`
99			`.rw(rw),`
100			`.addr(addr),`
101			`.rx(rx),`
102			`.idle(idle)`
103			`);`
104
105
106			`// Generate clock signal 24 MHz`
107			`initial`
108			`begin`
109			`clk=0;`
110			`forever #20 clk = ~clk;`
111			`end`
112
113			`initial`
114			`begin`
115			`start_tb = 0;`
116			`data_in = 'hz;`
117			`cs = 0;`
118			`rw = 'hz;`
119			`addr = 'hz;`
120			`rx = 1;`
121			`rst = 1;`
122	5	mohor	`idle = 1;`
123	2	mohor	`#200 rst = 0;`
124			`#200 start_tb = 1;`
125			`end`
126
127
128			`// Main testbench`
129			`initial`
130			`begin`
131			`wait(start_tb);`
132
133			`/* Set bus timing register 0 */`
134	8	mohor	write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
135
136	2	mohor	`/* Set bus timing register 1 */`
137	8	mohor	write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
138	2	mohor
139			`#10;`
140			`repeat (1000) @ (posedge clk);`
141
142	9	mohor	`// test_synchronization;`
143			`repeat (2) @ (posedge clk); // So we are not synchronized to anything`
144			`send_frame(1, 29'h12345678, 1); // mode, id, length`
145
146	5	mohor
147	2	mohor	`repeat (50000) @ (posedge clk);`
148			`$display("CAN Testbench finished.");`
149			`$stop;`
150			`end`
151
152
153
154
155			`task write_register;`
156			`input [7:0] reg_addr;`
157			`input [7:0] reg_data;`
158
159			`begin`
160			`@ (posedge clk);`
161			`#1;`
162			`addr = reg_addr;`
163			`data_in = reg_data;`
164			`cs = 1;`
165			`rw = 0;`
166			`@ (posedge clk);`
167			`#1;`
168			`addr = 'hz;`
169			`data_in = 'hz;`
170			`cs = 0;`
171			`rw = 'hz;`
172			`end`
173			`endtask`
174	7	mohor
175
176	8	mohor	`task test_synchronization;`
177			`begin`
178			`// Hard synchronization`
179			`repeat (2) @ (posedge clk); // So we are not synchronized to anything`
180			`#1 rx=0;`
181			`repeat (2*BRP) @ (posedge clk);`
182			`#1 idle = 0;`
183			`repeat (8*BRP) @ (posedge clk);`
184			`#1 rx=1;`
185			`repeat (10*BRP) @ (posedge clk);`
186
187			`// Resynchronization on time`
188			`#1 rx=0;`
189			`repeat (10*BRP) @ (posedge clk);`
190			`#1 rx=1;`
191			`idle = 0;`
192			`repeat (10*BRP) @ (posedge clk);`
193
194			`// Resynchronization late`
195			`repeat (BRP) @ (posedge clk);`
196			`repeat (BRP) @ (posedge clk);`
197			`#1 rx=0;`
198			`repeat (10*BRP) @ (posedge clk);`
199			`#1 rx=1;`
200			`idle = 0;`
201
202			`// Resynchronization early`
203			`repeat (8*BRP) @ (posedge clk); // two frames too early`
204			`#1 rx=0;`
205			`repeat (10*BRP) @ (posedge clk);`
206			`#1 rx=1;`
207			`idle = 0;`
208			`repeat (10*BRP) @ (posedge clk);`
209			`end`
210			`endtask`
211	7	mohor
212	8	mohor
213	9	mohor	`task send_bit;`
214			`input bit;`
215			`integer cnt;`
216			`begin`
217			`#1 rx=bit;`
218			repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
219			`idle=0;`
220			`end`
221			`endtask`
222
223
224	8	mohor	`task send_frame;`
225			`input mode;`
226	9	mohor	`input [28:0] id;`
227			`input [3:0] length;`
228			`integer cnt;`
229
230			`reg [28:0] data;`
231			`reg [3:0] len;`
232	8	mohor	`begin`
233	9	mohor
234			`data = id;`
235			`len = length;`
236
237			`send_bit(0); // SOF`
238
239			`if(mode) // Extended format`
240			`begin`
241			`for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID`
242			`begin`
243			`send_bit(data[28]);`
244			`data=data<<1;`
245			`end`
246			`send_bit(1); // SRR`
247			`send_bit(1); // IDE`
248
249			`for (cnt=11; cnt<29; cnt=cnt+1) // 18 bit ID`
250			`begin`
251			`send_bit(data[28]);`
252			`data=data<<1;`
253			`end`
254
255			`send_bit(0); // RTR`
256			`send_bit(0); // r1 (reserved 1)`
257			`send_bit(0); // r0 (reserved 0)`
258
259			`for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)`
260			`begin`
261			`send_bit(len[3]);`
262			`len=len<<1;`
263			`end`
264			`end`
265			`else // Standard format`
266			`begin`
267			`for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID`
268			`begin`
269			`send_bit(data[10]);`
270			`data=data<<1;`
271			`end`
272			`send_bit(0); // RTR`
273			`send_bit(0); // IDE`
274			`send_bit(0); // r0 (reserved 0)`
275
276			`for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)`
277			`begin`
278			`send_bit(len[3]);`
279			`len=len<<1;`
280			`end`
281			`end // End header`
282
283
284			`for (cnt=0; cnt<(8*length); cnt=cnt+4) // data`
285			`begin`
286			`send_bit(cnt[3]);`
287			`send_bit(cnt[2]);`
288			`send_bit(cnt[1]);`
289			`send_bit(cnt[0]);`
290			`end`
291
292
293			`// Nothing send after the data (just recessive bit)`
294			`send_bit(1);`
295
296
297
298	8	mohor	`end`
299			`endtask`
300
301
302	7	mohor	`/* State machine monitor (btl) */`
303			`always @ (posedge clk)`
304			`begin`
305			`if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 \| can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 \|`
306			`can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)`
307			`$display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance", $time);`
308
309			`if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 \| can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 \|`
310			`can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)`
311			`$display("(%0t) ERROR multiple sync, seg1 or seg2 occurance", $time);`
312			`end`
313
314	2	mohor	`endmodule`

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