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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_bsp.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12  2003/01/15 21:05:11  mohor
// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
//
// Revision 1.11  2003/01/15 14:40:23  mohor
// RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.
//
// Revision 1.10  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.
//
// Revision 1.9  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.8  2003/01/10 17:51:33  mohor
// Temporary version (backup).
//
// Revision 1.7  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.6  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.5  2003/01/08 13:30:31  mohor
// Temp version.
//
// Revision 1.4  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.3  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.2  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_bsp
(
  clk,
  rst,
 
  sample_point,
  sampled_bit,
  sampled_bit_q,
  hard_sync,
  resync,
 
  addr,
  data_out,
 
 
  /* Mode register */
  reset_mode,
  acceptance_filter_mode,
 
  /* Command register */
  release_buffer,
 
  /* Clock Divider register */
  extended_mode,
 
  rx_idle,
 
  /* This section is for BASIC and EXTENDED mode */
  /* Acceptance code register */
  acceptance_code_0,
 
  /* Acceptance mask register */
  acceptance_mask_0,
  /* End: This section is for BASIC and EXTENDED mode */
 
  /* This section is for EXTENDED mode */
  /* Acceptance code register */
  acceptance_code_1,
  acceptance_code_2,
  acceptance_code_3,
 
  /* Acceptance mask register */
  acceptance_mask_1,
  acceptance_mask_2,
  acceptance_mask_3,
  /* End: This section is for EXTENDED mode */
 
  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
  tx_data_0,
  tx_data_1,
  tx_data_2,
  tx_data_3,
  tx_data_4,
  tx_data_5,
  tx_data_6,
  tx_data_7,
  tx_data_8,
  tx_data_9,
  tx_data_10,
  tx_data_11,
  tx_data_12
  /* End: Tx data registers */
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         sample_point;
input         sampled_bit;
input         sampled_bit_q;
input         hard_sync;
input         resync;
input   [7:0] addr;
output  [7:0] data_out;
 
 
input         reset_mode;
input         acceptance_filter_mode;
input         extended_mode;
 
/* Command register */
input         release_buffer;
 
output        rx_idle;
 
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
input   [7:0] acceptance_code_0;
 
/* Acceptance mask register */
input   [7:0] acceptance_mask_0;
 
/* End: This section is for BASIC and EXTENDED mode */
 
 
/* This section is for EXTENDED mode */
/* Acceptance code register */
input   [7:0] acceptance_code_1;
input   [7:0] acceptance_code_2;
input   [7:0] acceptance_code_3;
 
/* Acceptance mask register */
input   [7:0] acceptance_mask_1;
input   [7:0] acceptance_mask_2;
input   [7:0] acceptance_mask_3;
/* End: This section is for EXTENDED mode */
 
  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
input   [7:0] tx_data_0;
input   [7:0] tx_data_1;
input   [7:0] tx_data_2;
input   [7:0] tx_data_3;
input   [7:0] tx_data_4;
input   [7:0] tx_data_5;
input   [7:0] tx_data_6;
input   [7:0] tx_data_7;
input   [7:0] tx_data_8;
input   [7:0] tx_data_9;
input   [7:0] tx_data_10;
input   [7:0] tx_data_11;
input   [7:0] tx_data_12;
  /* End: Tx data registers */
 
 
reg           reset_mode_q;
reg     [5:0] bit_cnt;
 
reg     [3:0] data_len;
reg    [28:0] id;
reg     [2:0] bit_stuff_cnt;
reg           stuff_error;
 
wire          bit_de_stuff;
 
 
/* Rx state machine */
wire          go_rx_idle;
wire          go_rx_id1;
wire          go_rx_rtr1;
wire          go_rx_ide;
wire          go_rx_id2;
wire          go_rx_rtr2;
wire          go_rx_r1;
wire          go_rx_r0;
wire          go_rx_dlc;
wire          go_rx_data;
wire          go_rx_crc;
wire          go_rx_crc_lim;
wire          go_rx_ack;
wire          go_rx_ack_lim;
wire          go_rx_eof;
 
wire          go_crc_enable;
wire          rst_crc_enable;
 
wire          bit_de_stuff_set;
wire          bit_de_stuff_reset;
 
reg           rx_idle;
reg           rx_id1;
reg           rx_rtr1;
reg           rx_ide;
reg           rx_id2;
reg           rx_rtr2;
reg           rx_r1;
reg           rx_r0;
reg           rx_dlc;
reg           rx_data;
reg           rx_crc;
reg           rx_crc_lim;
reg           rx_ack;
reg           rx_ack_lim;
reg           rx_eof;
 
reg           rtr1;
reg           ide;
reg           rtr2;
reg    [14:0] crc_in;
 
reg           crc_enable;
 
reg     [2:0] eof_cnt;
wire   [14:0] calculated_crc;
wire          remote_rq;
wire [3:0]    limited_data_len;
 
assign go_rx_idle     =                   sample_point &  rx_eof  & (eof_cnt == 6);
assign go_rx_id1      =                   sample_point &  rx_idle & (~sampled_bit);
assign go_rx_rtr1     = (~bit_de_stuff) & sample_point &  rx_id1  & (bit_cnt == 10);
assign go_rx_ide      = (~bit_de_stuff) & sample_point &  rx_rtr1;
assign go_rx_id2      = (~bit_de_stuff) & sample_point &  rx_ide  &   sampled_bit;
assign go_rx_rtr2     = (~bit_de_stuff) & sample_point &  rx_id2  & (bit_cnt == 17);
assign go_rx_r1       = (~bit_de_stuff) & sample_point &  rx_rtr2;
assign go_rx_r0       = (~bit_de_stuff) & sample_point & (rx_ide  & (~sampled_bit) | rx_r1);
assign go_rx_dlc      = (~bit_de_stuff) & sample_point &  rx_r0;
assign go_rx_data     = (~bit_de_stuff) & sample_point &  rx_dlc  & (bit_cnt == 3) &  (sampled_bit   |   (|data_len[2:0])) & (~remote_rq);
assign go_rx_crc      = (~bit_de_stuff) & sample_point & (rx_dlc  & (bit_cnt == 3) & ((~sampled_bit) & (~(|data_len[2:0])) | remote_rq) |
                                                          rx_data & (bit_cnt == ((limited_data_len<<3) - 1'b1)));
assign go_rx_crc_lim  = (~bit_de_stuff) & sample_point &  rx_crc  & (bit_cnt == 14);
assign go_rx_ack      =                   sample_point &  rx_crc_lim;
assign go_rx_ack_lim  =                   sample_point &  rx_ack;
assign go_rx_eof      =                   sample_point &  rx_ack_lim  | (~reset_mode) & reset_mode_q;
 
assign go_crc_enable  = hard_sync;
assign rst_crc_enable = go_rx_crc;
 
assign bit_de_stuff_set   = go_rx_id1;
assign bit_de_stuff_reset = go_rx_crc_lim;
 
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
assign limited_data_len = (data_len < 8)? data_len : 4'h8;
 
 
// Rx idle state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_idle <= 1'b1;
  else if (reset_mode | go_rx_id1)
    rx_idle <=#Tp 1'b0;
  else if (go_rx_idle)
    rx_idle <=#Tp 1'b1;
end
 
 
// Rx id1 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_id1 <= 1'b0;
  else if (reset_mode | go_rx_rtr1)
    rx_id1 <=#Tp 1'b0;
  else if (go_rx_id1)
    rx_id1 <=#Tp 1'b1;
end
 
 
// Rx rtr1 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_rtr1 <= 1'b0;
  else if (reset_mode | go_rx_ide)
    rx_rtr1 <=#Tp 1'b0;
  else if (go_rx_rtr1)
    rx_rtr1 <=#Tp 1'b1;
end
 
 
// Rx ide state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ide <= 1'b0;
  else if (reset_mode | go_rx_r0 | go_rx_id2)
    rx_ide <=#Tp 1'b0;
  else if (go_rx_ide)
    rx_ide <=#Tp 1'b1;
end
 
 
// Rx id2 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_id2 <= 1'b0;
  else if (reset_mode | go_rx_rtr2)
    rx_id2 <=#Tp 1'b0;
  else if (go_rx_id2)
    rx_id2 <=#Tp 1'b1;
end
 
 
// Rx rtr2 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_rtr2 <= 1'b0;
  else if (reset_mode | go_rx_r1)
    rx_rtr2 <=#Tp 1'b0;
  else if (go_rx_rtr2)
    rx_rtr2 <=#Tp 1'b1;
end
 
 
// Rx r0 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_r1 <= 1'b0;
  else if (reset_mode | go_rx_r0)
    rx_r1 <=#Tp 1'b0;
  else if (go_rx_r1)
    rx_r1 <=#Tp 1'b1;
end
 
 
// Rx r0 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_r0 <= 1'b0;
  else if (reset_mode | go_rx_dlc)
    rx_r0 <=#Tp 1'b0;
  else if (go_rx_r0)
    rx_r0 <=#Tp 1'b1;
end
 
 
// Rx dlc state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_dlc <= 1'b0;
  else if (reset_mode | go_rx_data | go_rx_crc)
    rx_dlc <=#Tp 1'b0;
  else if (go_rx_dlc)
    rx_dlc <=#Tp 1'b1;
end
 
 
// Rx data state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_data <= 1'b0;
  else if (reset_mode | go_rx_crc)
    rx_data <=#Tp 1'b0;
  else if (go_rx_data)
    rx_data <=#Tp 1'b1;
end
 
 
// Rx crc state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_crc <= 1'b0;
  else if (reset_mode | go_rx_crc_lim)
    rx_crc <=#Tp 1'b0;
  else if (go_rx_crc)
    rx_crc <=#Tp 1'b1;
end
 
 
// Rx crc delimiter state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_crc_lim <= 1'b0;
  else if (reset_mode | go_rx_ack)
    rx_crc_lim <=#Tp 1'b0;
  else if (go_rx_crc_lim)
    rx_crc_lim <=#Tp 1'b1;
end
 
 
// Rx ack state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ack <= 1'b0;
  else if (reset_mode | go_rx_ack_lim)
    rx_ack <=#Tp 1'b0;
  else if (go_rx_ack)
    rx_ack <=#Tp 1'b1;
end
 
 
// Rx ack delimiter state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ack_lim <= 1'b0;
  else if (reset_mode | go_rx_eof)
    rx_ack_lim <=#Tp 1'b0;
  else if (go_rx_ack_lim)
    rx_ack_lim <=#Tp 1'b1;
end
 
 
// Rx eof state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_eof <= 1'b0;
  else if (go_rx_idle)
    rx_eof <=#Tp 1'b0;
  else if (go_rx_eof)
    rx_eof <=#Tp 1'b1;
end
 
 
// ID register
always @ (posedge clk or posedge rst)
begin
  if (rst)
    id <= 0;
  else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
    id <=#Tp {id[27:0], sampled_bit};
end
 
 
// rtr1 bit
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rtr1 <= 0;
  else if (sample_point & rx_rtr1 & (~bit_de_stuff))
    rtr1 <=#Tp sampled_bit;
end
 
 
// rtr2 bit
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rtr2 <= 0;
  else if (sample_point & rx_rtr2 & (~bit_de_stuff))
    rtr2 <=#Tp sampled_bit;
end
 
 
// ide bit
always @ (posedge clk or posedge rst)
begin
  if (rst)
    ide <= 0;
  else if (sample_point & rx_ide & (~bit_de_stuff))
    ide <=#Tp sampled_bit;
end
 
 
// Data length
always @ (posedge clk or posedge rst)
begin
  if (rst)
    data_len <= 0;
  else if (sample_point & rx_dlc & (~bit_de_stuff))
    data_len <=#Tp {data_len[2:0], sampled_bit};
end
 
 
// Data
reg [7:0] tmp_data;
reg [7:0] tmp_fifo [0:7];
always @ (posedge clk or posedge rst)
begin
  if (rst)
    tmp_data <= 0;
  else if (sample_point & rx_data & (~bit_de_stuff))
    tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
end
 
 
reg write_data_to_tmp_fifo;
always @ (posedge clk or posedge rst)
begin
  if (rst)
    write_data_to_tmp_fifo <= 0;
  else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
    write_data_to_tmp_fifo <=#Tp 1'b1;
  else
    write_data_to_tmp_fifo <=#Tp 0;
end
 
 
reg [2:0] byte_cnt;
always @ (posedge clk or posedge rst)
begin
  if (rst)
    byte_cnt <= 0;
  else if (write_data_to_tmp_fifo)
    byte_cnt <=#Tp byte_cnt + 1;
  else if (sample_point & go_rx_crc_lim)
    byte_cnt <=#Tp 0;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (write_data_to_tmp_fifo)
    tmp_fifo[byte_cnt] <=#Tp tmp_data;
end
 
 
 
// CRC
always @ (posedge clk or posedge rst)
begin
  if (rst)
    crc_in <= 0;
  else if (sample_point & rx_crc & (~bit_de_stuff))
    crc_in <=#Tp {crc_in[13:0], sampled_bit};
end
 
 
// bit_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_cnt <= 0;
  else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc | go_rx_ack | go_rx_eof)
    bit_cnt <=#Tp 0;
  else if (sample_point & (~bit_de_stuff))
    bit_cnt <=#Tp bit_cnt + 1'b1;
end
 
 
// eof_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    eof_cnt <= 0;
  else if (sample_point)
    begin
      if (rx_eof & sampled_bit)
        eof_cnt <=#Tp eof_cnt + 1'b1;
      else
        eof_cnt <=#Tp 0;
    end
end
 
 
// Enabling bit de-stuffing
reg bit_stuff_cnt_en;
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_stuff_cnt_en <= 1'b0;
  else if (bit_de_stuff_set)
    bit_stuff_cnt_en <=#Tp 1'b1;
  else if (bit_de_stuff_reset)
    bit_stuff_cnt_en <=#Tp 1'b0;
end
 
// bit_stuff_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_stuff_cnt <= 1;
  else if (bit_de_stuff_reset)
    bit_stuff_cnt <=#Tp 1;
  else if (sample_point & bit_stuff_cnt_en)
    begin
      if (bit_stuff_cnt == 5)
        bit_stuff_cnt <=#Tp 1;
      else if (sampled_bit == sampled_bit_q)
        bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1;
      else
        bit_stuff_cnt <=#Tp 1;
    end
end
 
 
assign bit_de_stuff = bit_stuff_cnt == 5;
 
 
// stuff_error
always @ (posedge clk or posedge rst)
begin
  if (rst)
    stuff_error <= 0;
  else if (sample_point & (rx_id1) & bit_de_stuff & (sampled_bit == sampled_bit_q))   // Add other stages (data, control, etc.) !!!
    stuff_error <=#Tp 1'b1;
//  else if (reset condition)       // Add reset condition
//    stuff_error <=#Tp 0;
end
 
 
// Generating delayed reset_mode signal
always @ (posedge clk)
begin
  reset_mode_q <=#Tp reset_mode;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    crc_enable <= 1'b0;
  else if (go_crc_enable)
    crc_enable <=#Tp 1'b1;
  else if (reset_mode | rst_crc_enable)
    crc_enable <=#Tp 1'b0;
end
 
 
reg crc_error;
// CRC error generation
always @ (posedge clk or posedge rst)
begin
  if (rst)
    crc_error <= 0;
  else if (go_rx_ack)
    crc_error <=#Tp crc_in != calculated_crc;
  else if (reset_mode | rx_eof)
    crc_error <=#Tp 0;
end
 
 
 
// Instantiation of the RX CRC module
can_crc i_can_crc_rx
(
  .clk(clk),
//  .data(sampled_bit & (~rx_crc)),     // Zeros are shifted in for calculation when we are in crc stage
  .data(sampled_bit ),     // Zeros are shifted in for calculation when we are in crc stage
  .enable(crc_enable & sample_point & (~bit_de_stuff)),
  .initialize(rx_eof),
  .crc(calculated_crc)
);
 
 
 
wire          id_ok;        // If received ID matches ID set in registers
wire          no_byte0;     // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
wire          no_byte1;     // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
 
assign no_byte0 = rtr1 | (data_len<1);
assign no_byte1 = rtr1 | (data_len<2);
 
can_acf i_can_acf
(
  .clk(clk),
  .rst(rst),
 
  .id(id),
 
  /* Mode register */
  .reset_mode(reset_mode),
  .acceptance_filter_mode(acceptance_filter_mode),
 
  // Clock Divider register
  .extended_mode(extended_mode),
 
  /* This section is for BASIC and EXTENDED mode */
  /* Acceptance code register */
  .acceptance_code_0(acceptance_code_0),
 
  /* Acceptance mask register */
  .acceptance_mask_0(acceptance_mask_0),
  /* End: This section is for BASIC and EXTENDED mode */
 
  /* This section is for EXTENDED mode */
  /* Acceptance code register */
  .acceptance_code_1(acceptance_code_1),
  .acceptance_code_2(acceptance_code_2),
  .acceptance_code_3(acceptance_code_3),
 
  /* Acceptance mask register */
  .acceptance_mask_1(acceptance_mask_1),
  .acceptance_mask_2(acceptance_mask_2),
  .acceptance_mask_3(acceptance_mask_3),
  /* End: This section is for EXTENDED mode */
 
  .sample_point(sample_point),
  .go_rx_crc_lim(go_rx_crc_lim),
  .go_rx_idle(go_rx_idle),
 
  .data0(tmp_fifo[0]),
  .data1(tmp_fifo[1]),
  .rtr1(rtr1),
  .rtr2(rtr2),
  .ide(ide),
  .no_byte0(no_byte0),
  .no_byte1(no_byte1),
 
  .id_ok(id_ok)
 
);
 
 
 
reg [3:0]   data_cnt;       // Counting the data bytes that are written to FIFO
reg [2:0]   header_cnt;     // Counting header length
reg         wr_fifo;        // Write data and header to 64-byte fifo
reg [7:0]   data_for_fifo;  // Multiplexed data that is stored to 64-byte fifo
 
 
wire [2:0]  header_len;
wire        storing_header;
wire [3:0]  limited_data_len_minus1;
wire        reset_wr_fifo;
wire        no_error;
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
assign storing_header = header_cnt < header_len;
assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 8)? (data_len -1'b1) : 4'h7);   // - 1 because counter counts from 0
assign reset_wr_fifo = data_cnt == (limited_data_len_minus1 + header_len);
assign no_error = ~crc_error;
 
// Write enable signal for 64-byte rx fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_fifo <= 1'b0;
  else if (reset_wr_fifo)
    wr_fifo <=#Tp 1'b0;
  else if (go_rx_idle & id_ok & no_error)
    wr_fifo <=#Tp 1'b1;
end
 
 
// Header counter. Header length depends on the mode of operation and frame format.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    header_cnt <= 0;
  else if (reset_wr_fifo)
    header_cnt <=#Tp 0;
  else if (wr_fifo & storing_header)
    header_cnt <=#Tp header_cnt + 1;
end
 
 
// Data counter. Length of the data is limited to 8 bytes.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    data_cnt <= 0;
  else if (reset_wr_fifo)
    data_cnt <=#Tp 0;
  else if (wr_fifo)
    data_cnt <=#Tp data_cnt + 1;
end
 
 
// Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
always @ (extended_mode or ide or data_cnt or header_cnt or storing_header or id or rtr1 or rtr2 or data_len or
          tmp_fifo[0] or tmp_fifo[2] or tmp_fifo[4] or tmp_fifo[6] or
          tmp_fifo[1] or tmp_fifo[3] or tmp_fifo[5] or tmp_fifo[7])
begin
  if (storing_header)
    begin
      if (extended_mode)      // extended mode
        begin
          if (ide)              // extended format
            begin
              case (header_cnt)            // synopsys parallel_case synopsys full_case
                4'h0  : data_for_fifo <= {1'b1, rtr2, 2'h0, data_len};
                4'h1  : data_for_fifo <= id[28:21];
                4'h2  : data_for_fifo <= id[20:13];
                4'h3  : data_for_fifo <= id[12:5];
                4'h4  : data_for_fifo <= {id[4:0], 3'h0};
              endcase
            end
          else                  // standard format
            begin
              case (header_cnt)            // synopsys parallel_case synopsys full_case
                4'h0  : data_for_fifo <= {1'b0, rtr1, 2'h0, data_len};
                4'h1  : data_for_fifo <= id[10:3];
                4'h2  : data_for_fifo <= {id[2:0], 5'h0};
              endcase
            end
        end
      else                    // normal mode
        begin
          case (header_cnt)            // synopsys parallel_case synopsys full_case
            4'h0  : data_for_fifo <= id[10:3];
            4'h1  : data_for_fifo <= {id[2:0], rtr1, data_len};
          endcase
        end
    end
  else
    data_for_fifo <= tmp_fifo[data_cnt-header_len];
end
 
 
 
 
// Instantiation of the RX fifo module
can_fifo i_can_fifo
(
  .clk(clk),
  .rst(rst),
 
  .wr(wr_fifo),
 
  .data_in(data_for_fifo),
  .addr(addr),
  .data_out(data_out),
 
  .reset_mode(reset_mode),
  .release_buffer(release_buffer),
  .extended_mode(extended_mode)
 
 
);
 
 
 
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_bsp.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	21	mohor	`// Revision 1.12 2003/01/15 21:05:11 mohor`
49			`// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).`
50			`//`
51	20	mohor	`// Revision 1.11 2003/01/15 14:40:23 mohor`
52			`// RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.`
53			`//`
54	19	mohor	`// Revision 1.10 2003/01/15 13:16:47 mohor`
55			`// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.`
56			`//`
57	18	mohor	`// Revision 1.9 2003/01/14 12:19:35 mohor`
58			`// rx_fifo is now working.`
59			`//`
60	16	mohor	`// Revision 1.8 2003/01/10 17:51:33 mohor`
61			`// Temporary version (backup).`
62			`//`
63	15	mohor	`// Revision 1.7 2003/01/09 21:54:45 mohor`
64			`// rx fifo added. Not 100 % verified, yet.`
65			`//`
66	14	mohor	`// Revision 1.6 2003/01/09 14:46:58 mohor`
67			`// Temporary files (backup).`
68			`//`
69	13	mohor	`// Revision 1.5 2003/01/08 13:30:31 mohor`
70			`// Temp version.`
71			`//`
72	12	mohor	`// Revision 1.4 2003/01/08 02:10:53 mohor`
73			`// Acceptance filter added.`
74			`//`
75	11	mohor	`// Revision 1.3 2002/12/28 04:13:23 mohor`
76			`// Backup version.`
77			`//`
78	10	mohor	`// Revision 1.2 2002/12/27 00:12:52 mohor`
79			`// Header changed, testbench improved to send a frame (crc still missing).`
80			`//`
81	9	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
82			`// Initial`
83	2	mohor	`//`
84			`//`
85	9	mohor	`//`
86	2	mohor
87			`// synopsys translate_off`
88			`include "timescale.v"
89			`// synopsys translate_on`
90			`include "can_defines.v"
91
92			`module can_bsp`
93			`(`
94			`clk,`
95	10	mohor	`rst,`
96
97			`sample_point,`
98			`sampled_bit,`
99			`sampled_bit_q,`
100	11	mohor	`hard_sync,`
101			`resync,`
102
103	14	mohor	`addr,`
104			`data_out,`
105
106
107	11	mohor	`/* Mode register */`
108	10	mohor	`reset_mode,`
109	11	mohor	`acceptance_filter_mode,`
110
111	15	mohor	`/* Command register */`
112			`release_buffer,`
113
114			`/* Clock Divider register */`
115	11	mohor	`extended_mode,`
116
117			`rx_idle,`
118
119			`/* This section is for BASIC and EXTENDED mode */`
120			`/* Acceptance code register */`
121			`acceptance_code_0,`
122
123			`/* Acceptance mask register */`
124			`acceptance_mask_0,`
125			`/* End: This section is for BASIC and EXTENDED mode */`
126	10	mohor
127	11	mohor	`/* This section is for EXTENDED mode */`
128			`/* Acceptance code register */`
129			`acceptance_code_1,`
130			`acceptance_code_2,`
131			`acceptance_code_3,`
132	10	mohor
133	11	mohor	`/* Acceptance mask register */`
134			`acceptance_mask_1,`
135			`acceptance_mask_2,`
136	18	mohor	`acceptance_mask_3,`
137	11	mohor	`/* End: This section is for EXTENDED mode */`
138	10	mohor
139	18	mohor	`/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */`
140			`tx_data_0,`
141			`tx_data_1,`
142			`tx_data_2,`
143			`tx_data_3,`
144			`tx_data_4,`
145			`tx_data_5,`
146			`tx_data_6,`
147			`tx_data_7,`
148			`tx_data_8,`
149			`tx_data_9,`
150			`tx_data_10,`
151			`tx_data_11,`
152			`tx_data_12`
153			`/* End: Tx data registers */`
154
155	2	mohor	`);`
156
157			`parameter Tp = 1;`
158
159	10	mohor	`input clk;`
160			`input rst;`
161			`input sample_point;`
162			`input sampled_bit;`
163			`input sampled_bit_q;`
164	11	mohor	`input hard_sync;`
165			`input resync;`
166	14	mohor	`input [7:0] addr;`
167			`output [7:0] data_out;`
168	11	mohor
169	14	mohor
170	10	mohor	`input reset_mode;`
171	11	mohor	`input acceptance_filter_mode;`
172			`input extended_mode;`
173	2	mohor
174	15	mohor	`/* Command register */`
175			`input release_buffer;`
176	11	mohor
177	10	mohor	`output rx_idle;`
178	2	mohor
179	11	mohor	`/* This section is for BASIC and EXTENDED mode */`
180			`/* Acceptance code register */`
181			`input [7:0] acceptance_code_0;`
182
183			`/* Acceptance mask register */`
184			`input [7:0] acceptance_mask_0;`
185
186			`/* End: This section is for BASIC and EXTENDED mode */`
187
188
189			`/* This section is for EXTENDED mode */`
190			`/* Acceptance code register */`
191			`input [7:0] acceptance_code_1;`
192			`input [7:0] acceptance_code_2;`
193			`input [7:0] acceptance_code_3;`
194
195			`/* Acceptance mask register */`
196			`input [7:0] acceptance_mask_1;`
197			`input [7:0] acceptance_mask_2;`
198			`input [7:0] acceptance_mask_3;`
199			`/* End: This section is for EXTENDED mode */`
200
201	18	mohor	`/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */`
202			`input [7:0] tx_data_0;`
203			`input [7:0] tx_data_1;`
204			`input [7:0] tx_data_2;`
205			`input [7:0] tx_data_3;`
206			`input [7:0] tx_data_4;`
207			`input [7:0] tx_data_5;`
208			`input [7:0] tx_data_6;`
209			`input [7:0] tx_data_7;`
210			`input [7:0] tx_data_8;`
211			`input [7:0] tx_data_9;`
212			`input [7:0] tx_data_10;`
213			`input [7:0] tx_data_11;`
214			`input [7:0] tx_data_12;`
215			`/* End: Tx data registers */`
216	11	mohor
217
218	10	mohor	`reg reset_mode_q;`
219			`reg [5:0] bit_cnt;`
220	2	mohor
221	10	mohor	`reg [3:0] data_len;`
222			`reg [28:0] id;`
223			`reg [2:0] bit_stuff_cnt;`
224			`reg stuff_error;`
225
226			`wire bit_de_stuff;`
227
228
229			`/* Rx state machine */`
230			`wire go_rx_idle;`
231			`wire go_rx_id1;`
232			`wire go_rx_rtr1;`
233			`wire go_rx_ide;`
234			`wire go_rx_id2;`
235			`wire go_rx_rtr2;`
236			`wire go_rx_r1;`
237			`wire go_rx_r0;`
238			`wire go_rx_dlc;`
239			`wire go_rx_data;`
240			`wire go_rx_crc;`
241	11	mohor	`wire go_rx_crc_lim;`
242	10	mohor	`wire go_rx_ack;`
243	11	mohor	`wire go_rx_ack_lim;`
244	10	mohor	`wire go_rx_eof;`
245
246	11	mohor	`wire go_crc_enable;`
247			`wire rst_crc_enable;`
248
249			`wire bit_de_stuff_set;`
250			`wire bit_de_stuff_reset;`
251
252	10	mohor	`reg rx_idle;`
253			`reg rx_id1;`
254			`reg rx_rtr1;`
255			`reg rx_ide;`
256			`reg rx_id2;`
257			`reg rx_rtr2;`
258			`reg rx_r1;`
259			`reg rx_r0;`
260			`reg rx_dlc;`
261			`reg rx_data;`
262			`reg rx_crc;`
263	11	mohor	`reg rx_crc_lim;`
264	10	mohor	`reg rx_ack;`
265	11	mohor	`reg rx_ack_lim;`
266	10	mohor	`reg rx_eof;`
267
268	19	mohor	`reg rtr1;`
269			`reg ide;`
270			`reg rtr2;`
271			`reg [14:0] crc_in;`
272
273	11	mohor	`reg crc_enable;`
274
275	10	mohor	`reg [2:0] eof_cnt;`
276	11	mohor	`wire [14:0] calculated_crc;`
277	19	mohor	`wire remote_rq;`
278			`wire [3:0] limited_data_len;`
279	10	mohor
280	11	mohor	`assign go_rx_idle = sample_point & rx_eof & (eof_cnt == 6);`
281			`assign go_rx_id1 = sample_point & rx_idle & (~sampled_bit);`
282			`assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt == 10);`
283			`assign go_rx_ide = (~bit_de_stuff) & sample_point & rx_rtr1;`
284			`assign go_rx_id2 = (~bit_de_stuff) & sample_point & rx_ide & sampled_bit;`
285			`assign go_rx_rtr2 = (~bit_de_stuff) & sample_point & rx_id2 & (bit_cnt == 17);`
286			`assign go_rx_r1 = (~bit_de_stuff) & sample_point & rx_rtr2;`
287			`assign go_rx_r0 = (~bit_de_stuff) & sample_point & (rx_ide & (~sampled_bit) \| rx_r1);`
288			`assign go_rx_dlc = (~bit_de_stuff) & sample_point & rx_r0;`
289	19	mohor	`assign go_rx_data = (~bit_de_stuff) & sample_point & rx_dlc & (bit_cnt == 3) & (sampled_bit \| (\|data_len[2:0])) & (~remote_rq);`
290			`assign go_rx_crc = (~bit_de_stuff) & sample_point & (rx_dlc & (bit_cnt == 3) & ((~sampled_bit) & (~(\|data_len[2:0])) \| remote_rq) \|`
291			`rx_data & (bit_cnt == ((limited_data_len<<3) - 1'b1)));`
292	20	mohor	`assign go_rx_crc_lim = (~bit_de_stuff) & sample_point & rx_crc & (bit_cnt == 14);`
293	11	mohor	`assign go_rx_ack = sample_point & rx_crc_lim;`
294			`assign go_rx_ack_lim = sample_point & rx_ack;`
295			`assign go_rx_eof = sample_point & rx_ack_lim \| (~reset_mode) & reset_mode_q;`
296	10	mohor
297	11	mohor	`assign go_crc_enable = hard_sync;`
298			`assign rst_crc_enable = go_rx_crc;`
299	10	mohor
300	11	mohor	`assign bit_de_stuff_set = go_rx_id1;`
301			`assign bit_de_stuff_reset = go_rx_crc_lim;`
302
303	19	mohor	`assign remote_rq = ((~ide) & rtr1) \| (ide & rtr2);`
304			`assign limited_data_len = (data_len < 8)? data_len : 4'h8;`
305	11	mohor
306	19	mohor
307	10	mohor	`// Rx idle state`
308			`always @ (posedge clk or posedge rst)`
309			`begin`
310			`if (rst)`
311			`rx_idle <= 1'b1;`
312			`else if (reset_mode \| go_rx_id1)`
313			`rx_idle <=#Tp 1'b0;`
314			`else if (go_rx_idle)`
315			`rx_idle <=#Tp 1'b1;`
316			`end`
317
318
319			`// Rx id1 state`
320			`always @ (posedge clk or posedge rst)`
321			`begin`
322			`if (rst)`
323			`rx_id1 <= 1'b0;`
324			`else if (reset_mode \| go_rx_rtr1)`
325			`rx_id1 <=#Tp 1'b0;`
326			`else if (go_rx_id1)`
327			`rx_id1 <=#Tp 1'b1;`
328			`end`
329
330
331			`// Rx rtr1 state`
332			`always @ (posedge clk or posedge rst)`
333			`begin`
334			`if (rst)`
335			`rx_rtr1 <= 1'b0;`
336			`else if (reset_mode \| go_rx_ide)`
337			`rx_rtr1 <=#Tp 1'b0;`
338			`else if (go_rx_rtr1)`
339			`rx_rtr1 <=#Tp 1'b1;`
340			`end`
341
342
343			`// Rx ide state`
344			`always @ (posedge clk or posedge rst)`
345			`begin`
346			`if (rst)`
347			`rx_ide <= 1'b0;`
348			`else if (reset_mode \| go_rx_r0 \| go_rx_id2)`
349			`rx_ide <=#Tp 1'b0;`
350			`else if (go_rx_ide)`
351			`rx_ide <=#Tp 1'b1;`
352			`end`
353
354
355			`// Rx id2 state`
356			`always @ (posedge clk or posedge rst)`
357			`begin`
358			`if (rst)`
359			`rx_id2 <= 1'b0;`
360			`else if (reset_mode \| go_rx_rtr2)`
361			`rx_id2 <=#Tp 1'b0;`
362			`else if (go_rx_id2)`
363			`rx_id2 <=#Tp 1'b1;`
364			`end`
365
366
367			`// Rx rtr2 state`
368			`always @ (posedge clk or posedge rst)`
369			`begin`
370			`if (rst)`
371			`rx_rtr2 <= 1'b0;`
372			`else if (reset_mode \| go_rx_r1)`
373			`rx_rtr2 <=#Tp 1'b0;`
374			`else if (go_rx_rtr2)`
375			`rx_rtr2 <=#Tp 1'b1;`
376			`end`
377
378
379			`// Rx r0 state`
380			`always @ (posedge clk or posedge rst)`
381			`begin`
382			`if (rst)`
383			`rx_r1 <= 1'b0;`
384			`else if (reset_mode \| go_rx_r0)`
385			`rx_r1 <=#Tp 1'b0;`
386			`else if (go_rx_r1)`
387			`rx_r1 <=#Tp 1'b1;`
388			`end`
389
390
391			`// Rx r0 state`
392			`always @ (posedge clk or posedge rst)`
393			`begin`
394			`if (rst)`
395			`rx_r0 <= 1'b0;`
396			`else if (reset_mode \| go_rx_dlc)`
397			`rx_r0 <=#Tp 1'b0;`
398			`else if (go_rx_r0)`
399			`rx_r0 <=#Tp 1'b1;`
400			`end`
401
402
403			`// Rx dlc state`
404			`always @ (posedge clk or posedge rst)`
405			`begin`
406			`if (rst)`
407			`rx_dlc <= 1'b0;`
408			`else if (reset_mode \| go_rx_data \| go_rx_crc)`
409			`rx_dlc <=#Tp 1'b0;`
410			`else if (go_rx_dlc)`
411			`rx_dlc <=#Tp 1'b1;`
412			`end`
413
414
415			`// Rx data state`
416			`always @ (posedge clk or posedge rst)`
417			`begin`
418			`if (rst)`
419			`rx_data <= 1'b0;`
420			`else if (reset_mode \| go_rx_crc)`
421			`rx_data <=#Tp 1'b0;`
422			`else if (go_rx_data)`
423			`rx_data <=#Tp 1'b1;`
424			`end`
425
426
427			`// Rx crc state`
428			`always @ (posedge clk or posedge rst)`
429			`begin`
430			`if (rst)`
431			`rx_crc <= 1'b0;`
432	11	mohor	`else if (reset_mode \| go_rx_crc_lim)`
433	10	mohor	`rx_crc <=#Tp 1'b0;`
434			`else if (go_rx_crc)`
435			`rx_crc <=#Tp 1'b1;`
436			`end`
437
438
439	11	mohor	`// Rx crc delimiter state`
440			`always @ (posedge clk or posedge rst)`
441			`begin`
442			`if (rst)`
443			`rx_crc_lim <= 1'b0;`
444			`else if (reset_mode \| go_rx_ack)`
445			`rx_crc_lim <=#Tp 1'b0;`
446			`else if (go_rx_crc_lim)`
447			`rx_crc_lim <=#Tp 1'b1;`
448			`end`
449
450
451	10	mohor	`// Rx ack state`
452			`always @ (posedge clk or posedge rst)`
453			`begin`
454			`if (rst)`
455			`rx_ack <= 1'b0;`
456	11	mohor	`else if (reset_mode \| go_rx_ack_lim)`
457	10	mohor	`rx_ack <=#Tp 1'b0;`
458			`else if (go_rx_ack)`
459			`rx_ack <=#Tp 1'b1;`
460			`end`
461
462
463	11	mohor	`// Rx ack delimiter state`
464			`always @ (posedge clk or posedge rst)`
465			`begin`
466			`if (rst)`
467			`rx_ack_lim <= 1'b0;`
468			`else if (reset_mode \| go_rx_eof)`
469			`rx_ack_lim <=#Tp 1'b0;`
470			`else if (go_rx_ack_lim)`
471			`rx_ack_lim <=#Tp 1'b1;`
472			`end`
473
474
475	10	mohor	`// Rx eof state`
476			`always @ (posedge clk or posedge rst)`
477			`begin`
478			`if (rst)`
479			`rx_eof <= 1'b0;`
480			`else if (go_rx_idle)`
481			`rx_eof <=#Tp 1'b0;`
482			`else if (go_rx_eof)`
483			`rx_eof <=#Tp 1'b1;`
484			`end`
485
486
487			`// ID register`
488			`always @ (posedge clk or posedge rst)`
489			`begin`
490			`if (rst)`
491			`id <= 0;`
492	11	mohor	`else if (sample_point & (rx_id1 \| rx_id2) & (~bit_de_stuff))`
493	10	mohor	`id <=#Tp {id[27:0], sampled_bit};`
494			`end`
495
496	11	mohor
497			`// rtr1 bit`
498			`always @ (posedge clk or posedge rst)`
499			`begin`
500			`if (rst)`

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