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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_bsp.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_bsp
(
  clk,
  rst,
 
  sample_point,
  sampled_bit,
  sampled_bit_q,
  reset_mode,
 
  rx_idle
 
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         sample_point;
input         sampled_bit;
input         sampled_bit_q;
input         reset_mode;
 
output        rx_idle;
 
reg           reset_mode_q;
reg     [5:0] bit_cnt;
 
reg     [3:0] data_len;
reg    [28:0] id;
reg     [2:0] bit_stuff_cnt;
reg           stuff_error;
 
wire          bit_de_stuff;
 
 
/* Rx state machine */
wire          go_rx_idle;
wire          go_rx_id1;
wire          go_rx_rtr1;
wire          go_rx_ide;
wire          go_rx_id2;
wire          go_rx_rtr2;
wire          go_rx_r1;
wire          go_rx_r0;
wire          go_rx_dlc;
wire          go_rx_data;
wire          go_rx_crc;
wire          go_rx_ack;
wire          go_rx_eof;
 
reg           rx_idle;
reg           rx_id1;
reg           rx_rtr1;
reg           rx_ide;
reg           rx_id2;
reg           rx_rtr2;
reg           rx_r1;
reg           rx_r0;
reg           rx_dlc;
reg           rx_data;
reg           rx_crc;
reg           rx_ack;
reg           rx_eof;
 
reg     [2:0] eof_cnt;
 
 
assign go_rx_idle     = sample_point &  rx_eof  & (eof_cnt == 6);
assign go_rx_id1      = sample_point &  rx_idle & (~sampled_bit);
assign go_rx_rtr1     = sample_point &  rx_id1  & (bit_cnt == 10);
assign go_rx_ide      = sample_point &  rx_rtr1;
assign go_rx_id2      = sample_point &  rx_ide  &   sampled_bit;
assign go_rx_rtr2     = sample_point &  rx_id2  & (bit_cnt == 17);
assign go_rx_r1       = sample_point &  rx_rtr2;
assign go_rx_r0       = sample_point & (rx_ide  & (~sampled_bit) | rx_r1);
assign go_rx_dlc      = sample_point &  rx_r0;
assign go_rx_data     = sample_point &  rx_dlc  & (bit_cnt == 3) & (sampled_bit | (|data_len[2:0]));
assign go_rx_crc      = sample_point & (rx_dlc  & (bit_cnt == 3) & (~sampled_bit) & (~(|data_len[2:0]))
                                     |  rx_data & (bit_cnt == ((data_len<<3) - 1'b1)));
assign go_rx_ack      = sample_point &  rx_crc  & (bit_cnt == 15);
assign go_rx_eof      = sample_point &  rx_ack  & (bit_cnt == 1) | (~reset_mode) & reset_mode_q;
 
// Rx idle state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_idle <= 1'b1;
  else if (reset_mode | go_rx_id1)
    rx_idle <=#Tp 1'b0;
  else if (go_rx_idle)
    rx_idle <=#Tp 1'b1;
end
 
 
// Rx id1 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_id1 <= 1'b0;
  else if (reset_mode | go_rx_rtr1)
    rx_id1 <=#Tp 1'b0;
  else if (go_rx_id1)
    rx_id1 <=#Tp 1'b1;
end
 
 
// Rx rtr1 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_rtr1 <= 1'b0;
  else if (reset_mode | go_rx_ide)
    rx_rtr1 <=#Tp 1'b0;
  else if (go_rx_rtr1)
    rx_rtr1 <=#Tp 1'b1;
end
 
 
// Rx ide state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ide <= 1'b0;
  else if (reset_mode | go_rx_r0 | go_rx_id2)
    rx_ide <=#Tp 1'b0;
  else if (go_rx_ide)
    rx_ide <=#Tp 1'b1;
end
 
 
// Rx id2 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_id2 <= 1'b0;
  else if (reset_mode | go_rx_rtr2)
    rx_id2 <=#Tp 1'b0;
  else if (go_rx_id2)
    rx_id2 <=#Tp 1'b1;
end
 
 
// Rx rtr2 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_rtr2 <= 1'b0;
  else if (reset_mode | go_rx_r1)
    rx_rtr2 <=#Tp 1'b0;
  else if (go_rx_rtr2)
    rx_rtr2 <=#Tp 1'b1;
end
 
 
// Rx r0 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_r1 <= 1'b0;
  else if (reset_mode | go_rx_r0)
    rx_r1 <=#Tp 1'b0;
  else if (go_rx_r1)
    rx_r1 <=#Tp 1'b1;
end
 
 
// Rx r0 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_r0 <= 1'b0;
  else if (reset_mode | go_rx_dlc)
    rx_r0 <=#Tp 1'b0;
  else if (go_rx_r0)
    rx_r0 <=#Tp 1'b1;
end
 
 
// Rx dlc state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_dlc <= 1'b0;
  else if (reset_mode | go_rx_data | go_rx_crc)
    rx_dlc <=#Tp 1'b0;
  else if (go_rx_dlc)
    rx_dlc <=#Tp 1'b1;
end
 
 
// Rx data state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_data <= 1'b0;
  else if (reset_mode | go_rx_crc)
    rx_data <=#Tp 1'b0;
  else if (go_rx_data)
    rx_data <=#Tp 1'b1;
end
 
 
// Rx crc state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_crc <= 1'b0;
  else if (reset_mode | go_rx_ack)
    rx_crc <=#Tp 1'b0;
  else if (go_rx_crc)
    rx_crc <=#Tp 1'b1;
end
 
 
// Rx ack state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ack <= 1'b0;
  else if (reset_mode | go_rx_eof)
    rx_ack <=#Tp 1'b0;
  else if (go_rx_ack)
    rx_ack <=#Tp 1'b1;
end
 
 
// Rx eof state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_eof <= 1'b0;
  else if (go_rx_idle)
    rx_eof <=#Tp 1'b0;
  else if (go_rx_eof)
    rx_eof <=#Tp 1'b1;
end
 
 
 
 
 
 
 
 
// ID register
always @ (posedge clk or posedge rst)
begin
  if (rst)
    id <= 0;
  else if (sample_point & rx_id1 & (~bit_de_stuff))
    id <=#Tp {id[27:0], sampled_bit};
end
 
// Data length
always @ (posedge clk or posedge rst)
begin
  if (rst)
    data_len <= 0;
  else if (sample_point & rx_dlc & (~bit_de_stuff))
    data_len <=#Tp {data_len[2:0], sampled_bit};
end
 
 
// bit_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_cnt <= 0;
  else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc | go_rx_ack | go_rx_eof)
    bit_cnt <=#Tp 0;
  else if (sample_point)
    bit_cnt <=#Tp bit_cnt + 1'b1;
end
 
 
// eof_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    eof_cnt <= 0;
  else if (sample_point)
    begin
      if (rx_eof & sampled_bit)
        eof_cnt <=#Tp eof_cnt + 1'b1;
      else
        eof_cnt <=#Tp 0;
    end
end
 
 
 
 
 
// bit_stuff_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_stuff_cnt <= 1;
  else if (sample_point & (rx_id1 | rx_id2 | rx_dlc | rx_data | rx_crc))    // Is this OK? Check again
    begin
      if (bit_stuff_cnt == 5)
        bit_stuff_cnt <=#Tp 1;
      else if (sampled_bit == sampled_bit_q)
        bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1;
      else
        bit_stuff_cnt <=#Tp 1;
    end
end
 
 
assign bit_de_stuff = bit_stuff_cnt == 5;
 
 
// stuff_error
always @ (posedge clk or posedge rst)
begin
  if (rst)
    stuff_error <= 0;
  else if (sample_point & (rx_id1) & bit_de_stuff & (sampled_bit == sampled_bit_q))   // Add other stages (data, control, etc.) !!!
    stuff_error <=#Tp 1'b1;
//  else if (reset condition)       // Add reset condition
//    stuff_error <=#Tp 0;
end
 
 
// Generating delayed reset_mode signal
always @ (posedge clk)
begin
  reset_mode_q <=#Tp reset_mode;
end
 
 
endmodule

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[/] [can/] [tags/] [rel_6/] [rtl/] [verilog/] [can_bsp.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_bsp.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	10	mohor	`// Revision 1.2 2002/12/27 00:12:52 mohor`
49			`// Header changed, testbench improved to send a frame (crc still missing).`
50			`//`
51	9	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
52			`// Initial`
53	2	mohor	`//`
54			`//`
55	9	mohor	`//`
56	2	mohor
57			`// synopsys translate_off`
58			`include "timescale.v"
59			`// synopsys translate_on`
60			`include "can_defines.v"
61
62			`module can_bsp`
63			`(`
64			`clk,`
65	10	mohor	`rst,`
66
67			`sample_point,`
68			`sampled_bit,`
69			`sampled_bit_q,`
70			`reset_mode,`
71
72			`rx_idle`
73
74
75	2	mohor	`);`
76
77			`parameter Tp = 1;`
78
79	10	mohor	`input clk;`
80			`input rst;`
81			`input sample_point;`
82			`input sampled_bit;`
83			`input sampled_bit_q;`
84			`input reset_mode;`
85	2	mohor
86	10	mohor	`output rx_idle;`
87	2	mohor
88	10	mohor	`reg reset_mode_q;`
89			`reg [5:0] bit_cnt;`
90	2	mohor
91	10	mohor	`reg [3:0] data_len;`
92			`reg [28:0] id;`
93			`reg [2:0] bit_stuff_cnt;`
94			`reg stuff_error;`
95
96			`wire bit_de_stuff;`
97
98
99			`/* Rx state machine */`
100			`wire go_rx_idle;`
101			`wire go_rx_id1;`
102			`wire go_rx_rtr1;`
103			`wire go_rx_ide;`
104			`wire go_rx_id2;`
105			`wire go_rx_rtr2;`
106			`wire go_rx_r1;`
107			`wire go_rx_r0;`
108			`wire go_rx_dlc;`
109			`wire go_rx_data;`
110			`wire go_rx_crc;`
111			`wire go_rx_ack;`
112			`wire go_rx_eof;`
113
114			`reg rx_idle;`
115			`reg rx_id1;`
116			`reg rx_rtr1;`
117			`reg rx_ide;`
118			`reg rx_id2;`
119			`reg rx_rtr2;`
120			`reg rx_r1;`
121			`reg rx_r0;`
122			`reg rx_dlc;`
123			`reg rx_data;`
124			`reg rx_crc;`
125			`reg rx_ack;`
126			`reg rx_eof;`
127
128			`reg [2:0] eof_cnt;`
129
130
131			`assign go_rx_idle = sample_point & rx_eof & (eof_cnt == 6);`
132			`assign go_rx_id1 = sample_point & rx_idle & (~sampled_bit);`
133			`assign go_rx_rtr1 = sample_point & rx_id1 & (bit_cnt == 10);`
134			`assign go_rx_ide = sample_point & rx_rtr1;`
135			`assign go_rx_id2 = sample_point & rx_ide & sampled_bit;`
136			`assign go_rx_rtr2 = sample_point & rx_id2 & (bit_cnt == 17);`
137			`assign go_rx_r1 = sample_point & rx_rtr2;`
138			`assign go_rx_r0 = sample_point & (rx_ide & (~sampled_bit) \| rx_r1);`
139			`assign go_rx_dlc = sample_point & rx_r0;`
140			`assign go_rx_data = sample_point & rx_dlc & (bit_cnt == 3) & (sampled_bit \| (\|data_len[2:0]));`
141			`assign go_rx_crc = sample_point & (rx_dlc & (bit_cnt == 3) & (~sampled_bit) & (~(\|data_len[2:0]))`
142			`\| rx_data & (bit_cnt == ((data_len<<3) - 1'b1)));`
143			`assign go_rx_ack = sample_point & rx_crc & (bit_cnt == 15);`
144			`assign go_rx_eof = sample_point & rx_ack & (bit_cnt == 1) \| (~reset_mode) & reset_mode_q;`
145
146			`// Rx idle state`
147			`always @ (posedge clk or posedge rst)`
148			`begin`
149			`if (rst)`
150			`rx_idle <= 1'b1;`
151			`else if (reset_mode \| go_rx_id1)`
152			`rx_idle <=#Tp 1'b0;`
153			`else if (go_rx_idle)`
154			`rx_idle <=#Tp 1'b1;`
155			`end`
156
157
158			`// Rx id1 state`
159			`always @ (posedge clk or posedge rst)`
160			`begin`
161			`if (rst)`
162			`rx_id1 <= 1'b0;`
163			`else if (reset_mode \| go_rx_rtr1)`
164			`rx_id1 <=#Tp 1'b0;`
165			`else if (go_rx_id1)`
166			`rx_id1 <=#Tp 1'b1;`
167			`end`
168
169
170			`// Rx rtr1 state`
171			`always @ (posedge clk or posedge rst)`
172			`begin`
173			`if (rst)`
174			`rx_rtr1 <= 1'b0;`
175			`else if (reset_mode \| go_rx_ide)`
176			`rx_rtr1 <=#Tp 1'b0;`
177			`else if (go_rx_rtr1)`
178			`rx_rtr1 <=#Tp 1'b1;`
179			`end`
180
181
182			`// Rx ide state`
183			`always @ (posedge clk or posedge rst)`
184			`begin`
185			`if (rst)`
186			`rx_ide <= 1'b0;`
187			`else if (reset_mode \| go_rx_r0 \| go_rx_id2)`
188			`rx_ide <=#Tp 1'b0;`
189			`else if (go_rx_ide)`
190			`rx_ide <=#Tp 1'b1;`
191			`end`
192
193
194			`// Rx id2 state`
195			`always @ (posedge clk or posedge rst)`
196			`begin`
197			`if (rst)`
198			`rx_id2 <= 1'b0;`
199			`else if (reset_mode \| go_rx_rtr2)`
200			`rx_id2 <=#Tp 1'b0;`
201			`else if (go_rx_id2)`
202			`rx_id2 <=#Tp 1'b1;`
203			`end`
204
205
206			`// Rx rtr2 state`
207			`always @ (posedge clk or posedge rst)`
208			`begin`
209			`if (rst)`
210			`rx_rtr2 <= 1'b0;`
211			`else if (reset_mode \| go_rx_r1)`
212			`rx_rtr2 <=#Tp 1'b0;`
213			`else if (go_rx_rtr2)`
214			`rx_rtr2 <=#Tp 1'b1;`
215			`end`
216
217
218			`// Rx r0 state`
219			`always @ (posedge clk or posedge rst)`
220			`begin`
221			`if (rst)`
222			`rx_r1 <= 1'b0;`
223			`else if (reset_mode \| go_rx_r0)`
224			`rx_r1 <=#Tp 1'b0;`
225			`else if (go_rx_r1)`
226			`rx_r1 <=#Tp 1'b1;`
227			`end`
228
229
230			`// Rx r0 state`
231			`always @ (posedge clk or posedge rst)`
232			`begin`
233			`if (rst)`
234			`rx_r0 <= 1'b0;`
235			`else if (reset_mode \| go_rx_dlc)`
236			`rx_r0 <=#Tp 1'b0;`
237			`else if (go_rx_r0)`
238			`rx_r0 <=#Tp 1'b1;`
239			`end`
240
241
242			`// Rx dlc state`
243			`always @ (posedge clk or posedge rst)`
244			`begin`
245			`if (rst)`
246			`rx_dlc <= 1'b0;`
247			`else if (reset_mode \| go_rx_data \| go_rx_crc)`
248			`rx_dlc <=#Tp 1'b0;`
249			`else if (go_rx_dlc)`
250			`rx_dlc <=#Tp 1'b1;`
251			`end`
252
253
254			`// Rx data state`
255			`always @ (posedge clk or posedge rst)`
256			`begin`
257			`if (rst)`
258			`rx_data <= 1'b0;`
259			`else if (reset_mode \| go_rx_crc)`
260			`rx_data <=#Tp 1'b0;`
261			`else if (go_rx_data)`
262			`rx_data <=#Tp 1'b1;`
263			`end`
264
265
266			`// Rx crc state`
267			`always @ (posedge clk or posedge rst)`
268			`begin`
269			`if (rst)`
270			`rx_crc <= 1'b0;`
271			`else if (reset_mode \| go_rx_ack)`
272			`rx_crc <=#Tp 1'b0;`
273			`else if (go_rx_crc)`
274			`rx_crc <=#Tp 1'b1;`
275			`end`
276
277
278			`// Rx ack state`
279			`always @ (posedge clk or posedge rst)`
280			`begin`
281			`if (rst)`
282			`rx_ack <= 1'b0;`
283			`else if (reset_mode \| go_rx_eof)`
284			`rx_ack <=#Tp 1'b0;`
285			`else if (go_rx_ack)`
286			`rx_ack <=#Tp 1'b1;`
287			`end`
288
289
290			`// Rx eof state`
291			`always @ (posedge clk or posedge rst)`
292			`begin`
293			`if (rst)`
294			`rx_eof <= 1'b0;`
295			`else if (go_rx_idle)`
296			`rx_eof <=#Tp 1'b0;`
297			`else if (go_rx_eof)`
298			`rx_eof <=#Tp 1'b1;`
299			`end`
300
301
302
303
304
305
306
307
308			`// ID register`
309			`always @ (posedge clk or posedge rst)`
310			`begin`
311			`if (rst)`
312			`id <= 0;`
313			`else if (sample_point & rx_id1 & (~bit_de_stuff))`
314			`id <=#Tp {id[27:0], sampled_bit};`
315			`end`
316
317			`// Data length`
318			`always @ (posedge clk or posedge rst)`
319			`begin`
320			`if (rst)`
321			`data_len <= 0;`
322			`else if (sample_point & rx_dlc & (~bit_de_stuff))`
323			`data_len <=#Tp {data_len[2:0], sampled_bit};`
324			`end`
325
326
327			`// bit_cnt`
328			`always @ (posedge clk or posedge rst)`
329			`begin`
330			`if (rst)`
331			`bit_cnt <= 0;`
332			`else if (go_rx_id1 \| go_rx_id2 \| go_rx_dlc \| go_rx_data \| go_rx_crc \| go_rx_ack \| go_rx_eof)`
333			`bit_cnt <=#Tp 0;`
334			`else if (sample_point)`
335			`bit_cnt <=#Tp bit_cnt + 1'b1;`
336			`end`
337
338
339			`// eof_cnt`
340			`always @ (posedge clk or posedge rst)`
341			`begin`
342			`if (rst)`
343			`eof_cnt <= 0;`
344			`else if (sample_point)`
345			`begin`
346			`if (rx_eof & sampled_bit)`
347			`eof_cnt <=#Tp eof_cnt + 1'b1;`
348			`else`
349			`eof_cnt <=#Tp 0;`
350			`end`
351			`end`
352
353
354
355
356
357			`// bit_stuff_cnt`
358			`always @ (posedge clk or posedge rst)`
359			`begin`
360			`if (rst)`
361			`bit_stuff_cnt <= 1;`
362			`else if (sample_point & (rx_id1 \| rx_id2 \| rx_dlc \| rx_data \| rx_crc)) // Is this OK? Check again`
363			`begin`
364			`if (bit_stuff_cnt == 5)`
365			`bit_stuff_cnt <=#Tp 1;`
366			`else if (sampled_bit == sampled_bit_q)`
367			`bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1;`
368			`else`
369			`bit_stuff_cnt <=#Tp 1;`
370			`end`
371			`end`
372
373
374			`assign bit_de_stuff = bit_stuff_cnt == 5;`
375
376
377			`// stuff_error`
378			`always @ (posedge clk or posedge rst)`
379			`begin`
380			`if (rst)`
381			`stuff_error <= 0;`
382			`else if (sample_point & (rx_id1) & bit_de_stuff & (sampled_bit == sampled_bit_q)) // Add other stages (data, control, etc.) !!!`
383			`stuff_error <=#Tp 1'b1;`
384			`// else if (reset condition) // Add reset condition`
385			`// stuff_error <=#Tp 0;`
386			`end`
387
388
389			`// Generating delayed reset_mode signal`
390			`always @ (posedge clk)`
391			`begin`
392			`reset_mode_q <=#Tp reset_mode;`
393			`end`
394
395
396	2	mohor	`endmodule`