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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_bsp.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.3  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.2  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_bsp
(
  clk,
  rst,
 
  sample_point,
  sampled_bit,
  sampled_bit_q,
  hard_sync,
  resync,
 
  /* Mode register */
  reset_mode,
  acceptance_filter_mode,
 
  // Clock Divider register
  extended_mode,
 
  rx_idle,
 
  /* This section is for BASIC and EXTENDED mode */
  /* Acceptance code register */
  acceptance_code_0,
 
  /* Acceptance mask register */
  acceptance_mask_0,
  /* End: This section is for BASIC and EXTENDED mode */
 
  /* This section is for EXTENDED mode */
  /* Acceptance code register */
  acceptance_code_1,
  acceptance_code_2,
  acceptance_code_3,
 
  /* Acceptance mask register */
  acceptance_mask_1,
  acceptance_mask_2,
  acceptance_mask_3
  /* End: This section is for EXTENDED mode */
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         sample_point;
input         sampled_bit;
input         sampled_bit_q;
input         hard_sync;
input         resync;
 
input         reset_mode;
input         acceptance_filter_mode;
input         extended_mode;
 
 
output        rx_idle;
 
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
input   [7:0] acceptance_code_0;
 
/* Acceptance mask register */
input   [7:0] acceptance_mask_0;
 
/* End: This section is for BASIC and EXTENDED mode */
 
 
/* This section is for EXTENDED mode */
/* Acceptance code register */
input   [7:0] acceptance_code_1;
input   [7:0] acceptance_code_2;
input   [7:0] acceptance_code_3;
 
/* Acceptance mask register */
input   [7:0] acceptance_mask_1;
input   [7:0] acceptance_mask_2;
input   [7:0] acceptance_mask_3;
 
/* End: This section is for EXTENDED mode */
 
 
 
reg           reset_mode_q;
reg     [5:0] bit_cnt;
 
reg     [3:0] data_len;
reg    [28:0] id;
reg     [2:0] bit_stuff_cnt;
reg           stuff_error;
 
wire          bit_de_stuff;
 
 
/* Rx state machine */
wire          go_rx_idle;
wire          go_rx_id1;
wire          go_rx_rtr1;
wire          go_rx_ide;
wire          go_rx_id2;
wire          go_rx_rtr2;
wire          go_rx_r1;
wire          go_rx_r0;
wire          go_rx_dlc;
wire          go_rx_data;
wire          go_rx_crc;
wire          go_rx_crc_lim;
wire          go_rx_ack;
wire          go_rx_ack_lim;
wire          go_rx_eof;
 
wire          go_crc_enable;
wire          rst_crc_enable;
 
wire          bit_de_stuff_set;
wire          bit_de_stuff_reset;
 
reg           rx_idle;
reg           rx_id1;
reg           rx_rtr1;
reg           rx_ide;
reg           rx_id2;
reg           rx_rtr2;
reg           rx_r1;
reg           rx_r0;
reg           rx_dlc;
reg           rx_data;
reg           rx_crc;
reg           rx_crc_lim;
reg           rx_ack;
reg           rx_ack_lim;
reg           rx_eof;
 
reg           crc_enable;
 
reg     [2:0] eof_cnt;
wire   [14:0] calculated_crc;
 
assign go_rx_idle     =                   sample_point &  rx_eof  & (eof_cnt == 6);
assign go_rx_id1      =                   sample_point &  rx_idle & (~sampled_bit);
assign go_rx_rtr1     = (~bit_de_stuff) & sample_point &  rx_id1  & (bit_cnt == 10);
assign go_rx_ide      = (~bit_de_stuff) & sample_point &  rx_rtr1;
assign go_rx_id2      = (~bit_de_stuff) & sample_point &  rx_ide  &   sampled_bit;
assign go_rx_rtr2     = (~bit_de_stuff) & sample_point &  rx_id2  & (bit_cnt == 17);
assign go_rx_r1       = (~bit_de_stuff) & sample_point &  rx_rtr2;
assign go_rx_r0       = (~bit_de_stuff) & sample_point & (rx_ide  & (~sampled_bit) | rx_r1);
assign go_rx_dlc      = (~bit_de_stuff) & sample_point &  rx_r0;
assign go_rx_data     = (~bit_de_stuff) & sample_point &  rx_dlc  & (bit_cnt == 3) & (sampled_bit | (|data_len[2:0]));
assign go_rx_crc      = (~bit_de_stuff) & sample_point & (rx_dlc  & (bit_cnt == 3) & (~sampled_bit) & (~(|data_len[2:0])) |
                                                          rx_data & (bit_cnt == ((data_len<<3) - 1'b1)));
assign go_rx_crc_lim  =                   sample_point &  rx_crc  & (bit_cnt == 14);
assign go_rx_ack      =                   sample_point &  rx_crc_lim;
assign go_rx_ack_lim  =                   sample_point &  rx_ack;
assign go_rx_eof      =                   sample_point &  rx_ack_lim  | (~reset_mode) & reset_mode_q;
 
assign go_crc_enable  = hard_sync;
assign rst_crc_enable = go_rx_crc;
 
assign bit_de_stuff_set   = go_rx_id1;
assign bit_de_stuff_reset = go_rx_crc_lim;
 
 
// Rx idle state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_idle <= 1'b1;
  else if (reset_mode | go_rx_id1)
    rx_idle <=#Tp 1'b0;
  else if (go_rx_idle)
    rx_idle <=#Tp 1'b1;
end
 
 
// Rx id1 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_id1 <= 1'b0;
  else if (reset_mode | go_rx_rtr1)
    rx_id1 <=#Tp 1'b0;
  else if (go_rx_id1)
    rx_id1 <=#Tp 1'b1;
end
 
 
// Rx rtr1 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_rtr1 <= 1'b0;
  else if (reset_mode | go_rx_ide)
    rx_rtr1 <=#Tp 1'b0;
  else if (go_rx_rtr1)
    rx_rtr1 <=#Tp 1'b1;
end
 
 
// Rx ide state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ide <= 1'b0;
  else if (reset_mode | go_rx_r0 | go_rx_id2)
    rx_ide <=#Tp 1'b0;
  else if (go_rx_ide)
    rx_ide <=#Tp 1'b1;
end
 
 
// Rx id2 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_id2 <= 1'b0;
  else if (reset_mode | go_rx_rtr2)
    rx_id2 <=#Tp 1'b0;
  else if (go_rx_id2)
    rx_id2 <=#Tp 1'b1;
end
 
 
// Rx rtr2 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_rtr2 <= 1'b0;
  else if (reset_mode | go_rx_r1)
    rx_rtr2 <=#Tp 1'b0;
  else if (go_rx_rtr2)
    rx_rtr2 <=#Tp 1'b1;
end
 
 
// Rx r0 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_r1 <= 1'b0;
  else if (reset_mode | go_rx_r0)
    rx_r1 <=#Tp 1'b0;
  else if (go_rx_r1)
    rx_r1 <=#Tp 1'b1;
end
 
 
// Rx r0 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_r0 <= 1'b0;
  else if (reset_mode | go_rx_dlc)
    rx_r0 <=#Tp 1'b0;
  else if (go_rx_r0)
    rx_r0 <=#Tp 1'b1;
end
 
 
// Rx dlc state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_dlc <= 1'b0;
  else if (reset_mode | go_rx_data | go_rx_crc)
    rx_dlc <=#Tp 1'b0;
  else if (go_rx_dlc)
    rx_dlc <=#Tp 1'b1;
end
 
 
// Rx data state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_data <= 1'b0;
  else if (reset_mode | go_rx_crc)
    rx_data <=#Tp 1'b0;
  else if (go_rx_data)
    rx_data <=#Tp 1'b1;
end
 
 
// Rx crc state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_crc <= 1'b0;
  else if (reset_mode | go_rx_crc_lim)
    rx_crc <=#Tp 1'b0;
  else if (go_rx_crc)
    rx_crc <=#Tp 1'b1;
end
 
 
// Rx crc delimiter state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_crc_lim <= 1'b0;
  else if (reset_mode | go_rx_ack)
    rx_crc_lim <=#Tp 1'b0;
  else if (go_rx_crc_lim)
    rx_crc_lim <=#Tp 1'b1;
end
 
 
// Rx ack state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ack <= 1'b0;
  else if (reset_mode | go_rx_ack_lim)
    rx_ack <=#Tp 1'b0;
  else if (go_rx_ack)
    rx_ack <=#Tp 1'b1;
end
 
 
// Rx ack delimiter state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ack_lim <= 1'b0;
  else if (reset_mode | go_rx_eof)
    rx_ack_lim <=#Tp 1'b0;
  else if (go_rx_ack_lim)
    rx_ack_lim <=#Tp 1'b1;
end
 
 
// Rx eof state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_eof <= 1'b0;
  else if (go_rx_idle)
    rx_eof <=#Tp 1'b0;
  else if (go_rx_eof)
    rx_eof <=#Tp 1'b1;
end
 
 
 
 
reg rtr1;
reg ide;
reg rtr2;
reg [14:0] crc_in;
 
// ID register
always @ (posedge clk or posedge rst)
begin
  if (rst)
    id <= 0;
  else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
    id <=#Tp {id[27:0], sampled_bit};
end
 
 
// rtr1 bit
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rtr1 <= 0;
  else if (sample_point & rx_rtr1 & (~bit_de_stuff))
    rtr1 <=#Tp sampled_bit;
end
 
 
// rtr2 bit
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rtr2 <= 0;
  else if (sample_point & rx_rtr2 & (~bit_de_stuff))
    rtr2 <=#Tp sampled_bit;
end
 
 
// ide bit
always @ (posedge clk or posedge rst)
begin
  if (rst)
    ide <= 0;
  else if (sample_point & rx_ide & (~bit_de_stuff))
    ide <=#Tp sampled_bit;
end
 
 
// Data length
always @ (posedge clk or posedge rst)
begin
  if (rst)
    data_len <= 0;
  else if (sample_point & rx_dlc & (~bit_de_stuff))
    data_len <=#Tp {data_len[2:0], sampled_bit};
end
 
 
// Data
reg [7:0] tmp_data;
reg [7:0] tmp_fifo [0:7];
always @ (posedge clk or posedge rst)
begin
  if (rst)
    tmp_data <= 0;
  else if (sample_point & rx_data & (~bit_de_stuff))
    tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
end
 
 
reg write_data_to_tmp_fifo;
always @ (posedge clk or posedge rst)
begin
  if (rst)
    write_data_to_tmp_fifo <= 0;
  else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
    write_data_to_tmp_fifo <=#Tp 1'b1;
  else
    write_data_to_tmp_fifo <=#Tp 0;
end
 
 
reg [2:0] byte_cnt;
always @ (posedge clk or posedge rst)
begin
  if (rst)
    byte_cnt <= 0;
  else if (write_data_to_tmp_fifo)
    byte_cnt <=#Tp byte_cnt + 1;
  else if (sample_point & go_rx_crc_lim)
    byte_cnt <=#Tp 0;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (write_data_to_tmp_fifo)
    tmp_fifo[byte_cnt] <=#Tp tmp_data;
end
 
 
 
// CRC
always @ (posedge clk or posedge rst)
begin
  if (rst)
    crc_in <= 0;
  else if (sample_point & rx_crc & (~bit_de_stuff))
    crc_in <=#Tp {crc_in[13:0], sampled_bit};
end
 
 
// bit_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_cnt <= 0;
  else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc | go_rx_ack | go_rx_eof)
    bit_cnt <=#Tp 0;
  else if (sample_point & (~bit_de_stuff))
    bit_cnt <=#Tp bit_cnt + 1'b1;
end
 
 
// eof_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    eof_cnt <= 0;
  else if (sample_point)
    begin
      if (rx_eof & sampled_bit)
        eof_cnt <=#Tp eof_cnt + 1'b1;
      else
        eof_cnt <=#Tp 0;
    end
end
 
 
// Enabling bit de-stuffing
reg bit_stuff_cnt_en;
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_stuff_cnt_en <= 1'b0;
  else if (bit_de_stuff_set)
    bit_stuff_cnt_en <=#Tp 1'b1;
  else if (bit_de_stuff_reset)
    bit_stuff_cnt_en <=#Tp 1'b0;
end
 
// bit_stuff_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_stuff_cnt <= 1;
  else if (sample_point & bit_stuff_cnt_en)
    begin
      if (bit_stuff_cnt == 5)
        bit_stuff_cnt <=#Tp 1;
      else if (sampled_bit == sampled_bit_q)
        bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1;
      else
        bit_stuff_cnt <=#Tp 1;
    end
end
 
 
assign bit_de_stuff = bit_stuff_cnt == 5;
 
 
// stuff_error
always @ (posedge clk or posedge rst)
begin
  if (rst)
    stuff_error <= 0;
  else if (sample_point & (rx_id1) & bit_de_stuff & (sampled_bit == sampled_bit_q))   // Add other stages (data, control, etc.) !!!
    stuff_error <=#Tp 1'b1;
//  else if (reset condition)       // Add reset condition
//    stuff_error <=#Tp 0;
end
 
 
// Generating delayed reset_mode signal
always @ (posedge clk)
begin
  reset_mode_q <=#Tp reset_mode;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    crc_enable <= 1'b0;
  else if (go_crc_enable)
    crc_enable <=#Tp 1'b1;
  else if (reset_mode | rst_crc_enable)
    crc_enable <=#Tp 1'b0;
end
 
 
reg crc_error;
// CRC error generation
always @ (posedge clk or posedge rst)
begin
  if (rst)
    crc_error <= 0;
  else if (go_rx_ack)
    crc_error <=#Tp crc_in != calculated_crc;
  else if (reset_mode | rx_eof)
    crc_error <=#Tp 0;
end
 
 
 
// Instantiation of the RX CRC module
can_crc i_can_crc_rx
(
  .clk(clk),
//  .data(sampled_bit & (~rx_crc)),     // Zeros are shifted in for calculation when we are in crc stage
  .data(sampled_bit ),     // Zeros are shifted in for calculation when we are in crc stage
  .enable(crc_enable & sample_point & (~bit_de_stuff)),
  .initialize(rx_eof),
  .crc(calculated_crc)
);
 
 
 
wire          id_ok;        // If received ID matches ID set in registers
wire          no_data;      // There is no data (RTR bit set to 1 or DLC field equal to 0)
 
assign no_data = rtr1 | (~(|data_len));
 
can_acf i_can_acf
(
  .clk(clk),
  .rst(rst),
 
  .id(id),
 
  /* Mode register */
  .reset_mode(reset_mode),
  .acceptance_filter_mode(acceptance_filter_mode),
 
  // Clock Divider register
  .extended_mode(extended_mode),
 
  /* This section is for BASIC and EXTENDED mode */
  /* Acceptance code register */
  .acceptance_code_0(acceptance_code_0),
 
  /* Acceptance mask register */
  .acceptance_mask_0(acceptance_mask_0),
  /* End: This section is for BASIC and EXTENDED mode */
 
  /* This section is for EXTENDED mode */
  /* Acceptance code register */
  .acceptance_code_1(acceptance_code_1),
  .acceptance_code_2(acceptance_code_2),
  .acceptance_code_3(acceptance_code_3),
 
  /* Acceptance mask register */
  .acceptance_mask_1(acceptance_mask_1),
  .acceptance_mask_2(acceptance_mask_2),
  .acceptance_mask_3(acceptance_mask_3),
  /* End: This section is for EXTENDED mode */
 
  .sample_point(sample_point),
  .go_rx_crc_lim(go_rx_crc_lim),
  .go_rx_idle(go_rx_idle),
 
  .data0(tmp_fifo[0]),
  .data1(tmp_fifo[1]),
  .rtr1(rtr1),
  .rtr2(rtr2),
  .ide(ide),
  .no_data(no_data),
 
  .id_ok(id_ok)
 
);
 
 
 
reg [3:0] wr_fifo_cnt;    // Counting the data written in FIFO
 
reg wr_fifo_normal_mode;    // Write fifo when in normal mode (clock divider register)
reg wr_fifo_ext_mode_std;   // Write fifo when in extended mode (clock divider register) and receiving standard format msg
reg wr_fifo_ext_mode_ext;   // Write fifo when in extended mode (clock divider register) and receiving extended format msg
 
wire reset_wr_fifo_normal_mode;
 
wire [3:0] total_rx_byte = (data_len < 8)? data_len : 4'h8;
 
 
 
 
 
assign reset_wr_fifo_normal_mode = wr_fifo_cnt == (1'b1 + total_rx_byte);
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_fifo_normal_mode <= 1'b0;
  if (go_rx_ack_lim & (~extended_mode) & id_ok & (~crc_error))
    wr_fifo_normal_mode <=#Tp 1'b1;
  else if (reset_wr_fifo_normal_mode)
    wr_fifo_normal_mode <=#Tp 1'b0;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_fifo_cnt <= 0;
  if (wr_fifo_normal_mode)
    wr_fifo_cnt <=#Tp wr_fifo_cnt + 1;
  else if (reset_wr_fifo_normal_mode)
    wr_fifo_cnt <=#Tp 0;
end
 
 
reg [7:0] data_for_fifo;
always @ (extended_mode or ide or tmp_fifo or wr_fifo_cnt)
begin
  if (extended_mode)      // extended mode
    begin
      if (ide)              // extended format
        begin
          case (wr_fifo_cnt)            // synopsys parallel_case synopsys full_case
            4'h0  : data_for_fifo <= {1'b1, rtr2, 2'h0, data_len};
            4'h1  : data_for_fifo <= id[28:21];
            4'h2  : data_for_fifo <= id[20:13];
            4'h3  : data_for_fifo <= id[12:5];
            4'h4  : data_for_fifo <= {id[4:0], 3'h0};
            4'h5  : data_for_fifo <= tmp_fifo[0];
            4'h6  : data_for_fifo <= tmp_fifo[1];
            4'h7  : data_for_fifo <= tmp_fifo[2];
            4'h8  : data_for_fifo <= tmp_fifo[3];
            4'h9  : data_for_fifo <= tmp_fifo[4];
            4'hA  : data_for_fifo <= tmp_fifo[5];
            4'hB  : data_for_fifo <= tmp_fifo[6];
            4'hC  : data_for_fifo <= tmp_fifo[7];
          endcase
        end
      else                  // standard format
        begin
          case (wr_fifo_cnt)            // synopsys parallel_case synopsys full_case
            4'h0  : data_for_fifo <= {1'b0, rtr1, 2'h0, data_len};
            4'h1  : data_for_fifo <= id[10:3];
            4'h2  : data_for_fifo <= {id[2:0], 5'h0};
            4'h3  : data_for_fifo <= tmp_fifo[0];
            4'h4  : data_for_fifo <= tmp_fifo[1];
            4'h5  : data_for_fifo <= tmp_fifo[2];
            4'h6  : data_for_fifo <= tmp_fifo[3];
            4'h7  : data_for_fifo <= tmp_fifo[4];
            4'h8  : data_for_fifo <= tmp_fifo[5];
            4'h9  : data_for_fifo <= tmp_fifo[6];
            4'hA  : data_for_fifo <= tmp_fifo[7];
          endcase
        end
    end
  else                    // normal mode
    begin
      case (wr_fifo_cnt)            // synopsys parallel_case synopsys full_case
        4'h0  : data_for_fifo <= id[10:3];
        4'h1  : data_for_fifo <= {id[2:0], rtr1, data_len};
        4'h2  : data_for_fifo <= tmp_fifo[0];
        4'h3  : data_for_fifo <= tmp_fifo[1];
        4'h4  : data_for_fifo <= tmp_fifo[2];
        4'h5  : data_for_fifo <= tmp_fifo[3];
        4'h6  : data_for_fifo <= tmp_fifo[4];
        4'h7  : data_for_fifo <= tmp_fifo[5];
        4'h8  : data_for_fifo <= tmp_fifo[6];
        4'h9  : data_for_fifo <= tmp_fifo[7];
      endcase
    end
end
 
/*
always @ (posedge clk or posedge rst)
begin
  if (write_data_to_tmp_fifo)
    tmp_fifo[byte_cnt] <=#Tp tmp_data;
end
 
 
 
// Instantiation of the RX fifo module
can_fifo i_can_fifo;
(
  .clk(clk),
  .rst(rst),
 
  .rd(rd),
  .wr(wr),
  .wr_length_info(wr_length_info),
 
  .data_in(data_in),
  .data_out(data_out),
 
  .reset_mode(reset_mode),
  .release_buffer(release_buffer),
 
  // Clock Divider register
  .extended_mode(extended_mode)
 
);
*/
 
 
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_bsp.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	12	mohor	`// Revision 1.4 2003/01/08 02:10:53 mohor`
49			`// Acceptance filter added.`
50			`//`
51	11	mohor	`// Revision 1.3 2002/12/28 04:13:23 mohor`
52			`// Backup version.`
53			`//`
54	10	mohor	`// Revision 1.2 2002/12/27 00:12:52 mohor`
55			`// Header changed, testbench improved to send a frame (crc still missing).`
56			`//`
57	9	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
58			`// Initial`
59	2	mohor	`//`
60			`//`
61	9	mohor	`//`
62	2	mohor
63			`// synopsys translate_off`
64			`include "timescale.v"
65			`// synopsys translate_on`
66			`include "can_defines.v"
67
68			`module can_bsp`
69			`(`
70			`clk,`
71	10	mohor	`rst,`
72
73			`sample_point,`
74			`sampled_bit,`
75			`sampled_bit_q,`
76	11	mohor	`hard_sync,`
77			`resync,`
78
79			`/* Mode register */`
80	10	mohor	`reset_mode,`
81	11	mohor	`acceptance_filter_mode,`
82
83	12	mohor	`// Clock Divider register`
84	11	mohor	`extended_mode,`
85
86			`rx_idle,`
87
88			`/* This section is for BASIC and EXTENDED mode */`
89			`/* Acceptance code register */`
90			`acceptance_code_0,`
91
92			`/* Acceptance mask register */`
93			`acceptance_mask_0,`
94			`/* End: This section is for BASIC and EXTENDED mode */`
95	10	mohor
96	11	mohor	`/* This section is for EXTENDED mode */`
97			`/* Acceptance code register */`
98			`acceptance_code_1,`
99			`acceptance_code_2,`
100			`acceptance_code_3,`
101	10	mohor
102	11	mohor	`/* Acceptance mask register */`
103			`acceptance_mask_1,`
104			`acceptance_mask_2,`
105			`acceptance_mask_3`
106			`/* End: This section is for EXTENDED mode */`
107	10	mohor
108	2	mohor	`);`
109
110			`parameter Tp = 1;`
111
112	10	mohor	`input clk;`
113			`input rst;`
114			`input sample_point;`
115			`input sampled_bit;`
116			`input sampled_bit_q;`
117	11	mohor	`input hard_sync;`
118			`input resync;`
119
120	10	mohor	`input reset_mode;`
121	11	mohor	`input acceptance_filter_mode;`
122			`input extended_mode;`
123	2	mohor
124	11	mohor
125	10	mohor	`output rx_idle;`
126	2	mohor
127	11	mohor	`/* This section is for BASIC and EXTENDED mode */`
128			`/* Acceptance code register */`
129			`input [7:0] acceptance_code_0;`
130
131			`/* Acceptance mask register */`
132			`input [7:0] acceptance_mask_0;`
133
134			`/* End: This section is for BASIC and EXTENDED mode */`
135
136
137			`/* This section is for EXTENDED mode */`
138			`/* Acceptance code register */`
139			`input [7:0] acceptance_code_1;`
140			`input [7:0] acceptance_code_2;`
141			`input [7:0] acceptance_code_3;`
142
143			`/* Acceptance mask register */`
144			`input [7:0] acceptance_mask_1;`
145			`input [7:0] acceptance_mask_2;`
146			`input [7:0] acceptance_mask_3;`
147
148			`/* End: This section is for EXTENDED mode */`
149
150
151
152	10	mohor	`reg reset_mode_q;`
153			`reg [5:0] bit_cnt;`
154	2	mohor
155	10	mohor	`reg [3:0] data_len;`
156			`reg [28:0] id;`
157			`reg [2:0] bit_stuff_cnt;`
158			`reg stuff_error;`
159
160			`wire bit_de_stuff;`
161
162
163			`/* Rx state machine */`
164			`wire go_rx_idle;`
165			`wire go_rx_id1;`
166			`wire go_rx_rtr1;`
167			`wire go_rx_ide;`
168			`wire go_rx_id2;`
169			`wire go_rx_rtr2;`
170			`wire go_rx_r1;`
171			`wire go_rx_r0;`
172			`wire go_rx_dlc;`
173			`wire go_rx_data;`
174			`wire go_rx_crc;`
175	11	mohor	`wire go_rx_crc_lim;`
176	10	mohor	`wire go_rx_ack;`
177	11	mohor	`wire go_rx_ack_lim;`
178	10	mohor	`wire go_rx_eof;`
179
180	11	mohor	`wire go_crc_enable;`
181			`wire rst_crc_enable;`
182
183			`wire bit_de_stuff_set;`
184			`wire bit_de_stuff_reset;`
185
186	10	mohor	`reg rx_idle;`
187			`reg rx_id1;`
188			`reg rx_rtr1;`
189			`reg rx_ide;`
190			`reg rx_id2;`
191			`reg rx_rtr2;`
192			`reg rx_r1;`
193			`reg rx_r0;`
194			`reg rx_dlc;`
195			`reg rx_data;`
196			`reg rx_crc;`
197	11	mohor	`reg rx_crc_lim;`
198	10	mohor	`reg rx_ack;`
199	11	mohor	`reg rx_ack_lim;`
200	10	mohor	`reg rx_eof;`
201
202	11	mohor	`reg crc_enable;`
203
204	10	mohor	`reg [2:0] eof_cnt;`
205	11	mohor	`wire [14:0] calculated_crc;`
206	10	mohor
207	11	mohor	`assign go_rx_idle = sample_point & rx_eof & (eof_cnt == 6);`
208			`assign go_rx_id1 = sample_point & rx_idle & (~sampled_bit);`
209			`assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt == 10);`
210			`assign go_rx_ide = (~bit_de_stuff) & sample_point & rx_rtr1;`
211			`assign go_rx_id2 = (~bit_de_stuff) & sample_point & rx_ide & sampled_bit;`
212			`assign go_rx_rtr2 = (~bit_de_stuff) & sample_point & rx_id2 & (bit_cnt == 17);`
213			`assign go_rx_r1 = (~bit_de_stuff) & sample_point & rx_rtr2;`
214			`assign go_rx_r0 = (~bit_de_stuff) & sample_point & (rx_ide & (~sampled_bit) \| rx_r1);`
215			`assign go_rx_dlc = (~bit_de_stuff) & sample_point & rx_r0;`
216			`assign go_rx_data = (~bit_de_stuff) & sample_point & rx_dlc & (bit_cnt == 3) & (sampled_bit \| (\|data_len[2:0]));`
217			`assign go_rx_crc = (~bit_de_stuff) & sample_point & (rx_dlc & (bit_cnt == 3) & (~sampled_bit) & (~(\|data_len[2:0])) \|`
218			`rx_data & (bit_cnt == ((data_len<<3) - 1'b1)));`
219			`assign go_rx_crc_lim = sample_point & rx_crc & (bit_cnt == 14);`
220			`assign go_rx_ack = sample_point & rx_crc_lim;`
221			`assign go_rx_ack_lim = sample_point & rx_ack;`
222			`assign go_rx_eof = sample_point & rx_ack_lim \| (~reset_mode) & reset_mode_q;`
223	10	mohor
224	11	mohor	`assign go_crc_enable = hard_sync;`
225			`assign rst_crc_enable = go_rx_crc;`
226	10	mohor
227	11	mohor	`assign bit_de_stuff_set = go_rx_id1;`
228			`assign bit_de_stuff_reset = go_rx_crc_lim;`
229
230
231	10	mohor	`// Rx idle state`
232			`always @ (posedge clk or posedge rst)`
233			`begin`
234			`if (rst)`
235			`rx_idle <= 1'b1;`
236			`else if (reset_mode \| go_rx_id1)`
237			`rx_idle <=#Tp 1'b0;`
238			`else if (go_rx_idle)`
239			`rx_idle <=#Tp 1'b1;`
240			`end`
241
242
243			`// Rx id1 state`
244			`always @ (posedge clk or posedge rst)`
245			`begin`
246			`if (rst)`
247			`rx_id1 <= 1'b0;`
248			`else if (reset_mode \| go_rx_rtr1)`
249			`rx_id1 <=#Tp 1'b0;`
250			`else if (go_rx_id1)`
251			`rx_id1 <=#Tp 1'b1;`
252			`end`
253
254
255			`// Rx rtr1 state`
256			`always @ (posedge clk or posedge rst)`
257			`begin`
258			`if (rst)`
259			`rx_rtr1 <= 1'b0;`
260			`else if (reset_mode \| go_rx_ide)`
261			`rx_rtr1 <=#Tp 1'b0;`
262			`else if (go_rx_rtr1)`
263			`rx_rtr1 <=#Tp 1'b1;`
264			`end`
265
266
267			`// Rx ide state`
268			`always @ (posedge clk or posedge rst)`
269			`begin`
270			`if (rst)`
271			`rx_ide <= 1'b0;`
272			`else if (reset_mode \| go_rx_r0 \| go_rx_id2)`
273			`rx_ide <=#Tp 1'b0;`
274			`else if (go_rx_ide)`
275			`rx_ide <=#Tp 1'b1;`
276			`end`
277
278
279			`// Rx id2 state`
280			`always @ (posedge clk or posedge rst)`
281			`begin`
282			`if (rst)`
283			`rx_id2 <= 1'b0;`
284			`else if (reset_mode \| go_rx_rtr2)`
285			`rx_id2 <=#Tp 1'b0;`
286			`else if (go_rx_id2)`
287			`rx_id2 <=#Tp 1'b1;`
288			`end`
289
290
291			`// Rx rtr2 state`
292			`always @ (posedge clk or posedge rst)`
293			`begin`
294			`if (rst)`
295			`rx_rtr2 <= 1'b0;`
296			`else if (reset_mode \| go_rx_r1)`
297			`rx_rtr2 <=#Tp 1'b0;`
298			`else if (go_rx_rtr2)`
299			`rx_rtr2 <=#Tp 1'b1;`
300			`end`
301
302
303			`// Rx r0 state`
304			`always @ (posedge clk or posedge rst)`
305			`begin`
306			`if (rst)`
307			`rx_r1 <= 1'b0;`
308			`else if (reset_mode \| go_rx_r0)`
309			`rx_r1 <=#Tp 1'b0;`
310			`else if (go_rx_r1)`
311			`rx_r1 <=#Tp 1'b1;`
312			`end`
313
314
315			`// Rx r0 state`
316			`always @ (posedge clk or posedge rst)`
317			`begin`
318			`if (rst)`
319			`rx_r0 <= 1'b0;`
320			`else if (reset_mode \| go_rx_dlc)`
321			`rx_r0 <=#Tp 1'b0;`
322			`else if (go_rx_r0)`
323			`rx_r0 <=#Tp 1'b1;`
324			`end`
325
326
327			`// Rx dlc state`
328			`always @ (posedge clk or posedge rst)`
329			`begin`
330			`if (rst)`
331			`rx_dlc <= 1'b0;`
332			`else if (reset_mode \| go_rx_data \| go_rx_crc)`
333			`rx_dlc <=#Tp 1'b0;`
334			`else if (go_rx_dlc)`
335			`rx_dlc <=#Tp 1'b1;`
336			`end`
337
338
339			`// Rx data state`
340			`always @ (posedge clk or posedge rst)`
341			`begin`
342			`if (rst)`
343			`rx_data <= 1'b0;`
344			`else if (reset_mode \| go_rx_crc)`
345			`rx_data <=#Tp 1'b0;`
346			`else if (go_rx_data)`
347			`rx_data <=#Tp 1'b1;`
348			`end`
349
350
351			`// Rx crc state`
352			`always @ (posedge clk or posedge rst)`
353			`begin`
354			`if (rst)`
355			`rx_crc <= 1'b0;`
356	11	mohor	`else if (reset_mode \| go_rx_crc_lim)`
357	10	mohor	`rx_crc <=#Tp 1'b0;`
358			`else if (go_rx_crc)`
359			`rx_crc <=#Tp 1'b1;`
360			`end`
361
362
363	11	mohor	`// Rx crc delimiter state`
364			`always @ (posedge clk or posedge rst)`
365			`begin`
366			`if (rst)`
367			`rx_crc_lim <= 1'b0;`
368			`else if (reset_mode \| go_rx_ack)`
369			`rx_crc_lim <=#Tp 1'b0;`
370			`else if (go_rx_crc_lim)`
371			`rx_crc_lim <=#Tp 1'b1;`
372			`end`
373
374
375	10	mohor	`// Rx ack state`
376			`always @ (posedge clk or posedge rst)`
377			`begin`
378			`if (rst)`
379			`rx_ack <= 1'b0;`
380	11	mohor	`else if (reset_mode \| go_rx_ack_lim)`
381	10	mohor	`rx_ack <=#Tp 1'b0;`
382			`else if (go_rx_ack)`
383			`rx_ack <=#Tp 1'b1;`
384			`end`
385
386
387	11	mohor	`// Rx ack delimiter state`
388			`always @ (posedge clk or posedge rst)`
389			`begin`
390			`if (rst)`
391			`rx_ack_lim <= 1'b0;`
392			`else if (reset_mode \| go_rx_eof)`
393			`rx_ack_lim <=#Tp 1'b0;`
394			`else if (go_rx_ack_lim)`
395			`rx_ack_lim <=#Tp 1'b1;`
396			`end`
397
398
399	10	mohor	`// Rx eof state`
400			`always @ (posedge clk or posedge rst)`
401			`begin`
402			`if (rst)`
403			`rx_eof <= 1'b0;`
404			`else if (go_rx_idle)`
405			`rx_eof <=#Tp 1'b0;`
406			`else if (go_rx_eof)`
407			`rx_eof <=#Tp 1'b1;`
408			`end`
409
410
411
412
413	11	mohor	`reg rtr1;`
414			`reg ide;`
415			`reg rtr2;`
416			`reg [14:0] crc_in;`
417	10	mohor
418			`// ID register`
419			`always @ (posedge clk or posedge rst)`
420			`begin`
421			`if (rst)`
422			`id <= 0;`
423	11	mohor	`else if (sample_point & (rx_id1 \| rx_id2) & (~bit_de_stuff))`
424	10	mohor	`id <=#Tp {id[27:0], sampled_bit};`
425			`end`
426
427	11	mohor
428			`// rtr1 bit`
429			`always @ (posedge clk or posedge rst)`
430			`begin`
431			`if (rst)`
432			`rtr1 <= 0;`
433			`else if (sample_point & rx_rtr1 & (~bit_de_stuff))`
434			`rtr1 <=#Tp sampled_bit;`
435			`end`
436
437
438			`// rtr2 bit`
439			`always @ (posedge clk or posedge rst)`
440			`begin`
441			`if (rst)`
442			`rtr2 <= 0;`
443			`else if (sample_point & rx_rtr2 & (~bit_de_stuff))`
444			`rtr2 <=#Tp sampled_bit;`
445			`end`
446
447
448			`// ide bit`
449			`always @ (posedge clk or posedge rst)`
450			`begin`
451			`if (rst)`
452			`ide <= 0;`
453			`else if (sample_point & rx_ide & (~bit_de_stuff))`
454			`ide <=#Tp sampled_bit;`
455			`end`
456
457
458	10	mohor	`// Data length`
459			`always @ (posedge clk or posedge rst)`
460			`begin`
461			`if (rst)`
462			`data_len <= 0;`
463			`else if (sample_point & rx_dlc & (~bit_de_stuff))`
464			`data_len <=#Tp {data_len[2:0], sampled_bit};`
465			`end`
466
467
468	11	mohor	`// Data`
469			`reg [7:0] tmp_data;`
470			`reg [7:0] tmp_fifo [0:7];`
471			`always @ (posedge clk or posedge rst)`
472			`begin`
473			`if (rst)`
474			`tmp_data <= 0;`
475			`else if (sample_point & rx_data & (~bit_de_stuff))`
476			`tmp_data <=#Tp {tmp_data[6:0], sampled_bit};`
477			`end`
478
479
480			`reg write_data_to_tmp_fifo;`
481			`always @ (posedge clk or posedge rst)`
482			`begin`
483			`if (rst)`
484			`write_data_to_tmp_fifo <= 0;`
485			`else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))`
486			`write_data_to_tmp_fifo <=#Tp 1'b1;`
487			`else`
488			`write_data_to_tmp_fifo <=#Tp 0;`
489			`end`
490
491
492			`reg [2:0] byte_cnt;`
493			`always @ (posedge clk or posedge rst)`
494			`begin`
495			`if (rst)`
496			`byte_cnt <= 0;`
497			`else if (write_data_to_tmp_fifo)`
498			`byte_cnt <=#Tp byte_cnt + 1;`
499			`else if (sample_point & go_rx_crc_lim)`
500			`byte_cnt <=#Tp 0;`

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