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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_bsp.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.
//
// Revision 1.9  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.8  2003/01/10 17:51:33  mohor
// Temporary version (backup).
//
// Revision 1.7  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.6  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.5  2003/01/08 13:30:31  mohor
// Temp version.
//
// Revision 1.4  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.3  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.2  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_bsp
(
  clk,
  rst,
 
  sample_point,
  sampled_bit,
  sampled_bit_q,
  hard_sync,
  resync,
 
  addr,
  data_out,
 
 
  /* Mode register */
  reset_mode,
  acceptance_filter_mode,
 
  /* Command register */
  release_buffer,
 
  /* Clock Divider register */
  extended_mode,
 
  rx_idle,
 
  /* This section is for BASIC and EXTENDED mode */
  /* Acceptance code register */
  acceptance_code_0,
 
  /* Acceptance mask register */
  acceptance_mask_0,
  /* End: This section is for BASIC and EXTENDED mode */
 
  /* This section is for EXTENDED mode */
  /* Acceptance code register */
  acceptance_code_1,
  acceptance_code_2,
  acceptance_code_3,
 
  /* Acceptance mask register */
  acceptance_mask_1,
  acceptance_mask_2,
  acceptance_mask_3,
  /* End: This section is for EXTENDED mode */
 
  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
  tx_data_0,
  tx_data_1,
  tx_data_2,
  tx_data_3,
  tx_data_4,
  tx_data_5,
  tx_data_6,
  tx_data_7,
  tx_data_8,
  tx_data_9,
  tx_data_10,
  tx_data_11,
  tx_data_12
  /* End: Tx data registers */
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         sample_point;
input         sampled_bit;
input         sampled_bit_q;
input         hard_sync;
input         resync;
input   [7:0] addr;
output  [7:0] data_out;
 
 
input         reset_mode;
input         acceptance_filter_mode;
input         extended_mode;
 
/* Command register */
input         release_buffer;
 
output        rx_idle;
 
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
input   [7:0] acceptance_code_0;
 
/* Acceptance mask register */
input   [7:0] acceptance_mask_0;
 
/* End: This section is for BASIC and EXTENDED mode */
 
 
/* This section is for EXTENDED mode */
/* Acceptance code register */
input   [7:0] acceptance_code_1;
input   [7:0] acceptance_code_2;
input   [7:0] acceptance_code_3;
 
/* Acceptance mask register */
input   [7:0] acceptance_mask_1;
input   [7:0] acceptance_mask_2;
input   [7:0] acceptance_mask_3;
/* End: This section is for EXTENDED mode */
 
  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
input   [7:0] tx_data_0;
input   [7:0] tx_data_1;
input   [7:0] tx_data_2;
input   [7:0] tx_data_3;
input   [7:0] tx_data_4;
input   [7:0] tx_data_5;
input   [7:0] tx_data_6;
input   [7:0] tx_data_7;
input   [7:0] tx_data_8;
input   [7:0] tx_data_9;
input   [7:0] tx_data_10;
input   [7:0] tx_data_11;
input   [7:0] tx_data_12;
  /* End: Tx data registers */
 
 
reg           reset_mode_q;
reg     [5:0] bit_cnt;
 
reg     [3:0] data_len;
reg    [28:0] id;
reg     [2:0] bit_stuff_cnt;
reg           stuff_error;
 
wire          bit_de_stuff;
 
 
/* Rx state machine */
wire          go_rx_idle;
wire          go_rx_id1;
wire          go_rx_rtr1;
wire          go_rx_ide;
wire          go_rx_id2;
wire          go_rx_rtr2;
wire          go_rx_r1;
wire          go_rx_r0;
wire          go_rx_dlc;
wire          go_rx_data;
wire          go_rx_crc;
wire          go_rx_crc_lim;
wire          go_rx_ack;
wire          go_rx_ack_lim;
wire          go_rx_eof;
 
wire          go_crc_enable;
wire          rst_crc_enable;
 
wire          bit_de_stuff_set;
wire          bit_de_stuff_reset;
 
reg           rx_idle;
reg           rx_id1;
reg           rx_rtr1;
reg           rx_ide;
reg           rx_id2;
reg           rx_rtr2;
reg           rx_r1;
reg           rx_r0;
reg           rx_dlc;
reg           rx_data;
reg           rx_crc;
reg           rx_crc_lim;
reg           rx_ack;
reg           rx_ack_lim;
reg           rx_eof;
 
reg           rtr1;
reg           ide;
reg           rtr2;
reg    [14:0] crc_in;
 
reg           crc_enable;
 
reg     [2:0] eof_cnt;
wire   [14:0] calculated_crc;
wire          remote_rq;
wire [3:0]    limited_data_len;
 
assign go_rx_idle     =                   sample_point &  rx_eof  & (eof_cnt == 6);
assign go_rx_id1      =                   sample_point &  rx_idle & (~sampled_bit);
assign go_rx_rtr1     = (~bit_de_stuff) & sample_point &  rx_id1  & (bit_cnt == 10);
assign go_rx_ide      = (~bit_de_stuff) & sample_point &  rx_rtr1;
assign go_rx_id2      = (~bit_de_stuff) & sample_point &  rx_ide  &   sampled_bit;
assign go_rx_rtr2     = (~bit_de_stuff) & sample_point &  rx_id2  & (bit_cnt == 17);
assign go_rx_r1       = (~bit_de_stuff) & sample_point &  rx_rtr2;
assign go_rx_r0       = (~bit_de_stuff) & sample_point & (rx_ide  & (~sampled_bit) | rx_r1);
assign go_rx_dlc      = (~bit_de_stuff) & sample_point &  rx_r0;
assign go_rx_data     = (~bit_de_stuff) & sample_point &  rx_dlc  & (bit_cnt == 3) &  (sampled_bit   |   (|data_len[2:0])) & (~remote_rq);
assign go_rx_crc      = (~bit_de_stuff) & sample_point & (rx_dlc  & (bit_cnt == 3) & ((~sampled_bit) & (~(|data_len[2:0])) | remote_rq) |
                                                          rx_data & (bit_cnt == ((limited_data_len<<3) - 1'b1)));
assign go_rx_crc_lim  =                   sample_point &  rx_crc  & (bit_cnt == 14);
assign go_rx_ack      =                   sample_point &  rx_crc_lim;
assign go_rx_ack_lim  =                   sample_point &  rx_ack;
assign go_rx_eof      =                   sample_point &  rx_ack_lim  | (~reset_mode) & reset_mode_q;
 
assign go_crc_enable  = hard_sync;
assign rst_crc_enable = go_rx_crc;
 
assign bit_de_stuff_set   = go_rx_id1;
assign bit_de_stuff_reset = go_rx_crc_lim;
 
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
assign limited_data_len = (data_len < 8)? data_len : 4'h8;
 
 
// Rx idle state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_idle <= 1'b1;
  else if (reset_mode | go_rx_id1)
    rx_idle <=#Tp 1'b0;
  else if (go_rx_idle)
    rx_idle <=#Tp 1'b1;
end
 
 
// Rx id1 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_id1 <= 1'b0;
  else if (reset_mode | go_rx_rtr1)
    rx_id1 <=#Tp 1'b0;
  else if (go_rx_id1)
    rx_id1 <=#Tp 1'b1;
end
 
 
// Rx rtr1 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_rtr1 <= 1'b0;
  else if (reset_mode | go_rx_ide)
    rx_rtr1 <=#Tp 1'b0;
  else if (go_rx_rtr1)
    rx_rtr1 <=#Tp 1'b1;
end
 
 
// Rx ide state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ide <= 1'b0;
  else if (reset_mode | go_rx_r0 | go_rx_id2)
    rx_ide <=#Tp 1'b0;
  else if (go_rx_ide)
    rx_ide <=#Tp 1'b1;
end
 
 
// Rx id2 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_id2 <= 1'b0;
  else if (reset_mode | go_rx_rtr2)
    rx_id2 <=#Tp 1'b0;
  else if (go_rx_id2)
    rx_id2 <=#Tp 1'b1;
end
 
 
// Rx rtr2 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_rtr2 <= 1'b0;
  else if (reset_mode | go_rx_r1)
    rx_rtr2 <=#Tp 1'b0;
  else if (go_rx_rtr2)
    rx_rtr2 <=#Tp 1'b1;
end
 
 
// Rx r0 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_r1 <= 1'b0;
  else if (reset_mode | go_rx_r0)
    rx_r1 <=#Tp 1'b0;
  else if (go_rx_r1)
    rx_r1 <=#Tp 1'b1;
end
 
 
// Rx r0 state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_r0 <= 1'b0;
  else if (reset_mode | go_rx_dlc)
    rx_r0 <=#Tp 1'b0;
  else if (go_rx_r0)
    rx_r0 <=#Tp 1'b1;
end
 
 
// Rx dlc state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_dlc <= 1'b0;
  else if (reset_mode | go_rx_data | go_rx_crc)
    rx_dlc <=#Tp 1'b0;
  else if (go_rx_dlc)
    rx_dlc <=#Tp 1'b1;
end
 
 
// Rx data state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_data <= 1'b0;
  else if (reset_mode | go_rx_crc)
    rx_data <=#Tp 1'b0;
  else if (go_rx_data)
    rx_data <=#Tp 1'b1;
end
 
 
// Rx crc state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_crc <= 1'b0;
  else if (reset_mode | go_rx_crc_lim)
    rx_crc <=#Tp 1'b0;
  else if (go_rx_crc)
    rx_crc <=#Tp 1'b1;
end
 
 
// Rx crc delimiter state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_crc_lim <= 1'b0;
  else if (reset_mode | go_rx_ack)
    rx_crc_lim <=#Tp 1'b0;
  else if (go_rx_crc_lim)
    rx_crc_lim <=#Tp 1'b1;
end
 
 
// Rx ack state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ack <= 1'b0;
  else if (reset_mode | go_rx_ack_lim)
    rx_ack <=#Tp 1'b0;
  else if (go_rx_ack)
    rx_ack <=#Tp 1'b1;
end
 
 
// Rx ack delimiter state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_ack_lim <= 1'b0;
  else if (reset_mode | go_rx_eof)
    rx_ack_lim <=#Tp 1'b0;
  else if (go_rx_ack_lim)
    rx_ack_lim <=#Tp 1'b1;
end
 
 
// Rx eof state
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rx_eof <= 1'b0;
  else if (go_rx_idle)
    rx_eof <=#Tp 1'b0;
  else if (go_rx_eof)
    rx_eof <=#Tp 1'b1;
end
 
 
// ID register
always @ (posedge clk or posedge rst)
begin
  if (rst)
    id <= 0;
  else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
    id <=#Tp {id[27:0], sampled_bit};
end
 
 
// rtr1 bit
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rtr1 <= 0;
  else if (sample_point & rx_rtr1 & (~bit_de_stuff))
    rtr1 <=#Tp sampled_bit;
end
 
 
// rtr2 bit
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rtr2 <= 0;
  else if (sample_point & rx_rtr2 & (~bit_de_stuff))
    rtr2 <=#Tp sampled_bit;
end
 
 
// ide bit
always @ (posedge clk or posedge rst)
begin
  if (rst)
    ide <= 0;
  else if (sample_point & rx_ide & (~bit_de_stuff))
    ide <=#Tp sampled_bit;
end
 
 
// Data length
always @ (posedge clk or posedge rst)
begin
  if (rst)
    data_len <= 0;
  else if (sample_point & rx_dlc & (~bit_de_stuff))
    data_len <=#Tp {data_len[2:0], sampled_bit};
end
 
 
// Data
reg [7:0] tmp_data;
reg [7:0] tmp_fifo [0:7];
always @ (posedge clk or posedge rst)
begin
  if (rst)
    tmp_data <= 0;
  else if (sample_point & rx_data & (~bit_de_stuff))
    tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
end
 
 
reg write_data_to_tmp_fifo;
always @ (posedge clk or posedge rst)
begin
  if (rst)
    write_data_to_tmp_fifo <= 0;
  else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
    write_data_to_tmp_fifo <=#Tp 1'b1;
  else
    write_data_to_tmp_fifo <=#Tp 0;
end
 
 
reg [2:0] byte_cnt;
always @ (posedge clk or posedge rst)
begin
  if (rst)
    byte_cnt <= 0;
  else if (write_data_to_tmp_fifo)
    byte_cnt <=#Tp byte_cnt + 1;
  else if (sample_point & go_rx_crc_lim)
    byte_cnt <=#Tp 0;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (write_data_to_tmp_fifo)
    tmp_fifo[byte_cnt] <=#Tp tmp_data;
end
 
 
 
// CRC
always @ (posedge clk or posedge rst)
begin
  if (rst)
    crc_in <= 0;
  else if (sample_point & rx_crc & (~bit_de_stuff))
    crc_in <=#Tp {crc_in[13:0], sampled_bit};
end
 
 
// bit_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_cnt <= 0;
  else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc | go_rx_ack | go_rx_eof)
    bit_cnt <=#Tp 0;
  else if (sample_point & (~bit_de_stuff))
    bit_cnt <=#Tp bit_cnt + 1'b1;
end
 
 
// eof_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    eof_cnt <= 0;
  else if (sample_point)
    begin
      if (rx_eof & sampled_bit)
        eof_cnt <=#Tp eof_cnt + 1'b1;
      else
        eof_cnt <=#Tp 0;
    end
end
 
 
// Enabling bit de-stuffing
reg bit_stuff_cnt_en;
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_stuff_cnt_en <= 1'b0;
  else if (bit_de_stuff_set)
    bit_stuff_cnt_en <=#Tp 1'b1;
  else if (bit_de_stuff_reset)
    bit_stuff_cnt_en <=#Tp 1'b0;
end
 
// bit_stuff_cnt
always @ (posedge clk or posedge rst)
begin
  if (rst)
    bit_stuff_cnt <= 1;
  else if (bit_de_stuff_reset)
    bit_stuff_cnt <=#Tp 1;
  else if (sample_point & bit_stuff_cnt_en)
    begin
      if (bit_stuff_cnt == 5)
        bit_stuff_cnt <=#Tp 1;
      else if (sampled_bit == sampled_bit_q)
        bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1;
      else
        bit_stuff_cnt <=#Tp 1;
    end
end
 
 
assign bit_de_stuff = bit_stuff_cnt == 5;
 
 
// stuff_error
always @ (posedge clk or posedge rst)
begin
  if (rst)
    stuff_error <= 0;
  else if (sample_point & (rx_id1) & bit_de_stuff & (sampled_bit == sampled_bit_q))   // Add other stages (data, control, etc.) !!!
    stuff_error <=#Tp 1'b1;
//  else if (reset condition)       // Add reset condition
//    stuff_error <=#Tp 0;
end
 
 
// Generating delayed reset_mode signal
always @ (posedge clk)
begin
  reset_mode_q <=#Tp reset_mode;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    crc_enable <= 1'b0;
  else if (go_crc_enable)
    crc_enable <=#Tp 1'b1;
  else if (reset_mode | rst_crc_enable)
    crc_enable <=#Tp 1'b0;
end
 
 
reg crc_error;
// CRC error generation
always @ (posedge clk or posedge rst)
begin
  if (rst)
    crc_error <= 0;
  else if (go_rx_ack)
    crc_error <=#Tp crc_in != calculated_crc;
  else if (reset_mode | rx_eof)
    crc_error <=#Tp 0;
end
 
 
 
// Instantiation of the RX CRC module
can_crc i_can_crc_rx
(
  .clk(clk),
//  .data(sampled_bit & (~rx_crc)),     // Zeros are shifted in for calculation when we are in crc stage
  .data(sampled_bit ),     // Zeros are shifted in for calculation when we are in crc stage
  .enable(crc_enable & sample_point & (~bit_de_stuff)),
  .initialize(rx_eof),
  .crc(calculated_crc)
);
 
 
 
wire          id_ok;        // If received ID matches ID set in registers
wire          no_byte0;     // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
wire          no_byte1;     // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
 
assign no_byte0 = rtr1 | (data_len<1);
assign no_byte1 = rtr1 | (data_len<2);
 
can_acf i_can_acf
(
  .clk(clk),
  .rst(rst),
 
  .id(id),
 
  /* Mode register */
  .reset_mode(reset_mode),
  .acceptance_filter_mode(acceptance_filter_mode),
 
  // Clock Divider register
  .extended_mode(extended_mode),
 
  /* This section is for BASIC and EXTENDED mode */
  /* Acceptance code register */
  .acceptance_code_0(acceptance_code_0),
 
  /* Acceptance mask register */
  .acceptance_mask_0(acceptance_mask_0),
  /* End: This section is for BASIC and EXTENDED mode */
 
  /* This section is for EXTENDED mode */
  /* Acceptance code register */
  .acceptance_code_1(acceptance_code_1),
  .acceptance_code_2(acceptance_code_2),
  .acceptance_code_3(acceptance_code_3),
 
  /* Acceptance mask register */
  .acceptance_mask_1(acceptance_mask_1),
  .acceptance_mask_2(acceptance_mask_2),
  .acceptance_mask_3(acceptance_mask_3),
  /* End: This section is for EXTENDED mode */
 
  .sample_point(sample_point),
  .go_rx_crc_lim(go_rx_crc_lim),
  .go_rx_idle(go_rx_idle),
 
  .data0(tmp_fifo[0]),
  .data1(tmp_fifo[1]),
  .rtr1(rtr1),
  .rtr2(rtr2),
  .ide(ide),
  .no_byte0(no_byte0),
  .no_byte1(no_byte1),
 
  .id_ok(id_ok)
 
);
 
 
 
reg [3:0]   data_cnt;       // Counting the data bytes that are written to FIFO
reg [2:0]   header_cnt;     // Counting header length
reg         wr_fifo;        // Write data and header to 64-byte fifo
reg [7:0]   data_for_fifo;  // Multiplexed data that is stored to 64-byte fifo
 
 
wire [2:0]  header_len;
wire        storing_header;
wire [3:0]  limited_data_len_minus1;
wire        reset_wr_fifo;
 
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
assign storing_header = header_cnt < header_len;
assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 8)? (data_len -1'b1) : 4'h7);   // - 1 because counter counts from 0
assign reset_wr_fifo = data_cnt == (limited_data_len_minus1 + header_len);
 
 
// Write enable signal for 64-byte rx fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_fifo <= 1'b0;
  else if (reset_wr_fifo)
    wr_fifo <=#Tp 1'b0;
  else if (go_rx_ack_lim & (~extended_mode) & id_ok & (~crc_error))
    wr_fifo <=#Tp 1'b1;
end
 
 
// Header counter. Header length depends on the mode of operation and frame format.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    header_cnt <= 0;
  else if (reset_wr_fifo)
    header_cnt <=#Tp 0;
  else if (wr_fifo & storing_header)
    header_cnt <=#Tp header_cnt + 1;
end
 
 
// Data counter. Length of the data is limited to 8 bytes.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    data_cnt <= 0;
  else if (reset_wr_fifo)
    data_cnt <=#Tp 0;
  else if (wr_fifo)
    data_cnt <=#Tp data_cnt + 1;
end
 
 
// Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
always @ (extended_mode or ide or data_cnt or header_cnt or storing_header or id or rtr1 or rtr2 or data_len or
          tmp_fifo[0] or tmp_fifo[2] or tmp_fifo[4] or tmp_fifo[6] or
          tmp_fifo[1] or tmp_fifo[3] or tmp_fifo[5] or tmp_fifo[7])
begin
  if (storing_header)
    begin
      if (extended_mode)      // extended mode
        begin
          if (ide)              // extended format
            begin
              case (header_cnt)            // synopsys parallel_case synopsys full_case
                4'h0  : data_for_fifo <= {1'b1, rtr2, 2'h0, data_len};
                4'h1  : data_for_fifo <= id[28:21];
                4'h2  : data_for_fifo <= id[20:13];
                4'h3  : data_for_fifo <= id[12:5];
                4'h4  : data_for_fifo <= {id[4:0], 3'h0};
              endcase
            end
          else                  // standard format
            begin
              case (header_cnt)            // synopsys parallel_case synopsys full_case
                4'h0  : data_for_fifo <= {1'b0, rtr1, 2'h0, data_len};
                4'h1  : data_for_fifo <= id[10:3];
                4'h2  : data_for_fifo <= {id[2:0], 5'h0};
              endcase
            end
        end
      else                    // normal mode
        begin
          case (header_cnt)            // synopsys parallel_case synopsys full_case
            4'h0  : data_for_fifo <= id[10:3];
            4'h1  : data_for_fifo <= {id[2:0], rtr1, data_len};
          endcase
        end
    end
  else
    data_for_fifo <= tmp_fifo[data_cnt-header_len];
end
 
 
 
 
// Instantiation of the RX fifo module
can_fifo i_can_fifo
(
  .clk(clk),
  .rst(rst),
 
  .wr(wr_fifo),
 
  .data_in(data_for_fifo),
  .addr(addr),
  .data_out(data_out),
 
  .reset_mode(reset_mode),
  .release_buffer(release_buffer),
  .extended_mode(extended_mode)
 
 
);
 
 
 
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_bsp.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	19	mohor	`// Revision 1.10 2003/01/15 13:16:47 mohor`
49			`// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.`
50			`//`
51	18	mohor	`// Revision 1.9 2003/01/14 12:19:35 mohor`
52			`// rx_fifo is now working.`
53			`//`
54	16	mohor	`// Revision 1.8 2003/01/10 17:51:33 mohor`
55			`// Temporary version (backup).`
56			`//`
57	15	mohor	`// Revision 1.7 2003/01/09 21:54:45 mohor`
58			`// rx fifo added. Not 100 % verified, yet.`
59			`//`
60	14	mohor	`// Revision 1.6 2003/01/09 14:46:58 mohor`
61			`// Temporary files (backup).`
62			`//`
63	13	mohor	`// Revision 1.5 2003/01/08 13:30:31 mohor`
64			`// Temp version.`
65			`//`
66	12	mohor	`// Revision 1.4 2003/01/08 02:10:53 mohor`
67			`// Acceptance filter added.`
68			`//`
69	11	mohor	`// Revision 1.3 2002/12/28 04:13:23 mohor`
70			`// Backup version.`
71			`//`
72	10	mohor	`// Revision 1.2 2002/12/27 00:12:52 mohor`
73			`// Header changed, testbench improved to send a frame (crc still missing).`
74			`//`
75	9	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
76			`// Initial`
77	2	mohor	`//`
78			`//`
79	9	mohor	`//`
80	2	mohor
81			`// synopsys translate_off`
82			`include "timescale.v"
83			`// synopsys translate_on`
84			`include "can_defines.v"
85
86			`module can_bsp`
87			`(`
88			`clk,`
89	10	mohor	`rst,`
90
91			`sample_point,`
92			`sampled_bit,`
93			`sampled_bit_q,`
94	11	mohor	`hard_sync,`
95			`resync,`
96
97	14	mohor	`addr,`
98			`data_out,`
99
100
101	11	mohor	`/* Mode register */`
102	10	mohor	`reset_mode,`
103	11	mohor	`acceptance_filter_mode,`
104
105	15	mohor	`/* Command register */`
106			`release_buffer,`
107
108			`/* Clock Divider register */`
109	11	mohor	`extended_mode,`
110
111			`rx_idle,`
112
113			`/* This section is for BASIC and EXTENDED mode */`
114			`/* Acceptance code register */`
115			`acceptance_code_0,`
116
117			`/* Acceptance mask register */`
118			`acceptance_mask_0,`
119			`/* End: This section is for BASIC and EXTENDED mode */`
120	10	mohor
121	11	mohor	`/* This section is for EXTENDED mode */`
122			`/* Acceptance code register */`
123			`acceptance_code_1,`
124			`acceptance_code_2,`
125			`acceptance_code_3,`
126	10	mohor
127	11	mohor	`/* Acceptance mask register */`
128			`acceptance_mask_1,`
129			`acceptance_mask_2,`
130	18	mohor	`acceptance_mask_3,`
131	11	mohor	`/* End: This section is for EXTENDED mode */`
132	10	mohor
133	18	mohor	`/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */`
134			`tx_data_0,`
135			`tx_data_1,`
136			`tx_data_2,`
137			`tx_data_3,`
138			`tx_data_4,`
139			`tx_data_5,`
140			`tx_data_6,`
141			`tx_data_7,`
142			`tx_data_8,`
143			`tx_data_9,`
144			`tx_data_10,`
145			`tx_data_11,`
146			`tx_data_12`
147			`/* End: Tx data registers */`
148
149	2	mohor	`);`
150
151			`parameter Tp = 1;`
152
153	10	mohor	`input clk;`
154			`input rst;`
155			`input sample_point;`
156			`input sampled_bit;`
157			`input sampled_bit_q;`
158	11	mohor	`input hard_sync;`
159			`input resync;`
160	14	mohor	`input [7:0] addr;`
161			`output [7:0] data_out;`
162	11	mohor
163	14	mohor
164	10	mohor	`input reset_mode;`
165	11	mohor	`input acceptance_filter_mode;`
166			`input extended_mode;`
167	2	mohor
168	15	mohor	`/* Command register */`
169			`input release_buffer;`
170	11	mohor
171	10	mohor	`output rx_idle;`
172	2	mohor
173	11	mohor	`/* This section is for BASIC and EXTENDED mode */`
174			`/* Acceptance code register */`
175			`input [7:0] acceptance_code_0;`
176
177			`/* Acceptance mask register */`
178			`input [7:0] acceptance_mask_0;`
179
180			`/* End: This section is for BASIC and EXTENDED mode */`
181
182
183			`/* This section is for EXTENDED mode */`
184			`/* Acceptance code register */`
185			`input [7:0] acceptance_code_1;`
186			`input [7:0] acceptance_code_2;`
187			`input [7:0] acceptance_code_3;`
188
189			`/* Acceptance mask register */`
190			`input [7:0] acceptance_mask_1;`
191			`input [7:0] acceptance_mask_2;`
192			`input [7:0] acceptance_mask_3;`
193			`/* End: This section is for EXTENDED mode */`
194
195	18	mohor	`/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */`
196			`input [7:0] tx_data_0;`
197			`input [7:0] tx_data_1;`
198			`input [7:0] tx_data_2;`
199			`input [7:0] tx_data_3;`
200			`input [7:0] tx_data_4;`
201			`input [7:0] tx_data_5;`
202			`input [7:0] tx_data_6;`
203			`input [7:0] tx_data_7;`
204			`input [7:0] tx_data_8;`
205			`input [7:0] tx_data_9;`
206			`input [7:0] tx_data_10;`
207			`input [7:0] tx_data_11;`
208			`input [7:0] tx_data_12;`
209			`/* End: Tx data registers */`
210	11	mohor
211
212	10	mohor	`reg reset_mode_q;`
213			`reg [5:0] bit_cnt;`
214	2	mohor
215	10	mohor	`reg [3:0] data_len;`
216			`reg [28:0] id;`
217			`reg [2:0] bit_stuff_cnt;`
218			`reg stuff_error;`
219
220			`wire bit_de_stuff;`
221
222
223			`/* Rx state machine */`
224			`wire go_rx_idle;`
225			`wire go_rx_id1;`
226			`wire go_rx_rtr1;`
227			`wire go_rx_ide;`
228			`wire go_rx_id2;`
229			`wire go_rx_rtr2;`
230			`wire go_rx_r1;`
231			`wire go_rx_r0;`
232			`wire go_rx_dlc;`
233			`wire go_rx_data;`
234			`wire go_rx_crc;`
235	11	mohor	`wire go_rx_crc_lim;`
236	10	mohor	`wire go_rx_ack;`
237	11	mohor	`wire go_rx_ack_lim;`
238	10	mohor	`wire go_rx_eof;`
239
240	11	mohor	`wire go_crc_enable;`
241			`wire rst_crc_enable;`
242
243			`wire bit_de_stuff_set;`
244			`wire bit_de_stuff_reset;`
245
246	10	mohor	`reg rx_idle;`
247			`reg rx_id1;`
248			`reg rx_rtr1;`
249			`reg rx_ide;`
250			`reg rx_id2;`
251			`reg rx_rtr2;`
252			`reg rx_r1;`
253			`reg rx_r0;`
254			`reg rx_dlc;`
255			`reg rx_data;`
256			`reg rx_crc;`
257	11	mohor	`reg rx_crc_lim;`
258	10	mohor	`reg rx_ack;`
259	11	mohor	`reg rx_ack_lim;`
260	10	mohor	`reg rx_eof;`
261
262	19	mohor	`reg rtr1;`
263			`reg ide;`
264			`reg rtr2;`
265			`reg [14:0] crc_in;`
266
267	11	mohor	`reg crc_enable;`
268
269	10	mohor	`reg [2:0] eof_cnt;`
270	11	mohor	`wire [14:0] calculated_crc;`
271	19	mohor	`wire remote_rq;`
272			`wire [3:0] limited_data_len;`
273	10	mohor
274	11	mohor	`assign go_rx_idle = sample_point & rx_eof & (eof_cnt == 6);`
275			`assign go_rx_id1 = sample_point & rx_idle & (~sampled_bit);`
276			`assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt == 10);`
277			`assign go_rx_ide = (~bit_de_stuff) & sample_point & rx_rtr1;`
278			`assign go_rx_id2 = (~bit_de_stuff) & sample_point & rx_ide & sampled_bit;`
279			`assign go_rx_rtr2 = (~bit_de_stuff) & sample_point & rx_id2 & (bit_cnt == 17);`
280			`assign go_rx_r1 = (~bit_de_stuff) & sample_point & rx_rtr2;`
281			`assign go_rx_r0 = (~bit_de_stuff) & sample_point & (rx_ide & (~sampled_bit) \| rx_r1);`
282			`assign go_rx_dlc = (~bit_de_stuff) & sample_point & rx_r0;`
283	19	mohor	`assign go_rx_data = (~bit_de_stuff) & sample_point & rx_dlc & (bit_cnt == 3) & (sampled_bit \| (\|data_len[2:0])) & (~remote_rq);`
284			`assign go_rx_crc = (~bit_de_stuff) & sample_point & (rx_dlc & (bit_cnt == 3) & ((~sampled_bit) & (~(\|data_len[2:0])) \| remote_rq) \|`
285			`rx_data & (bit_cnt == ((limited_data_len<<3) - 1'b1)));`
286	11	mohor	`assign go_rx_crc_lim = sample_point & rx_crc & (bit_cnt == 14);`
287			`assign go_rx_ack = sample_point & rx_crc_lim;`
288			`assign go_rx_ack_lim = sample_point & rx_ack;`
289			`assign go_rx_eof = sample_point & rx_ack_lim \| (~reset_mode) & reset_mode_q;`
290	10	mohor
291	11	mohor	`assign go_crc_enable = hard_sync;`
292			`assign rst_crc_enable = go_rx_crc;`
293	10	mohor
294	11	mohor	`assign bit_de_stuff_set = go_rx_id1;`
295			`assign bit_de_stuff_reset = go_rx_crc_lim;`
296
297	19	mohor	`assign remote_rq = ((~ide) & rtr1) \| (ide & rtr2);`
298			`assign limited_data_len = (data_len < 8)? data_len : 4'h8;`
299	11	mohor
300	19	mohor
301	10	mohor	`// Rx idle state`
302			`always @ (posedge clk or posedge rst)`
303			`begin`
304			`if (rst)`
305			`rx_idle <= 1'b1;`
306			`else if (reset_mode \| go_rx_id1)`
307			`rx_idle <=#Tp 1'b0;`
308			`else if (go_rx_idle)`
309			`rx_idle <=#Tp 1'b1;`
310			`end`
311
312
313			`// Rx id1 state`
314			`always @ (posedge clk or posedge rst)`
315			`begin`
316			`if (rst)`
317			`rx_id1 <= 1'b0;`
318			`else if (reset_mode \| go_rx_rtr1)`
319			`rx_id1 <=#Tp 1'b0;`
320			`else if (go_rx_id1)`
321			`rx_id1 <=#Tp 1'b1;`
322			`end`
323
324
325			`// Rx rtr1 state`
326			`always @ (posedge clk or posedge rst)`
327			`begin`
328			`if (rst)`
329			`rx_rtr1 <= 1'b0;`
330			`else if (reset_mode \| go_rx_ide)`
331			`rx_rtr1 <=#Tp 1'b0;`
332			`else if (go_rx_rtr1)`
333			`rx_rtr1 <=#Tp 1'b1;`
334			`end`
335
336
337			`// Rx ide state`
338			`always @ (posedge clk or posedge rst)`
339			`begin`
340			`if (rst)`
341			`rx_ide <= 1'b0;`
342			`else if (reset_mode \| go_rx_r0 \| go_rx_id2)`
343			`rx_ide <=#Tp 1'b0;`
344			`else if (go_rx_ide)`
345			`rx_ide <=#Tp 1'b1;`
346			`end`
347
348
349			`// Rx id2 state`
350			`always @ (posedge clk or posedge rst)`
351			`begin`
352			`if (rst)`
353			`rx_id2 <= 1'b0;`
354			`else if (reset_mode \| go_rx_rtr2)`
355			`rx_id2 <=#Tp 1'b0;`
356			`else if (go_rx_id2)`
357			`rx_id2 <=#Tp 1'b1;`
358			`end`
359
360
361			`// Rx rtr2 state`
362			`always @ (posedge clk or posedge rst)`
363			`begin`
364			`if (rst)`
365			`rx_rtr2 <= 1'b0;`
366			`else if (reset_mode \| go_rx_r1)`
367			`rx_rtr2 <=#Tp 1'b0;`
368			`else if (go_rx_rtr2)`
369			`rx_rtr2 <=#Tp 1'b1;`
370			`end`
371
372
373			`// Rx r0 state`
374			`always @ (posedge clk or posedge rst)`
375			`begin`
376			`if (rst)`
377			`rx_r1 <= 1'b0;`
378			`else if (reset_mode \| go_rx_r0)`
379			`rx_r1 <=#Tp 1'b0;`
380			`else if (go_rx_r1)`
381			`rx_r1 <=#Tp 1'b1;`
382			`end`
383
384
385			`// Rx r0 state`
386			`always @ (posedge clk or posedge rst)`
387			`begin`
388			`if (rst)`
389			`rx_r0 <= 1'b0;`
390			`else if (reset_mode \| go_rx_dlc)`
391			`rx_r0 <=#Tp 1'b0;`
392			`else if (go_rx_r0)`
393			`rx_r0 <=#Tp 1'b1;`
394			`end`
395
396
397			`// Rx dlc state`
398			`always @ (posedge clk or posedge rst)`
399			`begin`
400			`if (rst)`
401			`rx_dlc <= 1'b0;`
402			`else if (reset_mode \| go_rx_data \| go_rx_crc)`
403			`rx_dlc <=#Tp 1'b0;`
404			`else if (go_rx_dlc)`
405			`rx_dlc <=#Tp 1'b1;`
406			`end`
407
408
409			`// Rx data state`
410			`always @ (posedge clk or posedge rst)`
411			`begin`
412			`if (rst)`
413			`rx_data <= 1'b0;`
414			`else if (reset_mode \| go_rx_crc)`
415			`rx_data <=#Tp 1'b0;`
416			`else if (go_rx_data)`
417			`rx_data <=#Tp 1'b1;`
418			`end`
419
420
421			`// Rx crc state`
422			`always @ (posedge clk or posedge rst)`
423			`begin`
424			`if (rst)`
425			`rx_crc <= 1'b0;`
426	11	mohor	`else if (reset_mode \| go_rx_crc_lim)`
427	10	mohor	`rx_crc <=#Tp 1'b0;`
428			`else if (go_rx_crc)`
429			`rx_crc <=#Tp 1'b1;`
430			`end`
431
432
433	11	mohor	`// Rx crc delimiter state`
434			`always @ (posedge clk or posedge rst)`
435			`begin`
436			`if (rst)`
437			`rx_crc_lim <= 1'b0;`
438			`else if (reset_mode \| go_rx_ack)`
439			`rx_crc_lim <=#Tp 1'b0;`
440			`else if (go_rx_crc_lim)`
441			`rx_crc_lim <=#Tp 1'b1;`
442			`end`
443
444
445	10	mohor	`// Rx ack state`
446			`always @ (posedge clk or posedge rst)`
447			`begin`
448			`if (rst)`
449			`rx_ack <= 1'b0;`
450	11	mohor	`else if (reset_mode \| go_rx_ack_lim)`
451	10	mohor	`rx_ack <=#Tp 1'b0;`
452			`else if (go_rx_ack)`
453			`rx_ack <=#Tp 1'b1;`
454			`end`
455
456
457	11	mohor	`// Rx ack delimiter state`
458			`always @ (posedge clk or posedge rst)`
459			`begin`
460			`if (rst)`
461			`rx_ack_lim <= 1'b0;`
462			`else if (reset_mode \| go_rx_eof)`
463			`rx_ack_lim <=#Tp 1'b0;`
464			`else if (go_rx_ack_lim)`
465			`rx_ack_lim <=#Tp 1'b1;`
466			`end`
467
468
469	10	mohor	`// Rx eof state`
470			`always @ (posedge clk or posedge rst)`
471			`begin`
472			`if (rst)`
473			`rx_eof <= 1'b0;`
474			`else if (go_rx_idle)`
475			`rx_eof <=#Tp 1'b0;`
476			`else if (go_rx_eof)`
477			`rx_eof <=#Tp 1'b1;`
478			`end`
479
480
481			`// ID register`
482			`always @ (posedge clk or posedge rst)`
483			`begin`
484			`if (rst)`
485			`id <= 0;`
486	11	mohor	`else if (sample_point & (rx_id1 \| rx_id2) & (~bit_de_stuff))`
487	10	mohor	`id <=#Tp {id[27:0], sampled_bit};`
488			`end`
489
490	11	mohor
491			`// rtr1 bit`
492			`always @ (posedge clk or posedge rst)`
493			`begin`
494			`if (rst)`
495			`rtr1 <= 0;`
496			`else if (sample_point & rx_rtr1 & (~bit_de_stuff))`
497			`rtr1 <=#Tp sampled_bit;`
498			`end`
499
500

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