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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  can_bsp.v                                                   ////

////                                                              ////

////                                                              ////

////  This file is part of the CAN Protocol Controller            ////

////  http://www.opencores.org/projects/can/                      ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////       Igor Mohor                                             ////

////       igorm@opencores.org                                    ////

////                                                              ////

////                                                              ////

////  All additional information is available in the README.txt   ////

////  file.                                                       ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2002, 2003 Authors                             ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//// The CAN protocol is developed by Robert Bosch GmbH and       ////

//// protected by patents. Anybody who wants to implement this    ////

//// CAN IP core on silicon has to obtain a CAN protocol license  ////

//// from Bosch.                                                  ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.21  2003/02/11 00:56:06  mohor

// Wishbone interface added.

//

// Revision 1.20  2003/02/10 16:02:11  mohor

// CAN is working according to the specification. WB interface and more

// registers (status, IRQ, ...) needs to be added.

//

// Revision 1.19  2003/02/09 18:40:29  mohor

// Overload fixed. Hard synchronization also enabled at the last bit of

// interframe.

//

// Revision 1.18  2003/02/09 02:24:33  mohor

// Bosch license warning added. Error counters finished. Overload frames

// still need to be fixed.

//

// Revision 1.17  2003/02/04 17:24:41  mohor

// Backup.

//

// Revision 1.16  2003/02/04 14:34:52  mohor

// *** empty log message ***

//

// Revision 1.15  2003/01/31 01:13:37  mohor

// backup.

//

// Revision 1.14  2003/01/16 13:36:19  mohor

// Form error supported. When receiving messages, last bit of the end-of-frame

// does not generate form error. Receiver goes to the idle mode one bit sooner.

// (CAN specification ver 2.0, part B, page 57).

//

// Revision 1.13  2003/01/15 21:59:45  mohor

// Data is stored to fifo at the end of ack stage.

//

// Revision 1.12  2003/01/15 21:05:11  mohor

// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).

//

// Revision 1.11  2003/01/15 14:40:23  mohor

// RX state machine fixed to receive "remote request" frames correctly.

// No data bytes are written to fifo when such frames are received.

//

// Revision 1.10  2003/01/15 13:16:47  mohor

// When a frame with "remote request" is received, no data is stored to

// fifo, just the frame information (identifier, ...). Data length that

// is stored is the received data length and not the actual data length

// that is stored to fifo.

//

// Revision 1.9  2003/01/14 12:19:35  mohor

// rx_fifo is now working.

//

// Revision 1.8  2003/01/10 17:51:33  mohor

// Temporary version (backup).

//

// Revision 1.7  2003/01/09 21:54:45  mohor

// rx fifo added. Not 100 % verified, yet.

//

// Revision 1.6  2003/01/09 14:46:58  mohor

// Temporary files (backup).

//

// Revision 1.5  2003/01/08 13:30:31  mohor

// Temp version.

//

// Revision 1.4  2003/01/08 02:10:53  mohor

// Acceptance filter added.

//

// Revision 1.3  2002/12/28 04:13:23  mohor

// Backup version.

//

// Revision 1.2  2002/12/27 00:12:52  mohor

// Header changed, testbench improved to send a frame (crc still missing).

//

// Revision 1.1.1.1  2002/12/20 16:39:21  mohor

// Initial

//

//

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "can_defines.v"

module can_bsp

(

  clk,

  rst,

  sample_point,

  sampled_bit,

  sampled_bit_q,

  tx_point,

  hard_sync,

  addr,

  data_out,

  /* Mode register */

  reset_mode,

  acceptance_filter_mode,

  /* Command register */

  release_buffer,

  tx_request,

  abort_tx,

  /* Clock Divider register */

  extended_mode,

  rx_idle,

  transmitting,

  last_bit_of_inter,

  /* This section is for BASIC and EXTENDED mode */

  /* Acceptance code register */

  acceptance_code_0,

  /* Acceptance mask register */

  acceptance_mask_0,

  /* End: This section is for BASIC and EXTENDED mode */

  /* This section is for EXTENDED mode */

  /* Acceptance code register */

  acceptance_code_1,

  acceptance_code_2,

  acceptance_code_3,

  /* Acceptance mask register */

  acceptance_mask_1,

  acceptance_mask_2,

  acceptance_mask_3,

  /* End: This section is for EXTENDED mode */

  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */

  tx_data_0,

  tx_data_1,

  tx_data_2,

  tx_data_3,

  tx_data_4,

  tx_data_5,

  tx_data_6,

  tx_data_7,

  tx_data_8,

  tx_data_9,

  tx_data_10,

  tx_data_11,

  tx_data_12,

  /* End: Tx data registers */

  /* Tx signal */

  tx,

  tx_oen

);

parameter Tp = 1;

input         clk;

input         rst;

input         sample_point;

input         sampled_bit;

input         sampled_bit_q;

input         tx_point;

input         hard_sync;

input   [7:0] addr;

output  [7:0] data_out;

input         reset_mode;

input         acceptance_filter_mode;

input         extended_mode;

/* Command register */

input         release_buffer;

input         tx_request;

input         abort_tx;

output        rx_idle;

output        transmitting;

output        last_bit_of_inter;

/* This section is for BASIC and EXTENDED mode */

/* Acceptance code register */

input   [7:0] acceptance_code_0;

/* Acceptance mask register */

input   [7:0] acceptance_mask_0;

/* End: This section is for BASIC and EXTENDED mode */

/* This section is for EXTENDED mode */

/* Acceptance code register */

input   [7:0] acceptance_code_1;

input   [7:0] acceptance_code_2;

input   [7:0] acceptance_code_3;

/* Acceptance mask register */

input   [7:0] acceptance_mask_1;

input   [7:0] acceptance_mask_2;

input   [7:0] acceptance_mask_3;

/* End: This section is for EXTENDED mode */

/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */

input   [7:0] tx_data_0;

input   [7:0] tx_data_1;

input   [7:0] tx_data_2;

input   [7:0] tx_data_3;

input   [7:0] tx_data_4;

input   [7:0] tx_data_5;

input   [7:0] tx_data_6;

input   [7:0] tx_data_7;

input   [7:0] tx_data_8;

input   [7:0] tx_data_9;

input   [7:0] tx_data_10;

input   [7:0] tx_data_11;

input   [7:0] tx_data_12;

/* End: Tx data registers */

/* Tx signal */

output        tx;

output        tx_oen;

reg           reset_mode_q;

reg     [5:0] bit_cnt;

reg     [3:0] data_len;

reg    [28:0] id;

reg     [2:0] bit_stuff_cnt;

reg     [2:0] bit_stuff_cnt_tx;

reg           tx_point_q;

reg           rx_idle;

reg           rx_id1;

reg           rx_rtr1;

reg           rx_ide;

reg           rx_id2;

reg           rx_rtr2;

reg           rx_r1;

reg           rx_r0;

reg           rx_dlc;

reg           rx_data;

reg           rx_crc;

reg           rx_crc_lim;

reg           rx_ack;

reg           rx_ack_lim;

reg           rx_eof;

reg           rx_inter;

reg           rtr1;

reg           ide;

reg           rtr2;

reg    [14:0] crc_in;

reg     [7:0] tmp_data;

reg     [7:0] tmp_fifo [0:7];

reg           write_data_to_tmp_fifo;

reg     [2:0] byte_cnt;

reg           bit_stuff_cnt_en;

reg           crc_enable;

reg     [2:0] eof_cnt;

reg     [2:0] passive_cnt;

reg           transmitting;

reg           error_frame;

reg           error_frame_q;

reg           enable_error_cnt2;

reg     [2:0] error_cnt1;

reg     [2:0] error_cnt2;

reg     [2:0] delayed_dominant_cnt;

reg           enable_overload_cnt2;

reg           overload_frame;

reg           overload_frame_blocked;

reg     [2:0] overload_cnt1;

reg     [2:0] overload_cnt2;

reg           tx;

reg           crc_err;

reg           priority_lost;

reg           tx_q;

reg           need_to_tx;   // When the CAN core has something to transmit and a dominant bit is sampled at the third bit

reg     [3:0] data_cnt;     // Counting the data bytes that are written to FIFO

reg     [2:0] header_cnt;   // Counting header length

reg           wr_fifo;      // Write data and header to 64-byte fifo

reg     [7:0] data_for_fifo;// Multiplexed data that is stored to 64-byte fifo

reg     [5:0] tx_pointer;

reg           tx_bit;

reg           tx_state;

reg           transmitter;

reg           finish_msg;

reg     [9:0] rx_err_cnt;

reg     [9:0] tx_err_cnt;

reg           rx_err_cnt_blocked;

reg    [10:0] recessive_cnt;

reg           node_error_passive;

reg           node_bus_off;

reg           ack_err_latched;

reg           bit_err_latched;

reg           stuff_err_latched;

reg           form_err_latched;

reg           rule5;

reg           rule3_exc1_1;

reg           rule3_exc1_2;

reg           rule3_exc2;

reg           suspend;

reg           susp_cnt_en;

reg     [2:0] susp_cnt;

reg           go_error_frame_q;

reg           error_flag_over_blocked;

wire          bit_de_stuff;

wire          bit_de_stuff_tx;

/* Rx state machine */

wire          go_rx_idle;

wire          go_rx_id1;

wire          go_rx_rtr1;

wire          go_rx_ide;

wire          go_rx_id2;

wire          go_rx_rtr2;

wire          go_rx_r1;

wire          go_rx_r0;

wire          go_rx_dlc;

wire          go_rx_data;

wire          go_rx_crc;

wire          go_rx_crc_lim;

wire          go_rx_ack;

wire          go_rx_ack_lim;

wire          go_rx_eof;

wire          go_error_frame;

wire          go_overload_frame;

wire          go_rx_inter;

wire          go_crc_enable;

wire          rst_crc_enable;

wire          bit_de_stuff_set;

wire          bit_de_stuff_reset;

wire          go_early_tx;

wire          go_tx;

wire   [14:0] calculated_crc;

wire   [15:0] r_calculated_crc;

wire          remote_rq;

wire    [3:0] limited_data_len;

wire          form_err;

wire          set_form_error;

wire          error_frame_ended;

wire          overload_frame_ended;

wire          bit_err;

wire          ack_err;

wire          stuff_err;

                                    // of intermission, it starts reading the identifier (and transmitting its own).

wire          overload_needed = 0;  // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to

                                    // be send in a row. This is not implemented because host can not send an overload request. FIX ME !!!!

wire          id_ok;                // If received ID matches ID set in registers

wire          no_byte0;             // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.

wire          no_byte1;             // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.

wire    [2:0] header_len;

wire          storing_header;

wire    [3:0] limited_data_len_minus1;

wire          reset_wr_fifo;

wire          err;

wire          tx_successful;

wire          recessive_cnt_ok;

wire          arbitration_field;

wire   [18:0] basic_chain;

wire   [63:0] basic_chain_data;

wire   [18:0] extended_chain_std;

wire   [38:0] extended_chain_ext;

wire   [63:0] extended_chain_data;

wire          rst_tx_pointer;

wire    [7:0] r_tx_data_0;

wire    [7:0] r_tx_data_1;

wire    [7:0] r_tx_data_2;

wire    [7:0] r_tx_data_3;

wire    [7:0] r_tx_data_4;

wire    [7:0] r_tx_data_5;

wire    [7:0] r_tx_data_6;

wire    [7:0] r_tx_data_7;

wire    [7:0] r_tx_data_8;

wire    [7:0] r_tx_data_9;

wire    [7:0] r_tx_data_10;

wire    [7:0] r_tx_data_11;

wire    [7:0] r_tx_data_12;

wire          send_ack;

wire          bit_err_exc1;

wire          bit_err_exc2;

wire          bit_err_exc3;

wire          bit_err_exc4;

wire          bit_err_exc5;

wire          error_flag_over;

wire          overload_flag_over;

assign go_rx_idle     =                   sample_point &  sampled_bit & last_bit_of_inter;

assign go_rx_id1      =                   sample_point &  (~sampled_bit) & (rx_idle | last_bit_of_inter);

assign go_rx_rtr1     = (~bit_de_stuff) & sample_point &  rx_id1  & (bit_cnt == 10);

assign go_rx_ide      = (~bit_de_stuff) & sample_point &  rx_rtr1;

assign go_rx_id2      = (~bit_de_stuff) & sample_point &  rx_ide  &   sampled_bit;

assign go_rx_rtr2     = (~bit_de_stuff) & sample_point &  rx_id2  & (bit_cnt == 17);

assign go_rx_r1       = (~bit_de_stuff) & sample_point &  rx_rtr2;

assign go_rx_r0       = (~bit_de_stuff) & sample_point & (rx_ide  & (~sampled_bit) | rx_r1);

assign go_rx_dlc      = (~bit_de_stuff) & sample_point &  rx_r0;

assign go_rx_data     = (~bit_de_stuff) & sample_point &  rx_dlc  & (bit_cnt == 3) &  (sampled_bit   |   (|data_len[2:0])) & (~remote_rq);

assign go_rx_crc      = (~bit_de_stuff) & sample_point & (rx_dlc  & (bit_cnt == 3) & ((~sampled_bit) & (~(|data_len[2:0])) | remote_rq) |

                                                          rx_data & (bit_cnt == ((limited_data_len<<3) - 1'b1)));

assign go_rx_crc_lim  = (~bit_de_stuff) & sample_point &  rx_crc  & (bit_cnt == 14);

assign go_rx_ack      =                   sample_point &  rx_crc_lim;

assign go_rx_ack_lim  =                   sample_point &  rx_ack;

assign go_rx_eof      =                   sample_point &  rx_ack_lim  | (~reset_mode) & reset_mode_q;

assign go_rx_inter    =                 ((sample_point &  rx_eof  & (eof_cnt == 6)) | error_frame_ended | overload_frame_ended) & (~overload_needed);

assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));

assign error_frame_ended = (error_cnt2 == 7) & tx_point;

assign overload_frame_ended = (overload_cnt2 == 7) & tx_point;

assign go_overload_frame = (   ((sample_point &  rx_eof  & (eof_cnt == 6)) | error_frame_ended | overload_frame_ended) & overload_needed |

                               sample_point & (~sampled_bit) & rx_inter & (bit_cnt < 2)                                                  |

                               sample_point & (~sampled_bit) & ((error_cnt2 == 7) | (overload_cnt2 == 7))

                           )

                           & (~overload_frame_blocked)

                           ;

assign go_crc_enable  = hard_sync | go_tx;

assign rst_crc_enable = go_rx_crc;

assign bit_de_stuff_set   = go_rx_id1 & (~go_error_frame);

assign bit_de_stuff_reset = go_rx_crc_lim | reset_mode | go_error_frame | go_overload_frame;

assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);

assign limited_data_len = (data_len < 8)? data_len : 4'h8;

assign ack_err = rx_ack & sample_point & sampled_bit & tx_state;

assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx !== sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5);

assign bit_err_exc1 = tx_state & arbitration_field & tx;

assign bit_err_exc2 = rx_ack & tx;

assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 7);

assign bit_err_exc4 = (error_frame & (error_cnt1 == 7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 7) & (~enable_overload_cnt2));

assign bit_err_exc5 = (error_frame & (error_cnt2 == 7)) | (overload_frame & (overload_cnt2 == 7));

assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;

assign last_bit_of_inter = rx_inter & (bit_cnt == 2);

// Rx idle state

always @ (posedge clk or posedge rst)

begin

  if (rst)

    rx_idle <= 1'b0;

  else if (reset_mode | go_rx_id1 | error_frame)

    rx_idle <=#Tp 1'b0;

  else if (go_rx_idle)

    rx_idle <=#Tp 1'b1;

end

// Rx id1 state

always @ (posedge clk or posedge rst)

begin

  if (rst)

    rx_id1 <= 1'b0;

  else if (reset_mode | go_rx_rtr1 | error_frame)

    rx_id1 <=#Tp 1'b0;

  else if (go_rx_id1)

    rx_id1 <=#Tp 1'b1;

end

// Rx rtr1 state

always @ (posedge clk or posedge rst)

begin

  if (rst)

    rx_rtr1 <= 1'b0;

  else if (reset_mode | go_rx_ide | error_frame)

    rx_rtr1 <=#Tp 1'b0;

  else if (go_rx_rtr1)

    rx_rtr1 <=#Tp 1'b1;

end

// Rx ide state

always @ (posedge clk or posedge rst)

begin

  if (rst)

    rx_ide <= 1'b0;

  else if (reset_mode | go_rx_r0 | go_rx_id2 | error_frame)

    rx_ide <=#Tp 1'b0;

  else if (go_rx_ide)

    rx_ide <=#Tp 1'b1;

end

// Rx id2 state

always @ (posedge clk or posedge rst)

begin

  if (rst)

    rx_id2 <= 1'b0;

  else if (reset_mode | go_rx_rtr2 | error_frame)

    rx_id2 <=#Tp 1'b0;

  else if (go_rx_id2)

    rx_id2 <=#Tp 1'b1;

end

// Rx rtr2 state

always @ (posedge clk or posedge rst)

begin

  if (rst)

    rx_rtr2 <= 1'b0;

  else if (reset_mode | go_rx_r1 | error_frame)

    rx_rtr2 <=#Tp 1'b0;

  else if (go_rx_rtr2)

    rx_rtr2 <=#Tp 1'b1;

end

// Rx r0 state

always @ (posedge clk or posedge rst)

begin

  if (rst)

    rx_r1 <= 1'b0;

  else if (reset_mode | go_rx_r0 | error_frame)

    rx_r1 <=#Tp 1'b0;

  else if (go_rx_r1)

    rx_r1 <=#Tp 1'b1;

end

// Rx r0 state

always @ (posedge clk or posedge rst)

begin

  if (rst)

    rx_r0 <= 1'b0;

  else if (reset_mode | go_rx_dlc | error_frame)

    rx_r0 <=#Tp 1'b0;

  else if (go_rx_r0)

    rx_r0 <=#Tp 1'b1;

end

// Rx dlc state

always @ (posedge clk or posedge rst)

begin

  if (rst)

    rx_dlc <= 1'b0;

  else if (reset_mode | go_rx_data | go_rx_crc | error_frame)

    rx_dlc <=#Tp 1'b0;

  else if (go_rx_dlc)

    rx_dlc <=#Tp 1'b1;

end

// Rx data state

always @ (posedge clk or posedge rst)

begin

  if (rst)

    rx_data <= 1'b0;

  else if (reset_mode | go_rx_crc | error_frame)

    rx_data <=#Tp 1'b0;

  else if (go_rx_data)

    rx_data <=#Tp 1'b1;

end

// Rx crc state

always @ (posedge clk or posedge rst)

begin

  if (rst)

    rx_crc <= 1'b0;

  else if (reset_mode | go_rx_crc_lim | error_frame)

    rx_crc <=#Tp 1'b0;

  else if (go_rx_crc)

    rx_crc <=#Tp 1'b1;

end

// Rx crc delimiter state

always @ (posedge clk or posedge rst)

begin

  if (rst)

    rx_crc_lim <= 1'b0;