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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.19  2003/06/20 14:28:20  mohor
// When hard_sync or resync occure we need to go to seg1 segment. Going to
// sync segment is in that case blocked.
//
// Revision 1.18  2003/06/17 15:53:33  mohor
// clk_cnt reduced from [8:0] to [6:0].
//
// Revision 1.17  2003/06/17 14:32:17  mohor
// Removed few signals.
//
// Revision 1.16  2003/06/16 13:57:58  mohor
// tx_point generated one clk earlier. rx_i registered. Data corrected when
// using extended mode.
//
// Revision 1.15  2003/06/13 15:02:24  mohor
// Synchronization is also needed when transmitting a message.
//
// Revision 1.14  2003/06/13 14:55:11  mohor
// Counters width changed.
//
// Revision 1.13  2003/06/11 14:21:35  mohor
// When switching to tx, sync stage is overjumped.
//
// Revision 1.12  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.11  2003/02/09 18:40:29  mohor
// Overload fixed. Hard synchronization also enabled at the last bit of
// interframe.
//
// Revision 1.10  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.9  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.8  2003/01/10 17:51:34  mohor
// Temporary version (backup).
//
// Revision 1.7  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.6  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.5  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.4  2002/12/26 01:33:05  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:16  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:17:00  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
 
  /* Mode register */
  reset_mode,
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  sample_point,
  sampled_bit,
  sampled_bit_q,
  tx_point,
  hard_sync,
 
  /* Output from can_bsp module */
  rx_idle,
  last_bit_of_inter
 
 
 
 
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
 
  /* Mode register */
input         reset_mode;
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output from can_bsp module */
input         rx_idle;
input         last_bit_of_inter;
 
/* Output signals from this module */
output        sample_point;
output        sampled_bit;
output        sampled_bit_q;
output        tx_point;
output        hard_sync;
 
 
 
reg     [6:0] clk_cnt;
reg           clk_en;
reg           clk_en_q;
reg           sync_blocked;
reg           resync_blocked;
reg           sampled_bit;
reg           sampled_bit_q;
reg     [4:0] quant_cnt;
reg     [3:0] delay;
reg           sync;
reg           seg1;
reg           seg2;
reg           resync_latched;
reg           sample_point;
reg     [1:0] sample;
reg           go_sync;
 
wire          go_sync_unregistered;
wire          go_seg1;
wire          go_seg2;
wire [8:0]    preset_cnt;
wire          sync_window;
wire          resync;
wire          quant_cnt_rst;
 
 
 
assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
assign hard_sync  =   (rx_idle | last_bit_of_inter)  & (~rx) & sampled_bit & (~sync_blocked);  // Hard synchronization
assign resync     =  (~rx_idle)                      & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked);  // Re-synchronization
 
 
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_cnt <= 0;
  else if (clk_cnt >= (preset_cnt-1'b1))
    clk_cnt <=#Tp 0;
  else
    clk_cnt <=#Tp clk_cnt + 1'b1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en  <= 1'b0;
  else if (clk_cnt == (preset_cnt-1'b1))
    clk_en  <=#Tp 1'b1;
  else
    clk_en  <=#Tp 1'b0;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en_q  <= 1'b0;
  else
    clk_en_q  <=#Tp clk_en;
end
 
 
 
/* Changing states */
 assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));
 assign go_seg1 = clk_en_q & ((sync & (~seg1)) | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
 assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    go_sync <= 1'b0;
  else
    go_sync <=#Tp go_sync_unregistered;
end
 
 
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
   SJW is reached */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_latched <= 1'b0;
  else if (resync & seg2 & (~sync_window))
    resync_latched <=#Tp 1'b1;
  else if (go_seg1)
    resync_latched <= 1'b0;
end
 
 
 
/* Synchronization stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync <= 0;
  else if (go_sync)
    sync <=#Tp 1'b1;
  else if (clk_en_q)
    sync <=#Tp 1'b0;
end
 
 
assign tx_point = go_sync;
 
/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg1 <= 1;
  else if (go_seg1)
    seg1 <=#Tp 1'b1;
  else if (go_seg2)
    seg1 <=#Tp 1'b0;
end
 
 
/* Seg2 stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg2 <= 0;
  else if (go_seg2)
    seg2 <=#Tp 1'b1;
  else if (go_sync | go_seg1)
    seg2 <=#Tp 1'b0;
end
 
 
/* Quant counter */
assign quant_cnt_rst = go_sync | go_seg1 | go_seg2;
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    quant_cnt <= 0;
  else if (quant_cnt_rst)
    quant_cnt <=#Tp 0;
  else if (clk_en_q)
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
 
 
/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    delay <= 0;
  else if (clk_en_q & resync & seg1)
    delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);
  else if (go_sync | go_seg1)
    delay <=#Tp 0;
end
 
 
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
 
 
// Sampling data (memorizing two samples all the time).
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sample <= 2'b11;
  else if (clk_en_q)
    sample <= {sample[0], rx};
end
 
 
// When enabled, tripple sampling is done here.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1;
      sampled_bit_q <= 1;
      sample_point <= 0;
    end
  else if (clk_en_q & (~hard_sync))
    begin
      if (seg1 & (quant_cnt == (time_segment1 + delay)))
        begin
          sample_point <=#Tp 1;
          sampled_bit_q <=#Tp sampled_bit;
          if (triple_sampling)
            sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
          else
            sampled_bit <=#Tp rx;
        end
    end
  else
    sample_point <=#Tp 0;
end
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync_blocked <=#Tp 1'b0;
  else if (clk_en_q)
    begin
      if (hard_sync | resync)
        sync_blocked <=#Tp 1'b1;
      else if (seg2 & (quant_cnt[2:0] == time_segment2))
        sync_blocked <=#Tp 1'b0;
    end
end
 
 
/* Blocking resynchronization until reception starts (needed because after reset mode exits we are waiting for
   end-of-frame and interframe. No resynchronization is needed meanwhile). */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_blocked <=#Tp 1'b1;
  else if (reset_mode)
    resync_blocked <=#Tp 1'b1;
  else if (hard_sync)
    resync_blocked <=#Tp 1'b0;
end
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	2	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	88	mohor	`// Revision 1.19 2003/06/20 14:28:20 mohor`
54			`// When hard_sync or resync occure we need to go to seg1 segment. Going to`
55			`// sync segment is in that case blocked.`
56			`//`
57	87	mohor	`// Revision 1.18 2003/06/17 15:53:33 mohor`
58			`// clk_cnt reduced from [8:0] to [6:0].`
59			`//`
60	84	mohor	`// Revision 1.17 2003/06/17 14:32:17 mohor`
61			`// Removed few signals.`
62			`//`
63	82	mohor	`// Revision 1.16 2003/06/16 13:57:58 mohor`
64			`// tx_point generated one clk earlier. rx_i registered. Data corrected when`
65			`// using extended mode.`
66			`//`
67	78	mohor	`// Revision 1.15 2003/06/13 15:02:24 mohor`
68			`// Synchronization is also needed when transmitting a message.`
69			`//`
70	77	mohor	`// Revision 1.14 2003/06/13 14:55:11 mohor`
71			`// Counters width changed.`
72			`//`
73	76	mohor	`// Revision 1.13 2003/06/11 14:21:35 mohor`
74			`// When switching to tx, sync stage is overjumped.`
75			`//`
76	75	mohor	`// Revision 1.12 2003/02/14 20:17:01 mohor`
77			`// Several registers added. Not finished, yet.`
78			`//`
79	35	mohor	`// Revision 1.11 2003/02/09 18:40:29 mohor`
80			`// Overload fixed. Hard synchronization also enabled at the last bit of`
81			`// interframe.`
82			`//`
83	29	mohor	`// Revision 1.10 2003/02/09 02:24:33 mohor`
84			`// Bosch license warning added. Error counters finished. Overload frames`
85			`// still need to be fixed.`
86			`//`
87	28	mohor	`// Revision 1.9 2003/01/31 01:13:38 mohor`
88			`// backup.`
89			`//`
90	24	mohor	`// Revision 1.8 2003/01/10 17:51:34 mohor`
91			`// Temporary version (backup).`
92			`//`
93	15	mohor	`// Revision 1.7 2003/01/08 02:10:53 mohor`
94			`// Acceptance filter added.`
95			`//`
96	11	mohor	`// Revision 1.6 2002/12/28 04:13:23 mohor`
97			`// Backup version.`
98			`//`
99	10	mohor	`// Revision 1.5 2002/12/27 00:12:52 mohor`
100			`// Header changed, testbench improved to send a frame (crc still missing).`
101			`//`
102	9	mohor	`// Revision 1.4 2002/12/26 01:33:05 mohor`
103			`// Tripple sampling supported.`
104			`//`
105	7	mohor	`// Revision 1.3 2002/12/25 23:44:16 mohor`
106			`// Commented lines removed.`
107			`//`
108	6	mohor	`// Revision 1.2 2002/12/25 14:17:00 mohor`
109			`// Synchronization working.`
110			`//`
111	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
112			`// Initial`
113	2	mohor	`//`
114			`//`
115	5	mohor	`//`
116	2	mohor
117			`// synopsys translate_off`
118			`include "timescale.v"
119			`// synopsys translate_on`
120			`include "can_defines.v"
121
122			`module can_btl`
123			`(`
124			`clk,`
125			`rst,`
126			`rx,`
127
128			`/* Mode register */`
129	10	mohor	`reset_mode,`
130	2	mohor
131			`/* Bus Timing 0 register */`
132			`baud_r_presc,`
133			`sync_jump_width,`
134
135			`/* Bus Timing 1 register */`
136			`time_segment1,`
137			`time_segment2,`
138			`triple_sampling,`
139
140			`/* Output signals from this module */`
141	10	mohor	`sample_point,`
142			`sampled_bit,`
143			`sampled_bit_q,`
144	24	mohor	`tx_point,`
145	11	mohor	`hard_sync,`
146	2	mohor
147	10	mohor	`/* Output from can_bsp module */`
148	24	mohor	`rx_idle,`
149	29	mohor	`last_bit_of_inter`
150	2	mohor
151	10	mohor
152	11	mohor
153	2	mohor
154
155			`);`
156
157			`parameter Tp = 1;`
158
159			`input clk;`
160			`input rst;`
161			`input rx;`
162
163	10	mohor	`/* Mode register */`
164	2	mohor	`input reset_mode;`
165
166			`/* Bus Timing 0 register */`
167			`input [5:0] baud_r_presc;`
168			`input [1:0] sync_jump_width;`
169
170			`/* Bus Timing 1 register */`
171			`input [3:0] time_segment1;`
172			`input [2:0] time_segment2;`
173			`input triple_sampling;`
174
175	10	mohor	`/* Output from can_bsp module */`
176			`input rx_idle;`
177	29	mohor	`input last_bit_of_inter;`
178	10	mohor
179	2	mohor	`/* Output signals from this module */`
180	10	mohor	`output sample_point;`
181			`output sampled_bit;`
182			`output sampled_bit_q;`
183	24	mohor	`output tx_point;`
184	11	mohor	`output hard_sync;`
185	2	mohor
186
187
188	84	mohor	`reg [6:0] clk_cnt;`
189	2	mohor	`reg clk_en;`
190	78	mohor	`reg clk_en_q;`
191	5	mohor	`reg sync_blocked;`
192	24	mohor	`reg resync_blocked;`
193	2	mohor	`reg sampled_bit;`
194	10	mohor	`reg sampled_bit_q;`
195	76	mohor	`reg [4:0] quant_cnt;`
196	6	mohor	`reg [3:0] delay;`
197			`reg sync;`
198			`reg seg1;`
199			`reg seg2;`
200			`reg resync_latched;`
201	10	mohor	`reg sample_point;`
202	7	mohor	`reg [1:0] sample;`
203	76	mohor	`reg go_sync;`
204	2	mohor
205	76	mohor	`wire go_sync_unregistered;`
206	6	mohor	`wire go_seg1;`
207			`wire go_seg2;`
208			`wire [8:0] preset_cnt;`
209			`wire sync_window;`
210	75	mohor	`wire resync;`
211	82	mohor	`wire quant_cnt_rst;`
212	2	mohor
213	5	mohor
214	76	mohor
215	6	mohor	`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
216	77	mohor	`assign hard_sync = (rx_idle \| last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked); // Hard synchronization`
217			`assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked); // Re-synchronization`
218	5	mohor
219
220	6	mohor	`/* Generating general enable signal that defines baud rate. */`
221	2	mohor	`always @ (posedge clk or posedge rst)`
222			`begin`
223			`if (rst)`
224	10	mohor	`clk_cnt <= 0;`
225	78	mohor	`else if (clk_cnt >= (preset_cnt-1'b1))`
226	10	mohor	`clk_cnt <=#Tp 0;`
227			`else`
228	76	mohor	`clk_cnt <=#Tp clk_cnt + 1'b1;`
229	10	mohor	`end`
230
231
232			`always @ (posedge clk or posedge rst)`
233			`begin`
234			`if (rst)`
235			`clk_en <= 1'b0;`
236	76	mohor	`else if (clk_cnt == (preset_cnt-1'b1))`
237	10	mohor	`clk_en <=#Tp 1'b1;`
238	2	mohor	`else`
239	10	mohor	`clk_en <=#Tp 1'b0;`
240	2	mohor	`end`
241
242
243	5	mohor
244	78	mohor	`always @ (posedge clk or posedge rst)`
245			`begin`
246			`if (rst)`
247			`clk_en_q <= 1'b0;`
248			`else`
249			`clk_en_q <=#Tp clk_en;`
250			`end`
251
252
253
254	6	mohor	`/* Changing states */`
255	76	mohor	`assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));`
256	88	mohor	`assign go_seg1 = clk_en_q & ((sync & (~seg1)) \| hard_sync \| (resync & seg2 & sync_window) \| (resync_latched & sync_window));`
257	78	mohor	`assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));`
258	5	mohor
259
260	76	mohor	`always @ (posedge clk or posedge rst)`
261			`begin`
262			`if (rst)`
263			`go_sync <= 1'b0;`
264			`else`
265	88	mohor	`go_sync <=#Tp go_sync_unregistered;`
266	76	mohor	`end`
267
268
269	6	mohor	`/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when`
270			`SJW is reached */`
271	2	mohor	`always @ (posedge clk or posedge rst)`
272			`begin`
273			`if (rst)`
274	5	mohor	`resync_latched <= 1'b0;`
275	6	mohor	`else if (resync & seg2 & (~sync_window))`
276	5	mohor	`resync_latched <=#Tp 1'b1;`
277			`else if (go_seg1)`
278			`resync_latched <= 1'b0;`
279			`end`
280
281
282
283	6	mohor	`/* Synchronization stage/segment */`
284	5	mohor	`always @ (posedge clk or posedge rst)`
285			`begin`
286			`if (rst)`
287	10	mohor	`sync <= 0;`
288	5	mohor	`else if (go_sync)`
289			`sync <=#Tp 1'b1;`
290	78	mohor	`else if (clk_en_q)`
291	5	mohor	`sync <=#Tp 1'b0;`
292			`end`
293
294
295	24	mohor	`assign tx_point = go_sync;`
296
297	6	mohor	`/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */`
298	5	mohor	`always @ (posedge clk or posedge rst)`
299			`begin`
300			`if (rst)`
301	10	mohor	`seg1 <= 1;`
302	5	mohor	`else if (go_seg1)`
303			`seg1 <=#Tp 1'b1;`
304			`else if (go_seg2)`
305			`seg1 <=#Tp 1'b0;`
306			`end`
307
308
309	6	mohor	`/* Seg2 stage/segment */`
310	5	mohor	`always @ (posedge clk or posedge rst)`
311			`begin`
312			`if (rst)`
313			`seg2 <= 0;`
314			`else if (go_seg2)`
315			`seg2 <=#Tp 1'b1;`
316			`else if (go_sync \| go_seg1)`
317			`seg2 <=#Tp 1'b0;`
318			`end`
319
320
321	6	mohor	`/* Quant counter */`
322	82	mohor	`assign quant_cnt_rst = go_sync \| go_seg1 \| go_seg2;`
323	76	mohor
324	5	mohor	`always @ (posedge clk or posedge rst)`
325			`begin`
326			`if (rst)`
327			`quant_cnt <= 0;`
328	82	mohor	`else if (quant_cnt_rst)`
329	5	mohor	`quant_cnt <=#Tp 0;`
330	78	mohor	`else if (clk_en_q)`
331	5	mohor	`quant_cnt <=#Tp quant_cnt + 1'b1;`
332			`end`
333
334
335	6	mohor	`/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */`
336	5	mohor	`always @ (posedge clk or posedge rst)`
337			`begin`
338			`if (rst)`
339	6	mohor	`delay <= 0;`
340	78	mohor	`else if (clk_en_q & resync & seg1)`
341	76	mohor	`delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);`
342	5	mohor	`else if (go_sync \| go_seg1)`
343	6	mohor	`delay <=#Tp 0;`
344	5	mohor	`end`
345
346
347	6	mohor	`// If early edge appears within this window (in seg2 stage), phase error is fully compensated`
348	76	mohor	`assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));`
349	5	mohor
350
351	7	mohor	`// Sampling data (memorizing two samples all the time).`
352	5	mohor	`always @ (posedge clk or posedge rst)`
353			`begin`
354			`if (rst)`
355	7	mohor	`sample <= 2'b11;`
356	78	mohor	`else if (clk_en_q)`
357	7	mohor	`sample <= {sample[0], rx};`
358			`end`
359
360
361			`// When enabled, tripple sampling is done here.`
362			`always @ (posedge clk or posedge rst)`
363			`begin`
364			`if (rst)`
365	2	mohor	`begin`
366			`sampled_bit <= 1;`
367	10	mohor	`sampled_bit_q <= 1;`
368			`sample_point <= 0;`
369	2	mohor	`end`
370	78	mohor	`else if (clk_en_q & (~hard_sync))`
371	2	mohor	`begin`
372	7	mohor	`if (seg1 & (quant_cnt == (time_segment1 + delay)))`
373			`begin`
374	10	mohor	`sample_point <=#Tp 1;`
375			`sampled_bit_q <=#Tp sampled_bit;`
376	7	mohor	`if (triple_sampling)`
377			`sampled_bit <=#Tp (sample[0] & sample[1]) \| ( sample[0] & rx) \| (sample[1] & rx);`
378			`else`
379			`sampled_bit <=#Tp rx;`
380			`end`
381	2	mohor	`end`
382	5	mohor	`else`
383	10	mohor	`sample_point <=#Tp 0;`
384	2	mohor	`end`
385
386
387
388	5	mohor	`/* Blocking synchronization (can occur only once in a bit time) */`
389	35	mohor
390	5	mohor	`always @ (posedge clk or posedge rst)`
391			`begin`
392			`if (rst)`
393			`sync_blocked <=#Tp 1'b0;`
394	78	mohor	`else if (clk_en_q)`
395	5	mohor	`begin`
396	35	mohor	`if (hard_sync \| resync)`
397	5	mohor	`sync_blocked <=#Tp 1'b1;`
398	76	mohor	`else if (seg2 & (quant_cnt[2:0] == time_segment2))`
399	5	mohor	`sync_blocked <=#Tp 1'b0;`
400			`end`
401			`end`
402	2	mohor
403
404	24	mohor	`/* Blocking resynchronization until reception starts (needed because after reset mode exits we are waiting for`
405			`end-of-frame and interframe. No resynchronization is needed meanwhile). */`
406			`always @ (posedge clk or posedge rst)`
407			`begin`
408			`if (rst)`
409			`resync_blocked <=#Tp 1'b1;`
410			`else if (reset_mode)`
411			`resync_blocked <=#Tp 1'b1;`
412			`else if (hard_sync)`
413			`resync_blocked <=#Tp 1'b0;`
414			`end`
415	2	mohor
416
417	5	mohor
418	24	mohor
419
420	2	mohor	`endmodule`

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