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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  can_register_asyn_syn.v                                     ////

////                                                              ////

////                                                              ////

////  This file is part of the CAN Protocol Controller            ////

////  http://www.opencores.org/projects/can/                      ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////       Igor Mohor                                             ////

////       igorm@opencores.org                                    ////

////                                                              ////

////                                                              ////

////  All additional information is available in the README.txt   ////

////  file.                                                       ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2002, 2003 Authors                             ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//// The CAN protocol is developed by Robert Bosch GmbH and       ////

//// protected by patents. Anybody who wants to implement this    ////

//// CAN IP core on silicon has to obtain a CAN protocol license  ////

//// from Bosch.                                                  ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.4  2003/03/11 16:32:34  mohor

// timescale.v is used for simulation only.

//

// Revision 1.3  2003/02/09 02:24:33  mohor

// Bosch license warning added. Error counters finished. Overload frames

// still need to be fixed.

//

// Revision 1.2  2002/12/27 00:12:52  mohor

// Header changed, testbench improved to send a frame (crc still missing).

//

// Revision 1.1.1.1  2002/12/20 16:39:21  mohor

// Initial

//

//

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

module can_register_asyn_syn

( data_in,

  data_out,

  we,

  clk,

  rst,

  rst_sync

);

parameter WIDTH = 8; // default parameter of the register width

parameter RESET_VALUE = 0;

input [WIDTH-1:0] data_in;

input             we;

input             clk;

input             rst;

input             rst_sync;

output [WIDTH-1:0] data_out;

reg    [WIDTH-1:0] data_out;

always @ (posedge clk or posedge rst)

begin

  if(rst)

    data_out<=#1 RESET_VALUE;

  else if (rst_sync)                  // synchronous reset

    data_out<=#1 RESET_VALUE;

  else if (we)                        // write

    data_out<=#1 data_in;

end

endmodule