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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_fifo.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.15  2003/06/11 09:37:05  mohor
// overrun and length_info fifos are initialized at the end of reset.
//
// Revision 1.14  2003/03/05 15:02:30  mohor
// Xilinx RAM added.
//
// Revision 1.13  2003/03/01 22:53:33  mohor
// Actel APA ram supported.
//
// Revision 1.12  2003/02/19 14:44:03  mohor
// CAN core finished. Host interface added. Registers finished.
// Synchronization to the wishbone finished.
//
// Revision 1.11  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.10  2003/02/11 00:56:06  mohor
// Wishbone interface added.
//
// Revision 1.9  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.8  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.7  2003/01/17 17:44:31  mohor
// Fifo corrected to be synthesizable.
//
// Revision 1.6  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored
// to fifo, just the frame information (identifier, ...). Data length
// that is stored is the received data length and not the actual data
// length that is stored to fifo.
//
// Revision 1.5  2003/01/14 17:25:09  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.4  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.3  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.2  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.1  2003/01/08 02:10:55  mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_fifo
(
  clk,
  rst,
 
  wr,
 
  data_in,
  addr,
  data_out,
  fifo_selected,
 
  reset_mode,
  release_buffer,
  extended_mode,
  overrun,
  info_empty,
  info_cnt
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         wr;
input   [7:0] data_in;
input   [7:0] addr;
input         reset_mode;
input         release_buffer;
input         extended_mode;
input         fifo_selected;
 
output  [7:0] data_out;
output        overrun;
output        info_empty;
output  [6:0] info_cnt;
 
`ifdef ACTEL_APA_RAM
`else
`ifdef XILINX_RAM
`else
  reg     [7:0] fifo [0:63];
  reg     [3:0] length_fifo[0:63];
  reg           overrun_info[0:63];
`endif
`endif
 
reg     [5:0] rd_pointer;
reg     [5:0] wr_pointer;
reg     [5:0] read_address;
reg     [5:0] wr_info_pointer;
reg     [5:0] rd_info_pointer;
reg           wr_q;
reg     [3:0] len_cnt;
reg     [6:0] fifo_cnt;
reg     [6:0] info_cnt;
reg           latch_overrun;
reg           initialize_memories;
 
wire    [3:0] length_info;
wire          write_length_info;
wire          fifo_empty;
wire          fifo_full;
wire          info_full;
 
assign write_length_info = (~wr) & wr_q;
 
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_q <= 0;
  else if (reset_mode)
    wr_q <=#Tp 0;
  else
    wr_q <=#Tp wr;
end
 
 
// length counter
always @ (posedge clk or posedge rst)
begin
  if (rst)
    len_cnt <= 0;
  else if (reset_mode | write_length_info)
    len_cnt <=#Tp 1'b0;
  else if (wr & (~fifo_full))
    len_cnt <=#Tp len_cnt + 1'b1;
end
 
 
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_info_pointer <= 0;
  else if (write_length_info & (~info_full) | initialize_memories)
    wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
  else if (reset_mode)
    wr_info_pointer <=#Tp 0;
end
 
 
 
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_info_pointer <= 0;
  else if (reset_mode)
    rd_info_pointer <=#Tp 0;
  else if (release_buffer & (~fifo_empty))
    rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
 
 
// rd_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_pointer <= 0;
  else if (release_buffer & (~fifo_empty))
    rd_pointer <=#Tp rd_pointer + length_info;
  else if (reset_mode)
    rd_pointer <=#Tp 0;
end
 
 
// wr_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_pointer <= 0;
  else if (wr & (~fifo_full))
    wr_pointer <=#Tp wr_pointer + 1'b1;
  else if (reset_mode)
    wr_pointer <=#Tp 0;
end
 
 
// latch_overrun
always @ (posedge clk or posedge rst)
begin
  if (rst)
    latch_overrun <= 0;
  else if (reset_mode | write_length_info)
    latch_overrun <=#Tp 0;
  else if (wr & fifo_full)
    latch_overrun <=#Tp 1'b1;
end
 
 
// Counting data in fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    fifo_cnt <= 0;
  else if (wr & (~release_buffer) & (~fifo_full))
    fifo_cnt <=#Tp fifo_cnt + 1'b1;
  else if ((~wr) & release_buffer & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - length_info;
  else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - length_info + 1'b1;
  else if (reset_mode)
    fifo_cnt <=#Tp 0;
end
 
assign fifo_full = fifo_cnt == 64;
assign fifo_empty = fifo_cnt == 0;
 
 
// Counting data in length_fifo and overrun_info fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    info_cnt <= 0;
  else if (write_length_info ^ release_buffer)
    begin
      if (release_buffer & (~info_empty))
        info_cnt <=#Tp info_cnt - 1'b1;
      else if (write_length_info & (~info_full))
        info_cnt <=#Tp info_cnt + 1'b1;
    end
end
 
assign info_full = info_cnt == 64;
assign info_empty = info_cnt == 0;
 
 
// Selecting which address will be used for reading data from rx fifo
always @ (extended_mode or rd_pointer or addr)
begin
  if (extended_mode)      // extended mode
    begin
      read_address <= rd_pointer + (addr - 8'd16);
    end
  else                    // normal mode
    begin
      read_address <= rd_pointer + (addr - 8'd20);
    end
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    initialize_memories <= 1;
  else if (&wr_info_pointer)
    initialize_memories <=#Tp 1'b0;
end
 
 
`ifdef ACTEL_APA_RAM
  actel_ram_64x8_sync fifo
  (
    .DO      (data_out),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (data_in),
    .PO      (),                       // parity not used
    .WRB     (~(wr & (~fifo_full))),
    .RDB     (~fifo_selected),
    .WADDR   (wr_pointer),
    .RADDR   (read_address)
  );
 
 
  actel_ram_64x4_sync info_fifo
  (
    .DO      (length_info),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (len_cnt & {4{~initialize_memories}}),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
 
 
  actel_ram_64x1_sync overrun_fifo
  (
    .DO      (overrun),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
`else
`ifdef XILINX_RAM
 
/*
  ram_64x8_sync fifo
  (
    .addra(wr_pointer),
    .addrb(read_address),
    .clka(clk),
    .clkb(clk),
    .dina(data_in),
    .doutb(data_out),
    .wea(wr & (~fifo_full))
  );
*/
 
  RAMB4_S8_S8 fifo
  (
    .DOA(),
    .DOB(data_out),
    .ADDRA({3'h0, wr_pointer}),
    .CLKA(clk),
    .DIA(data_in),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(wr & (~fifo_full)),
    .ADDRB({3'h0, read_address}),
    .CLKB(clk),
    .DIB(8'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
 
/*
  ram_64x4_sync info_fifo
  (
    .addra(wr_info_pointer),
    .addrb(rd_info_pointer),
    .clka(clk),
    .clkb(clk),
    .dina(len_cnt),
    .doutb(length_info),
    .wea(write_length_info & (~info_full))
  );
*/
  RAMB4_S4_S4 info_fifo
  (
    .DOA(),
    .DOB(length_info),
    .ADDRA({4'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA(len_cnt & {4{~initialize_memories}}),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({4'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(4'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
/*
  ram_64x1_sync overrun_fifo
  (
    .addra(wr_info_pointer),
    .addrb(rd_info_pointer),
    .clka(clk),
    .clkb(clk),
    .dina(latch_overrun | (wr & fifo_full)),
    .doutb(overrun),
    .wea(write_length_info & (~info_full))
  );
*/
 
 
  RAMB4_S1_S1 overrun_fifo
  (
    .DOA(),
    .DOB(overrun),
    .ADDRA({6'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({6'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(1'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
`else
  // writing data to fifo
  always @ (posedge clk)
  begin
    if (wr & (~fifo_full))
      fifo[wr_pointer] <=#Tp data_in;
  end
 
  // reading from fifo
  assign data_out = fifo[read_address];
 
 
  // writing length_fifo
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
  end
 
 
  // reading length_fifo
  assign length_info = length_fifo[rd_info_pointer];
 
  // overrun_info
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
  end
 
 
  // reading overrun
  assign overrun = overrun_info[rd_info_pointer];
 
 
`endif
`endif
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	11	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_fifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002, 2003 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	11	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	85	mohor	`// Revision 1.15 2003/06/11 09:37:05 mohor`
54			`// overrun and length_info fifos are initialized at the end of reset.`
55			`//`
56	73	mohor	`// Revision 1.14 2003/03/05 15:02:30 mohor`
57			`// Xilinx RAM added.`
58			`//`
59	51	mohor	`// Revision 1.13 2003/03/01 22:53:33 mohor`
60			`// Actel APA ram supported.`
61			`//`
62	48	mohor	`// Revision 1.12 2003/02/19 14:44:03 mohor`
63			`// CAN core finished. Host interface added. Registers finished.`
64			`// Synchronization to the wishbone finished.`
65			`//`
66	39	mohor	`// Revision 1.11 2003/02/14 20:17:01 mohor`
67			`// Several registers added. Not finished, yet.`
68			`//`
69	35	mohor	`// Revision 1.10 2003/02/11 00:56:06 mohor`
70			`// Wishbone interface added.`
71			`//`
72	31	mohor	`// Revision 1.9 2003/02/09 02:24:33 mohor`
73			`// Bosch license warning added. Error counters finished. Overload frames`
74			`// still need to be fixed.`
75			`//`
76	28	mohor	`// Revision 1.8 2003/01/31 01:13:38 mohor`
77			`// backup.`
78			`//`
79	24	mohor	`// Revision 1.7 2003/01/17 17:44:31 mohor`
80			`// Fifo corrected to be synthesizable.`
81			`//`
82	23	mohor	`// Revision 1.6 2003/01/15 13:16:47 mohor`
83	31	mohor	`// When a frame with "remote request" is received, no data is stored`
84			`// to fifo, just the frame information (identifier, ...). Data length`
85			`// that is stored is the received data length and not the actual data`
86			`// length that is stored to fifo.`
87	23	mohor	`//`
88	18	mohor	`// Revision 1.5 2003/01/14 17:25:09 mohor`
89			`// Addresses corrected to decimal values (previously hex).`
90			`//`
91	17	mohor	`// Revision 1.4 2003/01/14 12:19:35 mohor`
92			`// rx_fifo is now working.`
93			`//`
94	16	mohor	`// Revision 1.3 2003/01/09 21:54:45 mohor`
95			`// rx fifo added. Not 100 % verified, yet.`
96			`//`
97	14	mohor	`// Revision 1.2 2003/01/09 14:46:58 mohor`
98			`// Temporary files (backup).`
99			`//`
100	13	mohor	`// Revision 1.1 2003/01/08 02:10:55 mohor`
101			`// Acceptance filter added.`
102	11	mohor	`//`
103			`//`
104			`//`
105	13	mohor	`//`
106	11	mohor
107			`// synopsys translate_off`
108			`include "timescale.v"
109			`// synopsys translate_on`
110			`include "can_defines.v"
111
112			`module can_fifo`
113			`(`
114			`clk,`
115			`rst,`
116
117			`wr,`
118
119			`data_in,`
120	14	mohor	`addr,`
121	11	mohor	`data_out,`
122	48	mohor	`fifo_selected,`
123	11	mohor
124			`reset_mode,`
125	14	mohor	`release_buffer,`
126	35	mohor	`extended_mode,`
127			`overrun,`
128	39	mohor	`info_empty,`
129			`info_cnt`
130	13	mohor
131	11	mohor	`);`
132
133			`parameter Tp = 1;`
134
135			`input clk;`
136			`input rst;`
137			`input wr;`
138			`input [7:0] data_in;`
139	14	mohor	`input [7:0] addr;`
140	11	mohor	`input reset_mode;`
141			`input release_buffer;`
142	14	mohor	`input extended_mode;`
143	48	mohor	`input fifo_selected;`
144	11	mohor
145	13	mohor	`output [7:0] data_out;`
146	35	mohor	`output overrun;`
147			`output info_empty;`
148	39	mohor	`output [6:0] info_cnt;`
149	11	mohor
150	48	mohor	`ifdef ACTEL_APA_RAM
151			`else
152	51	mohor	`ifdef XILINX_RAM
153			`else
154	48	mohor	`reg [7:0] fifo [0:63];`
155			`reg [3:0] length_fifo[0:63];`
156			`reg overrun_info[0:63];`
157			`endif
158	51	mohor	`endif
159	11	mohor
160			`reg [5:0] rd_pointer;`
161			`reg [5:0] wr_pointer;`
162	14	mohor	`reg [5:0] read_address;`
163	16	mohor	`reg [5:0] wr_info_pointer;`
164			`reg [5:0] rd_info_pointer;`
165	13	mohor	`reg wr_q;`
166			`reg [3:0] len_cnt;`
167	16	mohor	`reg [6:0] fifo_cnt;`
168	24	mohor	`reg [6:0] info_cnt;`
169	16	mohor	`reg latch_overrun;`
170	73	mohor	`reg initialize_memories;`
171	11	mohor
172	48	mohor	`wire [3:0] length_info;`
173	13	mohor	`wire write_length_info;`
174	16	mohor	`wire fifo_empty;`
175			`wire fifo_full;`
176	24	mohor	`wire info_full;`
177	11	mohor
178	13	mohor	`assign write_length_info = (~wr) & wr_q;`
179
180			`// Delayed write signal`
181			`always @ (posedge clk or posedge rst)`
182			`begin`
183			`if (rst)`
184			`wr_q <= 0;`
185			`else if (reset_mode)`
186			`wr_q <=#Tp 0;`
187			`else`
188			`wr_q <=#Tp wr;`
189			`end`
190
191
192			`// length counter`
193			`always @ (posedge clk or posedge rst)`
194			`begin`
195			`if (rst)`
196			`len_cnt <= 0;`
197			`else if (reset_mode \| write_length_info)`
198			`len_cnt <=#Tp 1'b0;`
199	16	mohor	`else if (wr & (~fifo_full))`
200	13	mohor	`len_cnt <=#Tp len_cnt + 1'b1;`
201			`end`
202
203
204			`// wr_info_pointer`
205			`always @ (posedge clk or posedge rst)`
206			`begin`
207			`if (rst)`
208			`wr_info_pointer <= 0;`
209	73	mohor	`else if (write_length_info & (~info_full) \| initialize_memories)`
210			`wr_info_pointer <=#Tp wr_info_pointer + 1'b1;`
211	13	mohor	`else if (reset_mode)`
212			`wr_info_pointer <=#Tp 0;`
213			`end`
214
215
216
217			`// rd_info_pointer`
218	11	mohor	`always @ (posedge clk or posedge rst)`
219			`begin`
220			`if (rst)`
221	13	mohor	`rd_info_pointer <= 0;`
222	11	mohor	`else if (reset_mode)`
223	13	mohor	`rd_info_pointer <=#Tp 0;`
224	16	mohor	`else if (release_buffer & (~fifo_empty))`
225	13	mohor	`rd_info_pointer <=#Tp rd_info_pointer + 1'b1;`
226	11	mohor	`end`
227
228
229			`// rd_pointer`
230			`always @ (posedge clk or posedge rst)`
231			`begin`
232			`if (rst)`
233			`rd_pointer <= 0;`
234	16	mohor	`else if (release_buffer & (~fifo_empty))`
235	48	mohor	`rd_pointer <=#Tp rd_pointer + length_info;`
236	11	mohor	`else if (reset_mode)`
237			`rd_pointer <=#Tp 0;`
238			`end`
239
240
241			`// wr_pointer`
242			`always @ (posedge clk or posedge rst)`
243			`begin`
244			`if (rst)`
245			`wr_pointer <= 0;`
246	16	mohor	`else if (wr & (~fifo_full))`
247	13	mohor	`wr_pointer <=#Tp wr_pointer + 1'b1;`
248	11	mohor	`else if (reset_mode)`
249			`wr_pointer <=#Tp 0;`
250			`end`
251
252
253	16	mohor	`// latch_overrun`
254			`always @ (posedge clk or posedge rst)`
255			`begin`
256			`if (rst)`
257			`latch_overrun <= 0;`
258			`else if (reset_mode \| write_length_info)`
259			`latch_overrun <=#Tp 0;`
260			`else if (wr & fifo_full)`
261			`latch_overrun <=#Tp 1'b1;`
262			`end`
263
264
265			`// Counting data in fifo`
266			`always @ (posedge clk or posedge rst)`
267			`begin`
268			`if (rst)`
269			`fifo_cnt <= 0;`
270			`else if (wr & (~release_buffer) & (~fifo_full))`
271			`fifo_cnt <=#Tp fifo_cnt + 1'b1;`
272			`else if ((~wr) & release_buffer & (~fifo_empty))`
273	48	mohor	`fifo_cnt <=#Tp fifo_cnt - length_info;`
274	16	mohor	`else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))`
275	48	mohor	`fifo_cnt <=#Tp fifo_cnt - length_info + 1'b1;`
276	16	mohor	`else if (reset_mode)`
277			`fifo_cnt <=#Tp 0;`
278			`end`
279
280			`assign fifo_full = fifo_cnt == 64;`
281			`assign fifo_empty = fifo_cnt == 0;`
282
283
284	48	mohor	`// Counting data in length_fifo and overrun_info fifo`
285	24	mohor	`always @ (posedge clk or posedge rst)`
286			`begin`
287			`if (rst)`
288			`info_cnt <= 0;`
289			`else if (write_length_info ^ release_buffer)`
290			`begin`
291			`if (release_buffer & (~info_empty))`
292			`info_cnt <=#Tp info_cnt - 1'b1;`
293			`else if (write_length_info & (~info_full))`
294			`info_cnt <=#Tp info_cnt + 1'b1;`
295			`end`
296			`end`
297
298			`assign info_full = info_cnt == 64;`
299			`assign info_empty = info_cnt == 0;`
300	16	mohor
301	24	mohor
302	14	mohor	`// Selecting which address will be used for reading data from rx fifo`
303			`always @ (extended_mode or rd_pointer or addr)`
304			`begin`
305			`if (extended_mode) // extended mode`
306			`begin`
307	17	mohor	`read_address <= rd_pointer + (addr - 8'd16);`
308	14	mohor	`end`
309			`else // normal mode`
310			`begin`
311	17	mohor	`read_address <= rd_pointer + (addr - 8'd20);`
312	14	mohor	`end`
313			`end`
314	11	mohor
315
316	73	mohor	`always @ (posedge clk or posedge rst)`
317			`begin`
318			`if (rst)`
319			`initialize_memories <= 1;`
320			`else if (&wr_info_pointer)`
321			`initialize_memories <=#Tp 1'b0;`
322			`end`
323	14	mohor
324	73	mohor
325	48	mohor	`ifdef ACTEL_APA_RAM
326			`actel_ram_64x8_sync fifo`
327			`(`
328			`.DO (data_out),`
329			`.RCLOCK (clk),`
330			`.WCLOCK (clk),`
331			`.DI (data_in),`
332			`.PO (), // parity not used`
333			`.WRB (~(wr & (~fifo_full))),`
334			`.RDB (~fifo_selected),`
335			`.WADDR (wr_pointer),`
336			`.RADDR (read_address)`
337			`);`
338	14	mohor
339
340	48	mohor	`actel_ram_64x4_sync info_fifo`
341			`(`
342			`.DO (length_info),`
343			`.RCLOCK (clk),`
344			`.WCLOCK (clk),`
345	73	mohor	`.DI (len_cnt & {4{~initialize_memories}}),`
346	48	mohor	`.PO (), // parity not used`
347	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
348	48	mohor	`.RDB (1'b0), // always enabled`
349			`.WADDR (wr_info_pointer),`
350			`.RADDR (rd_info_pointer)`
351			`);`
352	14	mohor
353
354	48	mohor	`actel_ram_64x1_sync overrun_fifo`
355			`(`
356			`.DO (overrun),`
357			`.RCLOCK (clk),`
358			`.WCLOCK (clk),`
359	73	mohor	`.DI ((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
360	48	mohor	`.PO (), // parity not used`
361	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
362	48	mohor	`.RDB (1'b0), // always enabled`
363			`.WADDR (wr_info_pointer),`
364			`.RADDR (rd_info_pointer)`
365			`);`
366			`else
367	51	mohor	`ifdef XILINX_RAM
368
369			`/*`
370			`ram_64x8_sync fifo`
371			`(`
372			`.addra(wr_pointer),`
373			`.addrb(read_address),`
374			`.clka(clk),`
375			`.clkb(clk),`
376			`.dina(data_in),`
377			`.doutb(data_out),`
378			`.wea(wr & (~fifo_full))`
379			`);`
380			`*/`
381
382			`RAMB4_S8_S8 fifo`
383			`(`
384			`.DOA(),`
385			`.DOB(data_out),`
386			`.ADDRA({3'h0, wr_pointer}),`
387			`.CLKA(clk),`
388			`.DIA(data_in),`
389			`.ENA(1'b1),`
390			`.RSTA(1'b0),`
391			`.WEA(wr & (~fifo_full)),`
392			`.ADDRB({3'h0, read_address}),`
393			`.CLKB(clk),`
394			`.DIB(8'h0),`
395			`.ENB(1'b1),`
396			`.RSTB(1'b0),`
397			`.WEB(1'b0)`
398			`);`
399
400
401
402			`/*`
403			`ram_64x4_sync info_fifo`
404			`(`
405			`.addra(wr_info_pointer),`
406			`.addrb(rd_info_pointer),`
407			`.clka(clk),`
408			`.clkb(clk),`
409			`.dina(len_cnt),`
410			`.doutb(length_info),`
411			`.wea(write_length_info & (~info_full))`
412			`);`
413			`*/`
414			`RAMB4_S4_S4 info_fifo`
415			`(`
416			`.DOA(),`
417			`.DOB(length_info),`
418			`.ADDRA({4'h0, wr_info_pointer}),`
419			`.CLKA(clk),`
420	73	mohor	`.DIA(len_cnt & {4{~initialize_memories}}),`
421	51	mohor	`.ENA(1'b1),`
422			`.RSTA(1'b0),`
423	73	mohor	`.WEA(write_length_info & (~info_full) \| initialize_memories),`
424	51	mohor	`.ADDRB({4'h0, rd_info_pointer}),`
425			`.CLKB(clk),`
426			`.DIB(4'h0),`
427			`.ENB(1'b1),`
428			`.RSTB(1'b0),`
429			`.WEB(1'b0)`
430			`);`
431
432			`/*`
433			`ram_64x1_sync overrun_fifo`
434			`(`
435			`.addra(wr_info_pointer),`
436			`.addrb(rd_info_pointer),`
437			`.clka(clk),`
438			`.clkb(clk),`
439			`.dina(latch_overrun \| (wr & fifo_full)),`
440			`.doutb(overrun),`
441			`.wea(write_length_info & (~info_full))`
442			`);`
443			`*/`
444
445
446			`RAMB4_S1_S1 overrun_fifo`
447			`(`
448			`.DOA(),`
449			`.DOB(overrun),`
450			`.ADDRA({6'h0, wr_info_pointer}),`
451			`.CLKA(clk),`
452	73	mohor	`.DIA((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
453	51	mohor	`.ENA(1'b1),`
454			`.RSTA(1'b0),`
455	73	mohor	`.WEA(write_length_info & (~info_full) \| initialize_memories),`
456	51	mohor	`.ADDRB({6'h0, rd_info_pointer}),`
457			`.CLKB(clk),`
458			`.DIB(1'h0),`
459			`.ENB(1'b1),`
460			`.RSTB(1'b0),`
461			`.WEB(1'b0)`
462			`);`
463
464
465			`else
466	48	mohor	`// writing data to fifo`
467			`always @ (posedge clk)`
468			`begin`
469			`if (wr & (~fifo_full))`
470			`fifo[wr_pointer] <=#Tp data_in;`
471			`end`
472
473			`// reading from fifo`
474			`assign data_out = fifo[read_address];`
475
476
477			`// writing length_fifo`
478			`always @ (posedge clk)`
479			`begin`
480	85	mohor	`if (write_length_info & (~info_full) \| initialize_memories)`
481	73	mohor	`length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};`
482	48	mohor	`end`
483
484	73	mohor
485	48	mohor	`// reading length_fifo`
486			`assign length_info = length_fifo[rd_info_pointer];`
487
488			`// overrun_info`
489			`always @ (posedge clk)`
490			`begin`
491	73	mohor	`if (write_length_info & (~info_full) \| initialize_memories)`
492			`overrun_info[wr_info_pointer] <=#Tp (latch_overrun \| (wr & fifo_full)) & (~initialize_memories);`
493	48	mohor	`end`
494
495
496			`// reading overrun`
497			`assign overrun = overrun_info[rd_info_pointer];`
498
499
500			`endif

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