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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_testbench.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2002/12/27 00:12:48  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.5  2002/12/26 16:00:29  mohor
// Testbench define file added. Clock divider register added.
//
// Revision 1.4  2002/12/26 01:33:01  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:12  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:16:54  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
`include "can_testbench_defines.v"
 
module can_testbench();
 
 
 
parameter Tp = 1;
parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
 
 
 
reg         clk;
reg         rst;
reg   [7:0] data_in;
wire  [7:0] data_out;
reg         cs, rw;
reg   [7:0] addr;
reg         rx;
integer     start_tb;
 
/* Instantiate can_top module */
can_top i_can_top
(
  .clk(clk),
  .rst(rst),
  .data_in(data_in),
  .data_out(data_out),
  .cs(cs),
  .rw(rw),
  .addr(addr),
  .rx(rx)
);
 
 
// Generate clock signal 24 MHz
initial
begin
  clk=0;
  forever #20 clk = ~clk;
end
 
initial
begin
  start_tb = 0;
  data_in = 'hz;
  cs = 0;
  rw = 'hz;
  addr = 'hz;
  rx = 1;
  rst = 1;
  #200 rst = 0;
  #200 start_tb = 1;
end
 
 
// Main testbench
initial
begin
  wait(start_tb);
 
  /* Set bus timing register 0 */
  write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
 
  /* Set bus timing register 1 */
  write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
 
  #10;
  repeat (1000) @ (posedge clk);
 
  /* Switch-off reset mode */
  write_register(8'h0, {7'h0, ~(`CAN_MODE_RESET)});
 
  repeat (BRP) @ (posedge clk);   // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
                                  // This difference is resynchronized later.
 
//  test_synchronization;
 
  repeat (7) send_bit(1);         // Sending EOF
 
 
  send_frame(1, 29'h00075678, 1); // mode, id, length
 
 
  repeat (50000) @ (posedge clk);
  $display("CAN Testbench finished.");
  $stop;
end
 
 
 
 
task write_register;
  input [7:0] reg_addr;
  input [7:0] reg_data;
 
  begin
    @ (posedge clk);
    #1;
    addr = reg_addr;
    data_in = reg_data;
    cs = 1;
    rw = 0;
    @ (posedge clk);
    #1;
    addr = 'hz;
    data_in = 'hz;
    cs = 0;
    rw = 'hz;
  end
endtask
 
 
task test_synchronization;
  begin
    // Hard synchronization
    #1 rx=0;
    repeat (2*BRP) @ (posedge clk);
//    #1 idle = 0;
    repeat (8*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
 
    // Resynchronization on time
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
//    idle = 0;
    repeat (10*BRP) @ (posedge clk);
 
    // Resynchronization late
    repeat (BRP) @ (posedge clk);
    repeat (BRP) @ (posedge clk);
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
//    idle = 0;
 
    // Resynchronization early
    repeat (8*BRP) @ (posedge clk);   // two frames too early
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
//    idle = 0;
    repeat (10*BRP) @ (posedge clk);
  end
endtask
 
 
task send_bit;
  input bit;
  integer cnt;
  begin
    #1 rx=bit;
    repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
//    idle=0;
  end
endtask
 
 
task send_frame;
  input mode;
  input [28:0] id;
  input  [3:0] length;
  integer cnt;
 
  reg [28:0] data;
  reg  [3:0] len;
  begin
 
    data = id;
    len  = length;
 
    send_bit(0);                        // SOF
 
    if(mode)      // Extended format
      begin
        for (cnt=0; cnt<11; cnt=cnt+1)  // 11 bit ID
          begin
            send_bit(data[28]);
            data=data<<1;
          end
        send_bit(1);                    // SRR
        send_bit(1);                    // IDE
 
        for (cnt=11; cnt<29; cnt=cnt+1)  // 18 bit ID
          begin
            send_bit(data[28]);
            data=data<<1;
          end
 
        send_bit(0);                    // RTR
        send_bit(0);                    // r1 (reserved 1)
        send_bit(0);                    // r0 (reserved 0)
 
        for (cnt=0; cnt<4; cnt=cnt+1)   // DLC (length)
          begin
            send_bit(len[3]);
            len=len<<1;
          end
      end
    else                  // Standard format
      begin
        for (cnt=0; cnt<11; cnt=cnt+1)  // 11 bit ID
          begin
            send_bit(data[10]);
            data=data<<1;
          end
        send_bit(0);                    // RTR
        send_bit(0);                    // IDE
        send_bit(0);                    // r0 (reserved 0)
 
        for (cnt=0; cnt<4; cnt=cnt+1)   // DLC (length)
          begin
            send_bit(len[3]);
            len=len<<1;
          end
      end                 // End header
 
 
      for (cnt=0; cnt<(8*length); cnt=cnt+4)  // data
        begin
          send_bit(cnt[3]);
          send_bit(cnt[2]);
          send_bit(cnt[1]);
          send_bit(cnt[0]);
        end
 
 
      // Nothing send after the data (just recessive bit)
      send_bit(1);
 
 
 
  end
endtask
 
 
/* State machine monitor (btl) */
always @ (posedge clk)
begin
  if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
     can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
    begin
      $display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);
      #1000;
      $stop;
    end
 
  if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
     can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
    begin
      $display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);
      #1000;
      $stop;
    end
end
 
/* stuff_error monitor (bsp)
always @ (posedge clk)
begin
  if(can_testbench.i_can_top.i_can_bsp.stuff_error)
    begin
      $display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);
      $stop;                                      After everything is finished add another condition (something like & (~idle)) and enable stop
    end
end
*/
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_testbench.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	10	mohor	`// Revision 1.6 2002/12/27 00:12:48 mohor`
49			`// Header changed, testbench improved to send a frame (crc still missing).`
50			`//`
51	9	mohor	`// Revision 1.5 2002/12/26 16:00:29 mohor`
52			`// Testbench define file added. Clock divider register added.`
53			`//`
54	8	mohor	`// Revision 1.4 2002/12/26 01:33:01 mohor`
55			`// Tripple sampling supported.`
56			`//`
57	7	mohor	`// Revision 1.3 2002/12/25 23:44:12 mohor`
58			`// Commented lines removed.`
59			`//`
60	6	mohor	`// Revision 1.2 2002/12/25 14:16:54 mohor`
61			`// Synchronization working.`
62			`//`
63	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
64			`// Initial`
65	2	mohor	`//`
66			`//`
67	5	mohor	`//`
68	2	mohor
69			`// synopsys translate_off`
70			`include "timescale.v"
71			`// synopsys translate_on`
72			`include "can_defines.v"
73	8	mohor	`include "can_testbench_defines.v"
74	2	mohor
75			`module can_testbench();`
76
77
78
79			`parameter Tp = 1;`
80	8	mohor	parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
81	2	mohor
82
83
84			`reg clk;`
85			`reg rst;`
86			`reg [7:0] data_in;`
87			`wire [7:0] data_out;`
88			`reg cs, rw;`
89			`reg [7:0] addr;`
90			`reg rx;`
91			`integer start_tb;`
92
93			`/* Instantiate can_top module */`
94			`can_top i_can_top`
95			`(`
96			`.clk(clk),`
97			`.rst(rst),`
98			`.data_in(data_in),`
99			`.data_out(data_out),`
100			`.cs(cs),`
101			`.rw(rw),`
102			`.addr(addr),`
103	10	mohor	`.rx(rx)`
104	2	mohor	`);`
105
106
107			`// Generate clock signal 24 MHz`
108			`initial`
109			`begin`
110			`clk=0;`
111			`forever #20 clk = ~clk;`
112			`end`
113
114			`initial`
115			`begin`
116			`start_tb = 0;`
117			`data_in = 'hz;`
118			`cs = 0;`
119			`rw = 'hz;`
120			`addr = 'hz;`
121			`rx = 1;`
122			`rst = 1;`
123			`#200 rst = 0;`
124			`#200 start_tb = 1;`
125			`end`
126
127
128			`// Main testbench`
129			`initial`
130			`begin`
131			`wait(start_tb);`
132
133			`/* Set bus timing register 0 */`
134	8	mohor	write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
135
136	2	mohor	`/* Set bus timing register 1 */`
137	8	mohor	write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
138	2	mohor
139			`#10;`
140			`repeat (1000) @ (posedge clk);`
141
142	10	mohor	`/* Switch-off reset mode */`
143			write_register(8'h0, {7'h0, ~(`CAN_MODE_RESET)});
144
145			`repeat (BRP) @ (posedge clk); // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible`
146			`// This difference is resynchronized later.`
147
148	9	mohor	`// test_synchronization;`
149	10	mohor
150			`repeat (7) send_bit(1); // Sending EOF`
151
152
153			`send_frame(1, 29'h00075678, 1); // mode, id, length`
154	9	mohor
155	5	mohor
156	2	mohor	`repeat (50000) @ (posedge clk);`
157			`$display("CAN Testbench finished.");`
158			`$stop;`
159			`end`
160
161
162
163
164			`task write_register;`
165			`input [7:0] reg_addr;`
166			`input [7:0] reg_data;`
167
168			`begin`
169			`@ (posedge clk);`
170			`#1;`
171			`addr = reg_addr;`
172			`data_in = reg_data;`
173			`cs = 1;`
174			`rw = 0;`
175			`@ (posedge clk);`
176			`#1;`
177			`addr = 'hz;`
178			`data_in = 'hz;`
179			`cs = 0;`
180			`rw = 'hz;`
181			`end`
182			`endtask`
183	7	mohor
184
185	8	mohor	`task test_synchronization;`
186			`begin`
187			`// Hard synchronization`
188			`#1 rx=0;`
189			`repeat (2*BRP) @ (posedge clk);`
190	10	mohor	`// #1 idle = 0;`
191	8	mohor	`repeat (8*BRP) @ (posedge clk);`
192			`#1 rx=1;`
193			`repeat (10*BRP) @ (posedge clk);`
194
195			`// Resynchronization on time`
196			`#1 rx=0;`
197			`repeat (10*BRP) @ (posedge clk);`
198			`#1 rx=1;`
199	10	mohor	`// idle = 0;`
200	8	mohor	`repeat (10*BRP) @ (posedge clk);`
201
202			`// Resynchronization late`
203			`repeat (BRP) @ (posedge clk);`
204			`repeat (BRP) @ (posedge clk);`
205			`#1 rx=0;`
206			`repeat (10*BRP) @ (posedge clk);`
207			`#1 rx=1;`
208	10	mohor	`// idle = 0;`
209	8	mohor
210			`// Resynchronization early`
211			`repeat (8*BRP) @ (posedge clk); // two frames too early`
212			`#1 rx=0;`
213			`repeat (10*BRP) @ (posedge clk);`
214			`#1 rx=1;`
215	10	mohor	`// idle = 0;`
216	8	mohor	`repeat (10*BRP) @ (posedge clk);`
217			`end`
218			`endtask`
219	7	mohor
220	8	mohor
221	9	mohor	`task send_bit;`
222			`input bit;`
223			`integer cnt;`
224			`begin`
225			`#1 rx=bit;`
226			repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
227	10	mohor	`// idle=0;`
228	9	mohor	`end`
229			`endtask`
230
231
232	8	mohor	`task send_frame;`
233			`input mode;`
234	9	mohor	`input [28:0] id;`
235			`input [3:0] length;`
236			`integer cnt;`
237
238			`reg [28:0] data;`
239			`reg [3:0] len;`
240	8	mohor	`begin`
241	9	mohor
242			`data = id;`
243			`len = length;`
244
245			`send_bit(0); // SOF`
246
247			`if(mode) // Extended format`
248			`begin`
249			`for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID`
250			`begin`
251			`send_bit(data[28]);`
252			`data=data<<1;`
253			`end`
254			`send_bit(1); // SRR`
255			`send_bit(1); // IDE`
256
257			`for (cnt=11; cnt<29; cnt=cnt+1) // 18 bit ID`
258			`begin`
259			`send_bit(data[28]);`
260			`data=data<<1;`
261			`end`
262
263			`send_bit(0); // RTR`
264			`send_bit(0); // r1 (reserved 1)`
265			`send_bit(0); // r0 (reserved 0)`
266
267			`for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)`
268			`begin`
269			`send_bit(len[3]);`
270			`len=len<<1;`
271			`end`
272			`end`
273			`else // Standard format`
274			`begin`
275			`for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID`
276			`begin`
277			`send_bit(data[10]);`
278			`data=data<<1;`
279			`end`
280			`send_bit(0); // RTR`
281			`send_bit(0); // IDE`
282			`send_bit(0); // r0 (reserved 0)`
283
284			`for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)`
285			`begin`
286			`send_bit(len[3]);`
287			`len=len<<1;`
288			`end`
289			`end // End header`
290
291
292			`for (cnt=0; cnt<(8*length); cnt=cnt+4) // data`
293			`begin`
294			`send_bit(cnt[3]);`
295			`send_bit(cnt[2]);`
296			`send_bit(cnt[1]);`
297			`send_bit(cnt[0]);`
298			`end`
299
300
301			`// Nothing send after the data (just recessive bit)`
302			`send_bit(1);`
303
304
305
306	8	mohor	`end`
307			`endtask`
308
309
310	7	mohor	`/* State machine monitor (btl) */`
311			`always @ (posedge clk)`
312			`begin`
313			`if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 \| can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 \|`
314			`can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)`
315	10	mohor	`begin`
316			`$display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);`
317			`#1000;`
318			`$stop;`
319			`end`
320	7	mohor
321			`if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 \| can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 \|`
322			`can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)`
323	10	mohor	`begin`
324			`$display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);`
325			`#1000;`
326			`$stop;`
327			`end`
328	7	mohor	`end`
329
330	10	mohor	`/* stuff_error monitor (bsp)`
331			`always @ (posedge clk)`
332			`begin`
333			`if(can_testbench.i_can_top.i_can_bsp.stuff_error)`
334			`begin`
335			`$display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);`
336			`$stop; After everything is finished add another condition (something like & (~idle)) and enable stop`
337			`end`
338			`end`
339			`*/`
340
341
342	2	mohor	`endmodule`

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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Blame information for rev 10