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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_testbench.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2003/01/08 02:09:43  mohor
// Acceptance filter added.
//
// Revision 1.7  2002/12/28 04:13:53  mohor
// Backup version.
//
// Revision 1.6  2002/12/27 00:12:48  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.5  2002/12/26 16:00:29  mohor
// Testbench define file added. Clock divider register added.
//
// Revision 1.4  2002/12/26 01:33:01  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:12  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:16:54  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
`include "can_testbench_defines.v"
 
module can_testbench();
 
 
 
parameter Tp = 1;
parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
 
 
 
reg         clk;
reg         rst;
reg   [7:0] data_in;
wire  [7:0] data_out;
reg         cs, rw;
reg   [7:0] addr;
reg         rx;
integer     start_tb;
reg   [7:0] tmp_data;
 
// Instantiate can_top module
can_top i_can_top
(
  .clk(clk),
  .rst(rst),
  .data_in(data_in),
  .data_out(data_out),
  .cs(cs),
  .rw(rw),
  .addr(addr),
  .rx(rx)
);
 
 
// Generate clock signal 24 MHz
initial
begin
  clk=0;
  forever #20 clk = ~clk;
end
 
initial
begin
  start_tb = 0;
  data_in = 'hz;
  cs = 0;
  rw = 'hz;
  addr = 'hz;
  rx = 1;
  rst = 1;
  #200 rst = 0;
  #200 start_tb = 1;
end
 
 
// Main testbench
initial
begin
  wait(start_tb);
 
  // Set bus timing register 0
  write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
 
  // Set bus timing register 1
  write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
 
 
 
  // Set Clock Divider register
  write_register(8'h31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0});    // Setting the normal mode (not extended)
 
  // Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
  if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
    begin
      // Set Acceptance Code and Acceptance Mask registers
      write_register(8'h16, 8'ha6); // acceptance code 0
      write_register(8'h17, 8'hb0); // acceptance code 1
      write_register(8'h18, 8'h12); // acceptance code 2
      write_register(8'h19, 8'h34); // acceptance code 3
      write_register(8'h20, 8'h0); // acceptance mask 0
      write_register(8'h21, 8'h0); // acceptance mask 1
      write_register(8'h22, 8'h0); // acceptance mask 2
      write_register(8'h23, 8'h0); // acceptance mask 3
    end
  else
    begin
      // Set Acceptance Code and Acceptance Mask registers
      write_register(8'h4, 8'ha6); // acceptance code
      write_register(8'h5, 8'h00); // acceptance mask
    end
 
  #10;
  repeat (1000) @ (posedge clk);
 
  // Switch-off reset mode
  write_register(8'h0, {7'h0, ~(`CAN_MODE_RESET)});
 
  repeat (BRP) @ (posedge clk);   // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
                                  // This difference is resynchronized later.
  repeat (7) send_bit(1);         // Sending EOF
 
//  test_synchronization;
 
 
 
  if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
    begin
      send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
//      send_frame(0, 1, 29'h12567635, 2, 15'h75b4); // mode, rtr, id, length, crc
    end
  else
    begin
      send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
    end
 
 
  repeat (50000) @ (posedge clk);
 
  read_register(8'h4);
  read_register(8'h20);
  read_register(8'h21);
  read_register(8'h22);
  read_register(8'h23);
  read_register(8'h24);
  read_register(8'h25);
 
 
  $display("CAN Testbench finished.");
  $stop;
end
 
 
 
 
task read_register;
  input [7:0] reg_addr;
 
  begin
    @ (posedge clk);
    #1;
    addr = reg_addr;
    cs = 1;
    rw = 1;
    @ (posedge clk);
    $display("(%0t) Reading register [0x%0x] = 0x%0x", $time, addr, data_out);
    #1;
    addr = 'hz;
    cs = 0;
    rw = 'hz;
  end
endtask
 
 
task write_register;
  input [7:0] reg_addr;
  input [7:0] reg_data;
 
  begin
    @ (posedge clk);
    #1;
    addr = reg_addr;
    data_in = reg_data;
    cs = 1;
    rw = 0;
    @ (posedge clk);
    #1;
    addr = 'hz;
    data_in = 'hz;
    cs = 0;
    rw = 'hz;
  end
endtask
 
 
task test_synchronization;
  begin
    // Hard synchronization
    #1 rx=0;
    repeat (2*BRP) @ (posedge clk);
    repeat (8*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
 
    // Resynchronization on time
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
 
    // Resynchronization late
    repeat (BRP) @ (posedge clk);
    repeat (BRP) @ (posedge clk);
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
 
    // Resynchronization early
    repeat (8*BRP) @ (posedge clk);   // two frames too early
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
  end
endtask
 
 
task send_bit;
  input bit;
  integer cnt;
  begin
    #1 rx=bit;
    repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
  end
endtask
 
 
task send_frame;
  input mode;
  input remote_trans_req;
  input [28:0] id;
  input  [3:0] length;
  input [14:0] crc;
  integer cnt;
 
  reg [28:0] data;
  reg  [3:0] len;
  begin
 
    data = id;
    len  = length;
 
    send_bit(0);                        // SOF
 
    if(mode)      // Extended format
      begin
        for (cnt=0; cnt<11; cnt=cnt+1)  // 11 bit ID
          begin
            send_bit(data[28]);
            data=data<<1;
          end
        send_bit(1);                    // SRR
        send_bit(1);                    // IDE
 
        for (cnt=11; cnt<29; cnt=cnt+1)  // 18 bit ID
          begin
            send_bit(data[28]);
            data=data<<1;
          end
 
        send_bit(remote_trans_req);
        send_bit(0);                    // r1 (reserved 1)
        send_bit(0);                    // r0 (reserved 0)
 
        for (cnt=0; cnt<4; cnt=cnt+1)   // DLC (length)
          begin
            send_bit(len[3]);
            len=len<<1;
          end
      end
    else                  // Standard format
      begin
        for (cnt=0; cnt<11; cnt=cnt+1)  // 11 bit ID
          begin
            send_bit(data[10]);
            data=data<<1;
          end
        send_bit(remote_trans_req);
        send_bit(0);                    // IDE
        send_bit(0);                    // r0 (reserved 0)
 
        for (cnt=0; cnt<4; cnt=cnt+1)   // DLC (length)
          begin
            send_bit(len[3]);
            len=len<<1;
          end
      end                 // End header
 
 
    if(length)    // Send data if length is > 0
      begin
        for (cnt=1; cnt<=(2*length); cnt=cnt+1)  // data   (we are sending nibbles)
          begin
            send_bit(cnt[3]);
            send_bit(cnt[2]);
            send_bit(cnt[1]);
            send_bit(cnt[0]);
          end
      end
 
    // Send CRC
    data[14:0] = crc[14:0];
    for (cnt=0; cnt<15; cnt=cnt+1)  // 15 bit CRC
      begin
        send_bit(data[14]);
        data=data<<1;
      end
 
    // Send CRC delimiter
    send_bit(1);
 
    // Send ACK slot
    send_bit(1);
 
    // Send Ack delimiter
    send_bit(1);
 
 
    // Nothing send after the data (just recessive bit)
    send_bit(1);
 
 
 
  end
endtask
 
 
// State machine monitor (btl)
always @ (posedge clk)
begin
  if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
     can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
    begin
      $display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);
      #1000;
      $stop;
    end
 
  if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
     can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
    begin
      $display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);
      #1000;
      $stop;
    end
end
 
/* stuff_error monitor (bsp)
always @ (posedge clk)
begin
  if(can_testbench.i_can_top.i_can_bsp.stuff_error)
    begin
      $display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);
      $stop;                                      After everything is finished add another condition (something like & (~idle)) and enable stop
    end
end
*/
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_testbench.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	14	mohor	`// Revision 1.8 2003/01/08 02:09:43 mohor`
49			`// Acceptance filter added.`
50			`//`
51	11	mohor	`// Revision 1.7 2002/12/28 04:13:53 mohor`
52			`// Backup version.`
53			`//`
54	10	mohor	`// Revision 1.6 2002/12/27 00:12:48 mohor`
55			`// Header changed, testbench improved to send a frame (crc still missing).`
56			`//`
57	9	mohor	`// Revision 1.5 2002/12/26 16:00:29 mohor`
58			`// Testbench define file added. Clock divider register added.`
59			`//`
60	8	mohor	`// Revision 1.4 2002/12/26 01:33:01 mohor`
61			`// Tripple sampling supported.`
62			`//`
63	7	mohor	`// Revision 1.3 2002/12/25 23:44:12 mohor`
64			`// Commented lines removed.`
65			`//`
66	6	mohor	`// Revision 1.2 2002/12/25 14:16:54 mohor`
67			`// Synchronization working.`
68			`//`
69	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
70			`// Initial`
71	2	mohor	`//`
72			`//`
73	5	mohor	`//`
74	2	mohor
75			`// synopsys translate_off`
76			`include "timescale.v"
77			`// synopsys translate_on`
78			`include "can_defines.v"
79	8	mohor	`include "can_testbench_defines.v"
80	2	mohor
81			`module can_testbench();`
82
83
84
85			`parameter Tp = 1;`
86	8	mohor	parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
87	2	mohor
88
89
90			`reg clk;`
91			`reg rst;`
92			`reg [7:0] data_in;`
93			`wire [7:0] data_out;`
94			`reg cs, rw;`
95			`reg [7:0] addr;`
96			`reg rx;`
97			`integer start_tb;`
98	14	mohor	`reg [7:0] tmp_data;`
99	2	mohor
100	11	mohor	`// Instantiate can_top module`
101	2	mohor	`can_top i_can_top`
102			`(`
103			`.clk(clk),`
104			`.rst(rst),`
105			`.data_in(data_in),`
106			`.data_out(data_out),`
107			`.cs(cs),`
108			`.rw(rw),`
109			`.addr(addr),`
110	10	mohor	`.rx(rx)`
111	2	mohor	`);`
112
113
114			`// Generate clock signal 24 MHz`
115			`initial`
116			`begin`
117			`clk=0;`
118			`forever #20 clk = ~clk;`
119			`end`
120
121			`initial`
122			`begin`
123			`start_tb = 0;`
124			`data_in = 'hz;`
125			`cs = 0;`
126			`rw = 'hz;`
127			`addr = 'hz;`
128			`rx = 1;`
129			`rst = 1;`
130			`#200 rst = 0;`
131			`#200 start_tb = 1;`
132			`end`
133
134
135			`// Main testbench`
136			`initial`
137			`begin`
138			`wait(start_tb);`
139
140	11	mohor	`// Set bus timing register 0`
141	8	mohor	write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
142
143	11	mohor	`// Set bus timing register 1`
144	8	mohor	write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
145	11	mohor
146	14	mohor
147
148	11	mohor	`// Set Clock Divider register`
149			write_register(8'h31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
150
151			`// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode`
152			if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
153			`begin`
154			`// Set Acceptance Code and Acceptance Mask registers`
155			`write_register(8'h16, 8'ha6); // acceptance code 0`
156			`write_register(8'h17, 8'hb0); // acceptance code 1`
157			`write_register(8'h18, 8'h12); // acceptance code 2`
158			`write_register(8'h19, 8'h34); // acceptance code 3`
159			`write_register(8'h20, 8'h0); // acceptance mask 0`
160			`write_register(8'h21, 8'h0); // acceptance mask 1`
161			`write_register(8'h22, 8'h0); // acceptance mask 2`
162			`write_register(8'h23, 8'h0); // acceptance mask 3`
163			`end`
164			`else`
165			`begin`
166			`// Set Acceptance Code and Acceptance Mask registers`
167			`write_register(8'h4, 8'ha6); // acceptance code`
168			`write_register(8'h5, 8'h00); // acceptance mask`
169			`end`
170	2	mohor
171			`#10;`
172			`repeat (1000) @ (posedge clk);`
173
174	11	mohor	`// Switch-off reset mode`
175	10	mohor	write_register(8'h0, {7'h0, ~(`CAN_MODE_RESET)});
176
177			`repeat (BRP) @ (posedge clk); // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible`
178			`// This difference is resynchronized later.`
179	11	mohor	`repeat (7) send_bit(1); // Sending EOF`
180	10	mohor
181	9	mohor	`// test_synchronization;`
182	10	mohor
183
184
185	11	mohor	if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
186			`begin`
187			`send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc`
188			`// send_frame(0, 1, 29'h12567635, 2, 15'h75b4); // mode, rtr, id, length, crc`
189			`end`
190			`else`
191			`begin`
192			`send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc`
193			`end`
194	9	mohor
195	5	mohor
196	2	mohor	`repeat (50000) @ (posedge clk);`
197	14	mohor
198			`read_register(8'h4);`
199			`read_register(8'h20);`
200			`read_register(8'h21);`
201			`read_register(8'h22);`
202			`read_register(8'h23);`
203			`read_register(8'h24);`
204			`read_register(8'h25);`
205
206
207	2	mohor	`$display("CAN Testbench finished.");`
208			`$stop;`
209			`end`
210
211
212
213
214	14	mohor	`task read_register;`
215			`input [7:0] reg_addr;`
216
217			`begin`
218			`@ (posedge clk);`
219			`#1;`
220			`addr = reg_addr;`
221			`cs = 1;`
222			`rw = 1;`
223			`@ (posedge clk);`
224			`$display("(%0t) Reading register [0x%0x] = 0x%0x", $time, addr, data_out);`
225			`#1;`
226			`addr = 'hz;`
227			`cs = 0;`
228			`rw = 'hz;`
229			`end`
230			`endtask`
231
232
233	2	mohor	`task write_register;`
234			`input [7:0] reg_addr;`
235			`input [7:0] reg_data;`
236
237			`begin`
238			`@ (posedge clk);`
239			`#1;`
240			`addr = reg_addr;`
241			`data_in = reg_data;`
242			`cs = 1;`
243			`rw = 0;`
244			`@ (posedge clk);`
245			`#1;`
246			`addr = 'hz;`
247			`data_in = 'hz;`
248			`cs = 0;`
249			`rw = 'hz;`
250			`end`
251			`endtask`
252	7	mohor
253
254	8	mohor	`task test_synchronization;`
255			`begin`
256			`// Hard synchronization`
257			`#1 rx=0;`
258			`repeat (2*BRP) @ (posedge clk);`
259			`repeat (8*BRP) @ (posedge clk);`
260			`#1 rx=1;`
261			`repeat (10*BRP) @ (posedge clk);`
262
263			`// Resynchronization on time`
264			`#1 rx=0;`
265			`repeat (10*BRP) @ (posedge clk);`
266			`#1 rx=1;`
267			`repeat (10*BRP) @ (posedge clk);`
268
269			`// Resynchronization late`
270			`repeat (BRP) @ (posedge clk);`
271			`repeat (BRP) @ (posedge clk);`
272			`#1 rx=0;`
273			`repeat (10*BRP) @ (posedge clk);`
274			`#1 rx=1;`
275
276			`// Resynchronization early`
277			`repeat (8*BRP) @ (posedge clk); // two frames too early`
278			`#1 rx=0;`
279			`repeat (10*BRP) @ (posedge clk);`
280			`#1 rx=1;`
281			`repeat (10*BRP) @ (posedge clk);`
282			`end`
283			`endtask`
284	7	mohor
285	8	mohor
286	9	mohor	`task send_bit;`
287			`input bit;`
288			`integer cnt;`
289			`begin`
290			`#1 rx=bit;`
291			repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
292			`end`
293			`endtask`
294
295
296	8	mohor	`task send_frame;`
297			`input mode;`
298	11	mohor	`input remote_trans_req;`
299	9	mohor	`input [28:0] id;`
300			`input [3:0] length;`
301	11	mohor	`input [14:0] crc;`
302	9	mohor	`integer cnt;`
303
304			`reg [28:0] data;`
305			`reg [3:0] len;`
306	8	mohor	`begin`
307	9	mohor
308			`data = id;`
309			`len = length;`
310
311			`send_bit(0); // SOF`
312
313			`if(mode) // Extended format`
314			`begin`
315			`for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID`
316			`begin`
317			`send_bit(data[28]);`
318			`data=data<<1;`
319			`end`
320			`send_bit(1); // SRR`
321			`send_bit(1); // IDE`
322
323			`for (cnt=11; cnt<29; cnt=cnt+1) // 18 bit ID`
324			`begin`
325			`send_bit(data[28]);`
326			`data=data<<1;`
327			`end`
328
329	11	mohor	`send_bit(remote_trans_req);`
330	9	mohor	`send_bit(0); // r1 (reserved 1)`
331			`send_bit(0); // r0 (reserved 0)`
332
333			`for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)`
334			`begin`
335			`send_bit(len[3]);`
336			`len=len<<1;`
337			`end`
338			`end`
339			`else // Standard format`
340			`begin`
341			`for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID`
342			`begin`
343			`send_bit(data[10]);`
344			`data=data<<1;`
345			`end`
346	11	mohor	`send_bit(remote_trans_req);`
347	9	mohor	`send_bit(0); // IDE`
348			`send_bit(0); // r0 (reserved 0)`
349
350			`for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)`
351			`begin`
352			`send_bit(len[3]);`
353			`len=len<<1;`
354			`end`
355			`end // End header`
356
357
358	11	mohor	`if(length) // Send data if length is > 0`
359			`begin`
360			`for (cnt=1; cnt<=(2*length); cnt=cnt+1) // data (we are sending nibbles)`
361			`begin`
362			`send_bit(cnt[3]);`
363			`send_bit(cnt[2]);`
364			`send_bit(cnt[1]);`
365			`send_bit(cnt[0]);`
366			`end`
367			`end`
368
369			`// Send CRC`
370			`data[14:0] = crc[14:0];`
371			`for (cnt=0; cnt<15; cnt=cnt+1) // 15 bit CRC`
372			`begin`
373			`send_bit(data[14]);`
374			`data=data<<1;`
375			`end`
376	9	mohor
377	11	mohor	`// Send CRC delimiter`
378			`send_bit(1);`
379
380			`// Send ACK slot`
381			`send_bit(1);`
382
383			`// Send Ack delimiter`
384			`send_bit(1);`
385
386
387			`// Nothing send after the data (just recessive bit)`
388			`send_bit(1);`
389	9	mohor
390
391
392	8	mohor	`end`
393			`endtask`
394
395
396	11	mohor	`// State machine monitor (btl)`
397	7	mohor	`always @ (posedge clk)`
398			`begin`
399			`if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 \| can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 \|`
400			`can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)`
401	10	mohor	`begin`
402			`$display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);`
403			`#1000;`
404			`$stop;`
405			`end`
406	7	mohor
407			`if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 \| can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 \|`
408			`can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)`
409	10	mohor	`begin`
410			`$display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);`
411			`#1000;`
412			`$stop;`
413			`end`
414	7	mohor	`end`
415
416	10	mohor	`/* stuff_error monitor (bsp)`
417			`always @ (posedge clk)`
418			`begin`
419			`if(can_testbench.i_can_top.i_can_bsp.stuff_error)`
420			`begin`
421			`$display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);`
422			`$stop; After everything is finished add another condition (something like & (~idle)) and enable stop`
423			`end`
424			`end`
425			`*/`
426
427
428	2	mohor	`endmodule`

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