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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_testbench.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.20  2003/02/09 02:24:11  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.19  2003/02/04 17:24:33  mohor
// Backup.
//
// Revision 1.18  2003/02/04 14:34:45  mohor
// *** empty log message ***
//
// Revision 1.17  2003/01/31 01:13:31  mohor
// backup.
//
// Revision 1.16  2003/01/16 13:36:14  mohor
// Form error supported. When receiving messages, last bit of the end-of-frame
// does not generate form error. Receiver goes to the idle mode one bit sooner.
// (CAN specification ver 2.0, part B, page 57).
//
// Revision 1.15  2003/01/15 21:05:06  mohor
// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
//
// Revision 1.14  2003/01/15 14:40:16  mohor
// RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.
//
// Revision 1.13  2003/01/15 13:16:42  mohor
// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.
//
// Revision 1.12  2003/01/14 17:25:03  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.11  2003/01/14 12:19:29  mohor
// rx_fifo is now working.
//
// Revision 1.10  2003/01/10 17:51:28  mohor
// Temporary version (backup).
//
// Revision 1.9  2003/01/09 21:54:39  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.8  2003/01/08 02:09:43  mohor
// Acceptance filter added.
//
// Revision 1.7  2002/12/28 04:13:53  mohor
// Backup version.
//
// Revision 1.6  2002/12/27 00:12:48  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.5  2002/12/26 16:00:29  mohor
// Testbench define file added. Clock divider register added.
//
// Revision 1.4  2002/12/26 01:33:01  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:12  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:16:54  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
`include "can_testbench_defines.v"
 
module can_testbench();
 
 
 
parameter Tp = 1;
parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
 
 
 
reg         clk;
reg         rst;
reg   [7:0] data_in;
wire  [7:0] data_out;
reg         cs, rw;
reg   [7:0] addr;
reg         rx;
wire        tx;
wire        tx_oen;
wire        tx_3st;
wire        rx_and_tx;
 
integer     start_tb;
reg   [7:0] tmp_data;
reg         delayed_tx;
reg         tx_bypassed;
 
 
// Instantiate can_top module
can_top i_can_top
(
  .clk(clk),
  .rst(rst),
  .data_in(data_in),
  .data_out(data_out),
  .cs(cs),
  .rw(rw),
  .addr(addr),
  .rx(rx_and_tx),
  .tx(tx),
  .tx_oen(tx_oen)
);
 
assign tx_3st = tx_oen? 1'bz : tx;
 
 
// Generate clock signal 24 MHz
initial
begin
  clk=0;
  forever #20 clk = ~clk;
end
 
initial
begin
  start_tb = 0;
  data_in = 'hz;
  cs = 0;
  rw = 'hz;
  addr = 'hz;
  rx = 1;
  rst = 1;
  #200 rst = 0;
  #200 initialize_fifo;
  #200 start_tb = 1;
  tx_bypassed = 0;
end
 
 
 
 
// Generating delayed tx signal (CAN transciever delay)
always
begin
  wait (tx_3st);
  repeat (4*BRP) @ (posedge clk);   // 4 time quants delay
  #1 delayed_tx = tx_3st;
  wait (~tx_3st);
  repeat (4*BRP) @ (posedge clk);   // 4 time quants delay
  #1 delayed_tx = tx_3st;
end
 
//assign rx_and_tx = rx & delayed_tx;   FIX ME !!!
assign rx_and_tx = rx & (delayed_tx | tx_bypassed);
 
 
// Main testbench
initial
begin
  wait(start_tb);
 
  // Set bus timing register 0
  write_register(8'd6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
 
  // Set bus timing register 1
  write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
 
 
 
  // Set Clock Divider register
  write_register(8'd31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0});    // Setting the normal mode (not extended)
 
  // Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
  if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
    begin
      // Set Acceptance Code and Acceptance Mask registers
      write_register(8'd16, 8'ha6); // acceptance code 0
      write_register(8'd17, 8'hb0); // acceptance code 1
      write_register(8'd18, 8'h12); // acceptance code 2
      write_register(8'd19, 8'h30); // acceptance code 3
      write_register(8'd20, 8'h0); // acceptance mask 0
      write_register(8'd21, 8'h0); // acceptance mask 1
      write_register(8'd22, 8'h00); // acceptance mask 2
      write_register(8'd23, 8'h00); // acceptance mask 3
    end
  else
    begin
      // Set Acceptance Code and Acceptance Mask registers
//      write_register(8'd4, 8'ha6); // acceptance code
      write_register(8'd4, 8'he8); // acceptance code
      write_register(8'd5, 8'h0f); // acceptance mask
    end
 
  #10;
  repeat (1000) @ (posedge clk);
 
  // Switch-off reset mode
  write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
 
  repeat (BRP) @ (posedge clk);   // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
                                  // This difference is resynchronized later.
 
  // After exiting the reset mode
  repeat (7) send_bit(1);         // Sending EOF
  repeat (3) send_bit(1);         // Sending Interframe
 
//  test_synchronization;
 
 
 
  if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
    begin
//      test_empty_fifo_ext;    // test currently switched off
      test_full_fifo_ext;     // test currently switched on
//      send_frame_ext;         // test currently switched off
    end
  else
    begin
//      test_empty_fifo;    // test currently switched off
//      test_full_fifo;     // test currently switched off
//      send_frame;         // test currently switched off
      manual_frame;         // test currently switched on
    end
 
 
  $display("CAN Testbench finished !");
  $stop;
end
 
 
task manual_frame;    // Testbench sends a frame
  begin
/*
    begin
 
      $display("\n\nTestbench sends a frame bit by bit");
      send_bit(0);  // SOF
      send_bit(1);  // ID
      send_bit(1);  // ID
      send_bit(1);  // ID
      send_bit(0);  // ID
      send_bit(1);  // ID
      send_bit(0);  // ID
      send_bit(0);  // ID
      send_bit(0);  // ID
      send_bit(1);  // ID
      send_bit(0);  // ID
      send_bit(1);  // ID
      send_bit(1);  // RTR
      send_bit(0);  // IDE
      send_bit(0);  // r0
      send_bit(0);  // DLC
      send_bit(1);  // DLC
      send_bit(0);  // DLC
      send_bit(0);  // DLC
      send_bit(1);  // CRC
      send_bit(0);  // CRC
      send_bit(0);  // CRC
      send_bit(0);  // CRC
      send_bit(1);  // CRC
      send_bit(0);  // CRC
      send_bit(1);  // CRC
      send_bit(1);  // CRC
      send_bit(0);  // CRC
      send_bit(1);  // CRC
      send_bit(0);  // CRC
      send_bit(1);  // CRC
      send_bit(1);  // CRC
      send_bit(0);  // CRC
      send_bit(0);  // CRC          // error
      send_bit(1);  // CRC DELIM
      send_bit(0);  // ACK
      send_bit(1);  // ACK DELIM
      send_bit(0);  // EOF        // error comes here
      send_bit(0);  // EOF        // error comes here
 
//tx_bypassed=1;
      send_bit(0);  // EOF        // error comes here
//tx_bypassed=0;
 
      send_bit(0);  // EOF        // error comes here
      send_bit(0);  // EOF        // error comes here
      send_bit(0);  // EOF        // error comes here
      send_bit(1);  // EOF        // delimiter
      send_bit(1);  // INTER      // delimiter
      send_bit(1);  // INTER      // delimiter
      send_bit(1);  // INTER      // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(0);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE       // delimiter
      send_bit(1);  // IDLE
      send_bit(1);  // IDLE
      send_bit(1);  // IDLE
 
    end
*/
// tx_bypassed=1;
 
 
    write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8
    write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7
    write_register(8'd12, 8'h00); // data byte 1
    write_register(8'd13, 8'h00); // data byte 2
    write_register(8'd14, 8'h00); // data byte 3
    write_register(8'd15, 8'h00); // data byte 4
    write_register(8'd16, 8'h00); // data byte 5
    write_register(8'd17, 8'h00); // data byte 6
    write_register(8'd18, 8'h00); // data byte 7
    write_register(8'd19, 8'h00); // data byte 8
 
    fork
      begin
        tx_request;
      end
 
      begin
        #520;
        send_bit(0);  // SOF
        send_bit(1);  // ID
        send_bit(1);  // ID
        send_bit(1);  // ID
        send_bit(0);  // ID
        send_bit(1);  // ID
        send_bit(0);  // ID
        send_bit(0);  // ID
        send_bit(0);  // ID
        send_bit(1);  // ID
        send_bit(0);  // ID
        send_bit(1);  // ID
        send_bit(1);  // RTR
        send_bit(0);  // IDE
        send_bit(0);  // r0
        send_bit(0);  // DLC
        send_bit(1);  // DLC
        send_bit(1);  // DLC
        send_bit(1);  // DLC
        send_bit(1);  // CRC
        send_bit(0);  // CRC
        send_bit(0);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(0);  // CRC
        send_bit(1);  // CRC
        send_bit(0);  // CRC
        send_bit(0);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC
        send_bit(1);  // CRC DELIM
        send_bit(0);  // ACK
        send_bit(1);  // ACK DELIM
        send_bit(1);  // EOF
        send_bit(1);  // EOF
        send_bit(1);  // EOF
        send_bit(1);  // EOF
        send_bit(1);  // EOF
        send_bit(1);  // EOF
        send_bit(1);  // EOF
//  tx_bypassed=1;
        send_bit(0);  // INTER
        send_bit(1);  // INTER    overload
        send_bit(1);  // INTER    overload
        send_bit(1);  // INTER    overload
        send_bit(1);  // INTER    overload
        send_bit(1);  // INTER    overload
        send_bit(1);  // INTER    overload
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER
        send_bit(0);  // IDLE
        send_bit(1);  // INTER    overload
        send_bit(1);  // INTER    overload
        send_bit(1);  // INTER    overload
        send_bit(1);  // INTER    overload
        send_bit(1);  // INTER    overload
        send_bit(1);  // INTER    overload
        send_bit(0);  // INTER    waiting for recessive
        send_bit(0);  // INTER    waiting for recessive
        send_bit(0);  // INTER    waiting for recessive
        send_bit(0);  // INTER    waiting for recessive
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // INTER    overload delim
        send_bit(1);  // IDLE
        send_bit(1);  // IDLE
        send_bit(1);  // IDLE
 
      end
 
 
    join
 
    read_receive_buffer;
    release_rx_buffer;
 
 
 
 
 
    read_receive_buffer;
    release_rx_buffer;
    read_receive_buffer;
 
    #200000;
 
  end
endtask
 
 
 
task send_frame;    // CAN IP core sends frames
  begin
 
    if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
      begin
 
        // Writing TX frame information + identifier + data
        write_register(8'd16, 8'h12);
        write_register(8'd17, 8'h34);
        write_register(8'd18, 8'h56);
        write_register(8'd19, 8'h78);
        write_register(8'd20, 8'h9a);
        write_register(8'd21, 8'hbc);
        write_register(8'd22, 8'hde);
        write_register(8'd23, 8'hf0);
        write_register(8'd24, 8'h0f);
        write_register(8'd25, 8'hed);
        write_register(8'd26, 8'hcb);
        write_register(8'd27, 8'ha9);
        write_register(8'd28, 8'h87);
      end
    else
      begin
        write_register(8'd10, 8'hea); // Writing ID[10:3] = 0xea
        write_register(8'd11, 8'h28); // Writing ID[2:0] = 0x1, rtr = 0, length = 8
        write_register(8'd12, 8'h56); // data byte 1
        write_register(8'd13, 8'h78); // data byte 2
        write_register(8'd14, 8'h9a); // data byte 3
        write_register(8'd15, 8'hbc); // data byte 4
        write_register(8'd16, 8'hde); // data byte 5
        write_register(8'd17, 8'hf0); // data byte 6
        write_register(8'd18, 8'h0f); // data byte 7
        write_register(8'd19, 8'hed); // data byte 8
      end
 
 
    fork
      begin
        $display("\n\nStart receiving data from CAN bus");
        receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
        receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
        receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc
 
      end
 
      begin
        tx_request;
      end
 
      begin
        // Transmitting acknowledge
        wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
        #1 rx = 0;
        wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim);
        #1 rx = 1;
      end
 
    join
 
    read_receive_buffer;
    release_rx_buffer;
    release_rx_buffer;
    read_receive_buffer;
    release_rx_buffer;
    read_receive_buffer;
    release_rx_buffer;
    read_receive_buffer;
    release_rx_buffer;
    read_receive_buffer;
 
    #200000;
 
    read_receive_buffer;
 
  end
endtask
 
 
 
task test_empty_fifo;
  begin
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h3, 15'h7bcb); // mode, rtr, id, length, crc
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h7, 15'h085c); // mode, rtr, id, length, crc
 
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
 
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
  end
endtask
 
 
 
task test_empty_fifo_ext;
  begin
    receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
    receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
 
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
 
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
  end
endtask
 
 
 
task test_full_fifo;
  begin
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h0, 15'h4edd); // mode, rtr, id, length, crc
    read_receive_buffer;
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h1, 15'h1ccf); // mode, rtr, id, length, crc
    read_receive_buffer;
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h2, 15'h73f4); // mode, rtr, id, length, crc
    fifo_info;
    read_receive_buffer;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h3, 15'h7bcb); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h4, 15'h37da); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h5, 15'h7e15); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h6, 15'h39cf); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h7, 15'h085c); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
    fifo_info;
    read_overrun_info(0, 15);
 
    release_rx_buffer;
    release_rx_buffer;
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
    receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
    fifo_info;
    read_overrun_info(0, 15);
    $display("\n\n");
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
  end
endtask
 
 
 
task test_full_fifo_ext;
  begin
    release_rx_buffer;
    $display("\n\n");
    read_receive_buffer;
    fifo_info;
 
    receive_frame(1, 0, 29'h14d60246, 4'h0, 15'h6f54); // mode, rtr, id, length, crc
    read_receive_buffer;
    fifo_info;
    receive_frame(1, 0, 29'h14d60246, 4'h1, 15'h6d38); // mode, rtr, id, length, crc
    read_receive_buffer;
    fifo_info;
    receive_frame(1, 0, 29'h14d60246, 4'h2, 15'h053e); // mode, rtr, id, length, crc
    fifo_info;
    read_receive_buffer;
    receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(1, 0, 29'h14d60246, 4'h4, 15'h4bba); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(1, 0, 29'h14d60246, 4'h5, 15'h4d7d); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(1, 0, 29'h14d60246, 4'h6, 15'h6f40); // mode, rtr, id, length, crc
    fifo_info;
    receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
    fifo_info;
    read_overrun_info(0, 10);
 
    release_rx_buffer;
    release_rx_buffer;
    fifo_info;
    receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
    fifo_info;
    read_overrun_info(0, 15);
    $display("\n\n");
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
    release_rx_buffer;
    read_receive_buffer;
    fifo_info;
 
  end
endtask
 
 
 
task initialize_fifo;
  integer i;
  begin
    for (i=0; i<32; i=i+1)
      begin
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i] = 0;
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i] = 0;
      end
 
    for (i=0; i<64; i=i+1)
      begin
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo[i] = 0;
      end
 
    $display("(%0t) Fifo initialized", $time);
  end
endtask
 
 
task read_overrun_info;
  input [4:0] start_addr;
  input [4:0] end_addr;
  integer i;
  begin
    for (i=start_addr; i<=end_addr; i=i+1)
      begin
        $display("len[0x%0x]=0x%0x", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i]);
        $display("overrun[0x%0x]=0x%0x\n", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i]);
      end
  end
endtask
 
 
task fifo_info;   // Displaying how many packets and how many bytes are in fifo. Not working when wr_info_pointer is smaller than rd_info_pointer.
  begin
      $display("(%0t) Currently %0d bytes in fifo (%0d packets)", $time, can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_cnt,
      (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_info_pointer - can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer));
end
endtask
 
 
task read_register;
  input [7:0] reg_addr;
 
  begin
    @ (posedge clk);
    #1;
    addr = reg_addr;
    cs = 1;
    rw = 1;
    @ (posedge clk);
    $display("(%0t) Reading register [%0d] = 0x%0x", $time, addr, data_out);
    #1;
    addr = 'hz;
    cs = 0;
    rw = 'hz;
  end
endtask
 
 
task write_register;
  input [7:0] reg_addr;
  input [7:0] reg_data;
 
  begin
    @ (posedge clk);
    #1;
    addr = reg_addr;
    data_in = reg_data;
    cs = 1;
    rw = 0;
    @ (posedge clk);
    #1;
    addr = 'hz;
    data_in = 'hz;
    cs = 0;
    rw = 'hz;
  end
endtask
 
 
task read_receive_buffer;
  integer i;
  begin
    if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode
      begin
        for (i=8'd16; i<=8'd28; i=i+1)
          read_register(i);
        if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])
          $display("\nWARNING: This packet was received with overrun.");
      end
    else
      begin
        for (i=8'd20; i<=8'd29; i=i+1)
          read_register(i);
        if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])
          $display("\nWARNING: This packet was received with overrun.");
      end
  end
endtask
 
 
task release_rx_buffer;
  begin
    write_register(8'd1, 8'h4);
    $display("(%0t) Rx buffer released.", $time);
    repeat (2) @ (posedge clk);   // Time to decrement all the counters
  end
endtask
 
 
task tx_request;
  begin
    write_register(8'd1, 8'h1);
    $display("(%0t) Tx requested.", $time);
    repeat (2) @ (posedge clk);   // Time to decrement all the counters, etc.
  end
endtask
 
 
task test_synchronization;
  begin
    // Hard synchronization
    #1 rx=0;
    repeat (2*BRP) @ (posedge clk);
    repeat (8*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
 
    // Resynchronization on time
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
 
    // Resynchronization late
    repeat (BRP) @ (posedge clk);
    repeat (BRP) @ (posedge clk);
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
 
    // Resynchronization early
    repeat (8*BRP) @ (posedge clk);   // two frames too early
    #1 rx=0;
    repeat (10*BRP) @ (posedge clk);
    #1 rx=1;
    repeat (10*BRP) @ (posedge clk);
  end
endtask
 
 
task send_bit;
  input bit;
  integer cnt;
  begin
    #1 rx=bit;
    repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
  end
endtask
 
 
task receive_frame;           // CAN IP core receives frames
  input mode;
  input remote_trans_req;
  input [28:0] id;
  input  [3:0] length;
  input [14:0] crc;
 
  reg [117:0] data;
  reg         previous_bit;
  reg         stuff;
  reg         tmp;
  reg         arbitration_lost;
  integer     pointer;
  integer     cnt;
  integer     total_bits;
  integer     stuff_cnt;
 
  begin
 
    stuff_cnt = 1;
    stuff = 0;
 
    if(mode)          // Extended format
      data = {id[28:18], 1'b1, 1'b1, id[17:0], remote_trans_req, 2'h0, length};
    else              // Standard format
      data = {id[10:0], remote_trans_req, 1'b0, 1'b0, length};
 
    if (~remote_trans_req)
      begin
        if(length)    // Send data if length is > 0
          begin
            for (cnt=1; cnt<=(2*length); cnt=cnt+1)  // data   (we are sending nibbles)
              data = {data[113:0], cnt[3:0]};
          end
      end
 
    // Adding CRC
    data = {data[104:0], crc[14:0]};
 
 
    // Calculating pointer that points to the bit that will be send
    if (remote_trans_req)
      begin
        if(mode)          // Extended format
          pointer = 52;
        else              // Standard format
          pointer = 32;
      end
    else
      begin
        if(mode)          // Extended format
          pointer = 52 + 8 * length;
        else              // Standard format
          pointer = 32 + 8 * length;
      end
 
    // This is how many bits we need to shift
    total_bits = pointer;
 
    // Waiting until previous msg is finished before sending another one
    wait (~can_testbench.i_can_top.i_can_bsp.error_frame & ~can_testbench.i_can_top.i_can_bsp.rx_inter & ~can_testbench.i_can_top.i_can_bsp.tx_state);
    arbitration_lost = 0;
 
    send_bit(0);                        // SOF
    previous_bit = 0;
 
    fork
 
    begin
      while (~arbitration_lost)
        begin
          for (cnt=0; cnt<=total_bits; cnt=cnt+1)
            begin
              if (stuff_cnt == 5)
                begin
                  stuff_cnt = 1;
                  total_bits = total_bits + 1;
                  stuff = 1;
                  tmp = ~data[pointer+1];
                  send_bit(~data[pointer+1]);
                  previous_bit = ~data[pointer+1];
                end
              else
                begin
                  if (data[pointer] == previous_bit)
                    stuff_cnt <= stuff_cnt + 1;
                  else
                    stuff_cnt <= 1;
 
                  stuff = 0;
                  tmp = data[pointer];
                  send_bit(data[pointer]);
                  previous_bit = data[pointer];
                  pointer = pointer - 1;
                end
              if (arbitration_lost)
                cnt=total_bits+1;         // Exit the for loop
            end
            arbitration_lost = 1; // At the end we exit the while loop
 
            // Nothing send after the data (just recessive bit)
            repeat (13) send_bit(1);         // CRC delimiter + ack + ack delimiter + EOF + intermission= 1 + 1 + 1 + 7 + 3
        end
    end
 
    begin
      while (~arbitration_lost)
        begin
          #1 wait (can_testbench.i_can_top.sample_point);
          if (mode)
            begin
              if (cnt<32 & tmp & (~rx_and_tx))
                begin
                  arbitration_lost = 1;
                  rx = 1;       // Only recessive is send from now on.
                end
            end
          else
            begin
              if (cnt<12 & tmp & (~rx_and_tx))
                begin
                  arbitration_lost = 1;
                  rx = 1;       // Only recessive is send from now on.
                end
            end
        end
    end
 
    join
 
  end
endtask
 
 
 
// State machine monitor (btl)
always @ (posedge clk)
begin
  if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
     can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
    begin
      $display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);
      #1000;
      $stop;
    end
 
  if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
     can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
    begin
      $display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);
      #1000;
      $stop;
    end
end
 
/* stuff_error monitor (bsp)
always @ (posedge clk)
begin
  if(can_testbench.i_can_top.i_can_bsp.stuff_error)
    begin
      $display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);
      $stop;                                      After everything is finished add another condition (something like & (~idle)) and enable stop
    end
end
*/
 
//
// CRC monitor (used until proper CRC generation is used in testbench
always @ (posedge clk)
begin
  if (can_testbench.i_can_top.i_can_bsp.crc_err)
    $display("Calculated crc = 0x%0x, crc_in = 0x%0x", can_testbench.i_can_top.i_can_bsp.calculated_crc, can_testbench.i_can_top.i_can_bsp.crc_in);
end
//
 
 
 
 
/*
// overrun monitor
always @ (posedge clk)
begin
  if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr & can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_full)
    $display("(%0t)overrun", $time);
end
*/
 
 
// form error monitor
always @ (posedge clk)
begin
  if (can_testbench.i_can_top.i_can_bsp.form_err)
    $display("\n\n(%0t) ERROR: form_error\n\n", $time);
end
//
 
 
endmodule
 

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_testbench.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	2	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	29	mohor	`// Revision 1.20 2003/02/09 02:24:11 mohor`
54			`// Bosch license warning added. Error counters finished. Overload frames`
55			`// still need to be fixed.`
56			`//`
57	28	mohor	`// Revision 1.19 2003/02/04 17:24:33 mohor`
58			`// Backup.`
59			`//`
60	26	mohor	`// Revision 1.18 2003/02/04 14:34:45 mohor`
61			`// * empty log message *`
62			`//`
63	25	mohor	`// Revision 1.17 2003/01/31 01:13:31 mohor`
64			`// backup.`
65			`//`
66	24	mohor	`// Revision 1.16 2003/01/16 13:36:14 mohor`
67			`// Form error supported. When receiving messages, last bit of the end-of-frame`
68			`// does not generate form error. Receiver goes to the idle mode one bit sooner.`
69			`// (CAN specification ver 2.0, part B, page 57).`
70			`//`
71	22	mohor	`// Revision 1.15 2003/01/15 21:05:06 mohor`
72			`// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).`
73			`//`
74	20	mohor	`// Revision 1.14 2003/01/15 14:40:16 mohor`
75			`// RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.`
76			`//`
77	19	mohor	`// Revision 1.13 2003/01/15 13:16:42 mohor`
78			`// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.`
79			`//`
80	18	mohor	`// Revision 1.12 2003/01/14 17:25:03 mohor`
81			`// Addresses corrected to decimal values (previously hex).`
82			`//`
83	17	mohor	`// Revision 1.11 2003/01/14 12:19:29 mohor`
84			`// rx_fifo is now working.`
85			`//`
86	16	mohor	`// Revision 1.10 2003/01/10 17:51:28 mohor`
87			`// Temporary version (backup).`
88			`//`
89	15	mohor	`// Revision 1.9 2003/01/09 21:54:39 mohor`
90			`// rx fifo added. Not 100 % verified, yet.`
91			`//`
92	14	mohor	`// Revision 1.8 2003/01/08 02:09:43 mohor`
93			`// Acceptance filter added.`
94			`//`
95	11	mohor	`// Revision 1.7 2002/12/28 04:13:53 mohor`
96			`// Backup version.`
97			`//`
98	10	mohor	`// Revision 1.6 2002/12/27 00:12:48 mohor`
99			`// Header changed, testbench improved to send a frame (crc still missing).`
100			`//`
101	9	mohor	`// Revision 1.5 2002/12/26 16:00:29 mohor`
102			`// Testbench define file added. Clock divider register added.`
103			`//`
104	8	mohor	`// Revision 1.4 2002/12/26 01:33:01 mohor`
105			`// Tripple sampling supported.`
106			`//`
107	7	mohor	`// Revision 1.3 2002/12/25 23:44:12 mohor`
108			`// Commented lines removed.`
109			`//`
110	6	mohor	`// Revision 1.2 2002/12/25 14:16:54 mohor`
111			`// Synchronization working.`
112			`//`
113	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
114			`// Initial`
115	2	mohor	`//`
116			`//`
117	5	mohor	`//`
118	2	mohor
119			`// synopsys translate_off`
120			`include "timescale.v"
121			`// synopsys translate_on`
122			`include "can_defines.v"
123	8	mohor	`include "can_testbench_defines.v"
124	2	mohor
125			`module can_testbench();`
126
127
128
129			`parameter Tp = 1;`
130	8	mohor	parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
131	2	mohor
132
133
134			`reg clk;`
135			`reg rst;`
136			`reg [7:0] data_in;`
137			`wire [7:0] data_out;`
138			`reg cs, rw;`
139			`reg [7:0] addr;`
140			`reg rx;`
141	24	mohor	`wire tx;`
142	28	mohor	`wire tx_oen;`
143			`wire tx_3st;`
144	24	mohor	`wire rx_and_tx;`
145
146	2	mohor	`integer start_tb;`
147	14	mohor	`reg [7:0] tmp_data;`
148	24	mohor	`reg delayed_tx;`
149	28	mohor	`reg tx_bypassed;`
150	2	mohor
151	24	mohor
152	11	mohor	`// Instantiate can_top module`
153	2	mohor	`can_top i_can_top`
154			`(`
155			`.clk(clk),`
156			`.rst(rst),`
157			`.data_in(data_in),`
158			`.data_out(data_out),`
159			`.cs(cs),`
160			`.rw(rw),`
161			`.addr(addr),`
162	24	mohor	`.rx(rx_and_tx),`
163	28	mohor	`.tx(tx),`
164			`.tx_oen(tx_oen)`
165	2	mohor	`);`
166
167	28	mohor	`assign tx_3st = tx_oen? 1'bz : tx;`
168	2	mohor
169	24	mohor
170	2	mohor	`// Generate clock signal 24 MHz`
171			`initial`
172			`begin`
173			`clk=0;`
174			`forever #20 clk = ~clk;`
175			`end`
176
177			`initial`
178			`begin`
179			`start_tb = 0;`
180			`data_in = 'hz;`
181			`cs = 0;`
182			`rw = 'hz;`
183			`addr = 'hz;`
184			`rx = 1;`
185			`rst = 1;`
186			`#200 rst = 0;`
187	16	mohor	`#200 initialize_fifo;`
188	2	mohor	`#200 start_tb = 1;`
189	28	mohor	`tx_bypassed = 0;`
190	2	mohor	`end`
191
192
193	28	mohor
194
195	24	mohor	`// Generating delayed tx signal (CAN transciever delay)`
196			`always`
197			`begin`
198	28	mohor	`wait (tx_3st);`
199	24	mohor	`repeat (4*BRP) @ (posedge clk); // 4 time quants delay`
200	28	mohor	`#1 delayed_tx = tx_3st;`
201			`wait (~tx_3st);`
202	24	mohor	`repeat (4*BRP) @ (posedge clk); // 4 time quants delay`
203	28	mohor	`#1 delayed_tx = tx_3st;`
204	24	mohor	`end`
205
206	28	mohor	`//assign rx_and_tx = rx & delayed_tx; FIX ME !!!`
207			`assign rx_and_tx = rx & (delayed_tx \| tx_bypassed);`
208	24	mohor
209
210	2	mohor	`// Main testbench`
211			`initial`
212			`begin`
213			`wait(start_tb);`
214
215	11	mohor	`// Set bus timing register 0`
216	17	mohor	write_register(8'd6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
217	8	mohor
218	11	mohor	`// Set bus timing register 1`
219	17	mohor	write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
220	11	mohor
221	14	mohor
222
223	11	mohor	`// Set Clock Divider register`
224	17	mohor	write_register(8'd31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
225	16	mohor
226	11	mohor	`// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode`
227			if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
228			`begin`
229			`// Set Acceptance Code and Acceptance Mask registers`
230	17	mohor	`write_register(8'd16, 8'ha6); // acceptance code 0`
231			`write_register(8'd17, 8'hb0); // acceptance code 1`
232			`write_register(8'd18, 8'h12); // acceptance code 2`
233	20	mohor	`write_register(8'd19, 8'h30); // acceptance code 3`
234	17	mohor	`write_register(8'd20, 8'h0); // acceptance mask 0`
235			`write_register(8'd21, 8'h0); // acceptance mask 1`
236	20	mohor	`write_register(8'd22, 8'h00); // acceptance mask 2`
237			`write_register(8'd23, 8'h00); // acceptance mask 3`
238	11	mohor	`end`
239			`else`
240			`begin`
241			`// Set Acceptance Code and Acceptance Mask registers`
242	17	mohor	`// write_register(8'd4, 8'ha6); // acceptance code`
243	25	mohor	`write_register(8'd4, 8'he8); // acceptance code`
244			`write_register(8'd5, 8'h0f); // acceptance mask`
245	11	mohor	`end`
246	2	mohor
247			`#10;`
248			`repeat (1000) @ (posedge clk);`
249
250	11	mohor	`// Switch-off reset mode`
251	17	mohor	write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
252	10	mohor
253			`repeat (BRP) @ (posedge clk); // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible`
254			`// This difference is resynchronized later.`
255	24	mohor
256			`// After exiting the reset mode`
257	11	mohor	`repeat (7) send_bit(1); // Sending EOF`
258	24	mohor	`repeat (3) send_bit(1); // Sending Interframe`
259	10	mohor
260	9	mohor	`// test_synchronization;`
261	10	mohor
262
263
264	11	mohor	if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
265			`begin`
266	20	mohor	`// test_empty_fifo_ext; // test currently switched off`
267			`test_full_fifo_ext; // test currently switched on`
268			`// send_frame_ext; // test currently switched off`
269	11	mohor	`end`
270			`else`
271			`begin`
272	18	mohor	`// test_empty_fifo; // test currently switched off`
273	24	mohor	`// test_full_fifo; // test currently switched off`
274	28	mohor	`// send_frame; // test currently switched off`
275			`manual_frame; // test currently switched on`
276	16	mohor	`end`
277	15	mohor
278
279	16	mohor	`$display("CAN Testbench finished !");`
280			`$stop;`
281			`end`
282	5	mohor
283	14	mohor
284	28	mohor	`task manual_frame; // Testbench sends a frame`
285			`begin`
286	29	mohor	`/*`
287			`begin`
288	14	mohor
289	28	mohor	`$display("\n\nTestbench sends a frame bit by bit");`
290			`send_bit(0); // SOF`
291			`send_bit(1); // ID`
292			`send_bit(1); // ID`
293			`send_bit(1); // ID`
294			`send_bit(0); // ID`
295			`send_bit(1); // ID`
296			`send_bit(0); // ID`
297			`send_bit(0); // ID`
298			`send_bit(0); // ID`
299			`send_bit(1); // ID`
300			`send_bit(0); // ID`
301			`send_bit(1); // ID`
302			`send_bit(1); // RTR`
303			`send_bit(0); // IDE`
304			`send_bit(0); // r0`
305			`send_bit(0); // DLC`
306			`send_bit(1); // DLC`
307			`send_bit(0); // DLC`
308			`send_bit(0); // DLC`
309			`send_bit(1); // CRC`
310			`send_bit(0); // CRC`
311			`send_bit(0); // CRC`
312			`send_bit(0); // CRC`
313			`send_bit(1); // CRC`
314			`send_bit(0); // CRC`
315			`send_bit(1); // CRC`
316			`send_bit(1); // CRC`
317			`send_bit(0); // CRC`
318			`send_bit(1); // CRC`
319			`send_bit(0); // CRC`
320			`send_bit(1); // CRC`
321			`send_bit(1); // CRC`
322			`send_bit(0); // CRC`
323			`send_bit(0); // CRC // error`
324			`send_bit(1); // CRC DELIM`
325			`send_bit(0); // ACK`
326			`send_bit(1); // ACK DELIM`
327			`send_bit(0); // EOF // error comes here`
328			`send_bit(0); // EOF // error comes here`
329
330			`//tx_bypassed=1;`
331			`send_bit(0); // EOF // error comes here`
332			`//tx_bypassed=0;`
333
334			`send_bit(0); // EOF // error comes here`
335			`send_bit(0); // EOF // error comes here`
336			`send_bit(0); // EOF // error comes here`
337			`send_bit(1); // EOF // delimiter`
338			`send_bit(1); // INTER // delimiter`
339			`send_bit(1); // INTER // delimiter`
340			`send_bit(1); // INTER // delimiter`
341			`send_bit(1); // IDLE // delimiter`
342			`send_bit(1); // IDLE // delimiter`
343			`send_bit(1); // IDLE // delimiter`
344			`send_bit(0); // IDLE // delimiter`
345			`send_bit(1); // IDLE // delimiter`
346			`send_bit(1); // IDLE // delimiter`
347			`send_bit(1); // IDLE // delimiter`
348			`send_bit(1); // IDLE // delimiter`
349			`send_bit(1); // IDLE // delimiter`
350			`send_bit(1); // IDLE // delimiter`
351			`send_bit(1); // IDLE`
352			`send_bit(1); // IDLE`
353			`send_bit(1); // IDLE`
354
355			`end`
356	29	mohor	`*/`
357	28	mohor	`// tx_bypassed=1;`
358
359
360	29	mohor	`write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8`
361			`write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7`
362			`write_register(8'd12, 8'h00); // data byte 1`
363			`write_register(8'd13, 8'h00); // data byte 2`
364			`write_register(8'd14, 8'h00); // data byte 3`
365			`write_register(8'd15, 8'h00); // data byte 4`
366			`write_register(8'd16, 8'h00); // data byte 5`
367			`write_register(8'd17, 8'h00); // data byte 6`
368			`write_register(8'd18, 8'h00); // data byte 7`
369			`write_register(8'd19, 8'h00); // data byte 8`
370
371	28	mohor	`fork`
372			`begin`
373			`tx_request;`
374			`end`
375
376			`begin`
377			`#520;`
378			`send_bit(0); // SOF`
379			`send_bit(1); // ID`
380			`send_bit(1); // ID`
381			`send_bit(1); // ID`
382			`send_bit(0); // ID`
383			`send_bit(1); // ID`
384			`send_bit(0); // ID`
385			`send_bit(0); // ID`
386			`send_bit(0); // ID`
387			`send_bit(1); // ID`
388			`send_bit(0); // ID`
389			`send_bit(1); // ID`
390			`send_bit(1); // RTR`
391			`send_bit(0); // IDE`
392			`send_bit(0); // r0`
393			`send_bit(0); // DLC`
394			`send_bit(1); // DLC`
395			`send_bit(1); // DLC`
396			`send_bit(1); // DLC`
397			`send_bit(1); // CRC`
398			`send_bit(0); // CRC`
399			`send_bit(0); // CRC`
400			`send_bit(1); // CRC`
401			`send_bit(1); // CRC`
402			`send_bit(1); // CRC`
403			`send_bit(0); // CRC`
404			`send_bit(1); // CRC`
405			`send_bit(0); // CRC`
406			`send_bit(0); // CRC`
407			`send_bit(1); // CRC`
408			`send_bit(1); // CRC`
409			`send_bit(1); // CRC`
410			`send_bit(1); // CRC`
411			`send_bit(1); // CRC`
412			`send_bit(1); // CRC DELIM`
413			`send_bit(0); // ACK`
414			`send_bit(1); // ACK DELIM`
415			`send_bit(1); // EOF`
416			`send_bit(1); // EOF`
417			`send_bit(1); // EOF`
418			`send_bit(1); // EOF`
419			`send_bit(1); // EOF`
420			`send_bit(1); // EOF`
421			`send_bit(1); // EOF`
422			`// tx_bypassed=1;`
423	29	mohor	`send_bit(0); // INTER`
424			`send_bit(1); // INTER overload`
425			`send_bit(1); // INTER overload`
426			`send_bit(1); // INTER overload`
427			`send_bit(1); // INTER overload`
428			`send_bit(1); // INTER overload`
429			`send_bit(1); // INTER overload`
430			`send_bit(1); // INTER overload delim`
431			`send_bit(1); // INTER overload delim`
432			`send_bit(1); // INTER overload delim`
433			`send_bit(1); // INTER overload delim`
434			`send_bit(1); // INTER overload delim`
435			`send_bit(1); // INTER overload delim`
436			`send_bit(1); // INTER overload delim`
437			`send_bit(1); // INTER overload delim`
438	28	mohor	`send_bit(1); // INTER`
439	29	mohor	`send_bit(0); // IDLE`
440			`send_bit(1); // INTER overload`
441			`send_bit(1); // INTER overload`
442			`send_bit(1); // INTER overload`
443			`send_bit(1); // INTER overload`
444			`send_bit(1); // INTER overload`
445			`send_bit(1); // INTER overload`
446			`send_bit(0); // INTER waiting for recessive`
447			`send_bit(0); // INTER waiting for recessive`
448			`send_bit(0); // INTER waiting for recessive`
449			`send_bit(0); // INTER waiting for recessive`
450			`send_bit(1); // INTER overload delim`
451			`send_bit(1); // INTER overload delim`
452			`send_bit(1); // INTER overload delim`
453			`send_bit(1); // INTER overload delim`
454			`send_bit(1); // INTER overload delim`
455			`send_bit(1); // INTER overload delim`
456			`send_bit(1); // INTER overload delim`
457			`send_bit(1); // INTER overload delim`
458	28	mohor	`send_bit(1); // IDLE`
459			`send_bit(1); // IDLE`
460			`send_bit(1); // IDLE`
461
462			`end`
463
464
465			`join`
466
467			`read_receive_buffer;`
468			`release_rx_buffer;`
469
470
471
472
473
474			`read_receive_buffer;`
475			`release_rx_buffer;`
476			`read_receive_buffer;`
477
478			`#200000;`
479
480			`end`
481			`endtask`
482
483
484
485	18	mohor	`task send_frame; // CAN IP core sends frames`
486			`begin`
487	14	mohor
488	18	mohor	if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
489			`begin`
490
491			`// Writing TX frame information + identifier + data`
492			`write_register(8'd16, 8'h12);`
493			`write_register(8'd17, 8'h34);`
494			`write_register(8'd18, 8'h56);`
495			`write_register(8'd19, 8'h78);`
496			`write_register(8'd20, 8'h9a);`
497			`write_register(8'd21, 8'hbc);`
498			`write_register(8'd22, 8'hde);`
499			`write_register(8'd23, 8'hf0);`
500			`write_register(8'd24, 8'h0f);`

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