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1 83 mohor 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  can_testbench.v                                             ////
4 
////                                                              ////
5 
////                                                              ////
6 
////  This file is part of the CAN Protocol Controller            ////
7 
////  http://www.opencores.org/projects/can/                      ////
8 
////                                                              ////
9 
////                                                              ////
10 
////  Author(s):                                                  ////
11 
////       Igor Mohor                                             ////
12 
////       igorm@opencores.org                                    ////
13 
////                                                              ////
14 
////                                                              ////
15 
////  All additional information is available in the README.txt   ////
16 
////  file.                                                       ////
17 
////                                                              ////
18 
//////////////////////////////////////////////////////////////////////
19 
////                                                              ////
20 
//// Copyright (C) 2002, 2003 Authors                             ////
21 
////                                                              ////
22 
//// This source file may be used and distributed without         ////
23 
//// restriction provided that this copyright statement is not    ////
24 
//// removed from the file and that any derivative work contains  ////
25 
//// the original copyright notice and the associated disclaimer. ////
26 
////                                                              ////
27 
//// This source file is free software; you can redistribute it   ////
28 
//// and/or modify it under the terms of the GNU Lesser General   ////
29 
//// Public License as published by the Free Software Foundation; ////
30 
//// either version 2.1 of the License, or (at your option) any   ////
31 
//// later version.                                               ////
32 
////                                                              ////
33 
//// This source is distributed in the hope that it will be       ////
34 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37 
//// details.                                                     ////
38 
////                                                              ////
39 
//// You should have received a copy of the GNU Lesser General    ////
40 
//// Public License along with this source; if not, download it   ////
41 
//// from http://www.opencores.org/lgpl.shtml                     ////
42 
////                                                              ////
43 
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
44 
//// protected by patents. Anybody who wants to implement this    ////
45 
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
46 
//// from Bosch.                                                  ////
47 
////                                                              ////
48 
//////////////////////////////////////////////////////////////////////
49 
//
50 
// CVS Revision History
51 
//
52 
// $Log: not supported by cvs2svn $
53 
// Revision 1.34  2003/03/26 11:25:39  mohor
54 
// CAN inturrupt is active low.
55 
//
56 
// Revision 1.33  2003/03/14 19:37:30  mohor
57 
// ALE changes on negedge of clk.
58 
//
59 
// Revision 1.32  2003/03/12 05:57:36  mohor
60 
// Bidirectional port_0_i changed to port_0_io.
61 
// input cs_can changed to cs_can_i.
62 
//
63 
// Revision 1.31  2003/03/12 04:40:00  mohor
64 
// rd_i and wr_i are active high signals. If 8051 is connected, these two signals
65 
// need to be negated one level higher.
66 
//
67 
// Revision 1.30  2003/03/12 04:16:40  mohor
68 
// 8051 interface added (besides WISHBONE interface). Selection is made in
69 
// can_defines.v file.
70 
//
71 
// Revision 1.29  2003/03/05 15:33:37  mohor
72 
// tx_o is now tristated signal. tx_oen and tx_o combined together.
73 
//
74 
// Revision 1.28  2003/03/05 15:00:49  mohor
75 
// Top level signal names changed.
76 
//
77 
// Revision 1.27  2003/03/01 22:48:26  mohor
78 
// Actel APA ram supported.
79 
//
80 
// Revision 1.26  2003/02/19 14:43:17  mohor
81 
// CAN core finished. Host interface added. Registers finished.
82 
// Synchronization to the wishbone finished.
83 
//
84 
// Revision 1.25  2003/02/18 00:19:39  mohor
85 
// Temporary backup version (still fully operable).
86 
//
87 
// Revision 1.24  2003/02/14 20:16:53  mohor
88 
// Several registers added. Not finished, yet.
89 
//
90 
// Revision 1.23  2003/02/12 14:28:30  mohor
91 
// Errors monitoring improved. arbitration_lost improved.
92 
//
93 
// Revision 1.22  2003/02/11 00:57:19  mohor
94 
// Wishbone interface added.
95 
//
96 
// Revision 1.21  2003/02/09 18:40:23  mohor
97 
// Overload fixed. Hard synchronization also enabled at the last bit of
98 
// interframe.
99 
//
100 
// Revision 1.20  2003/02/09 02:24:11  mohor
101 
// Bosch license warning added. Error counters finished. Overload frames
102 
// still need to be fixed.
103 
//
104 
// Revision 1.19  2003/02/04 17:24:33  mohor
105 
// Backup.
106 
//
107 
// Revision 1.18  2003/02/04 14:34:45  mohor
108 
// *** empty log message ***
109 
//
110 
// Revision 1.17  2003/01/31 01:13:31  mohor
111 
// backup.
112 
//
113 
// Revision 1.16  2003/01/16 13:36:14  mohor
114 
// Form error supported. When receiving messages, last bit of the end-of-frame
115 
// does not generate form error. Receiver goes to the idle mode one bit sooner.
116 
// (CAN specification ver 2.0, part B, page 57).
117 
//
118 
// Revision 1.15  2003/01/15 21:05:06  mohor
119 
// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
120 
//
121 
// Revision 1.14  2003/01/15 14:40:16  mohor
122 
// RX state machine fixed to receive "remote request" frames correctly. No
123 
// data bytes are written to fifo when such frames are received.
124 
//
125 
// Revision 1.13  2003/01/15 13:16:42  mohor
126 
// When a frame with "remote request" is received, no data is stored to
127 
// fifo, just the frame information (identifier, ...). Data length that
128 
// is stored is the received data length and not the actual data length
129 
// that is stored to fifo.
130 
//
131 
// Revision 1.12  2003/01/14 17:25:03  mohor
132 
// Addresses corrected to decimal values (previously hex).
133 
//
134 
// Revision 1.11  2003/01/14 12:19:29  mohor
135 
// rx_fifo is now working.
136 
//
137 
// Revision 1.10  2003/01/10 17:51:28  mohor
138 
// Temporary version (backup).
139 
//
140 
// Revision 1.9  2003/01/09 21:54:39  mohor
141 
// rx fifo added. Not 100 % verified, yet.
142 
//
143 
// Revision 1.8  2003/01/08 02:09:43  mohor
144 
// Acceptance filter added.
145 
//
146 
// Revision 1.7  2002/12/28 04:13:53  mohor
147 
// Backup version.
148 
//
149 
// Revision 1.6  2002/12/27 00:12:48  mohor
150 
// Header changed, testbench improved to send a frame (crc still missing).
151 
//
152 
// Revision 1.5  2002/12/26 16:00:29  mohor
153 
// Testbench define file added. Clock divider register added.
154 
//
155 
// Revision 1.4  2002/12/26 01:33:01  mohor
156 
// Tripple sampling supported.
157 
//
158 
// Revision 1.3  2002/12/25 23:44:12  mohor
159 
// Commented lines removed.
160 
//
161 
// Revision 1.2  2002/12/25 14:16:54  mohor
162 
// Synchronization working.
163 
//
164 
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
165 
// Initial
166 
//
167 
//
168 
//
169 
 
170 
// synopsys translate_off
171 
`include "timescale.v"
172 
// synopsys translate_on
173 
`include "can_defines.v"
174 
`include "can_testbench_defines.v"
175 
 
176 
module can_testbench();
177 
 
178 
 
179 
 
180 
parameter Tp = 1;
181 
parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
182 
 
183 
 
184 
`ifdef CAN_WISHBONE_IF
185 
  reg         wb_clk_i;
186 
  reg         wb_rst_i;
187 
  reg   [7:0] wb_dat_i;
188 
  wire  [7:0] wb_dat_o;
189 
  reg         wb_cyc_i;
190 
  reg         wb_stb_i;
191 
  reg         wb_we_i;
192 
  reg   [7:0] wb_adr_i;
193 
  wire        wb_ack_o;
194 
  reg         wb_free;
195 
`else
196 
  reg         rst_i;
197 
  reg         ale_i;
198 
  reg         rd_i;
199 
  reg         wr_i;
200 
  wire  [7:0] port_0;
201 
  wire  [7:0] port_0_i;
202 
  reg   [7:0] port_0_o;
203 
  reg         port_0_en;
204 
  reg         port_free;
205 
`endif
206 
 
207 
 
208 
reg         cs_can;
209 
reg         clk;
210 
reg         rx;
211 
wire        tx;
212 
wire        irq;
213 
wire        clkout;
214 
 
215 
wire        rx_and_tx;
216 
 
217 
integer     start_tb;
218 
reg   [7:0] tmp_data;
219 
reg         delayed_tx;
220 
reg         tx_bypassed;
221 
reg         extended_mode;
222 
 
223 
 
224 
 
225 
// Instantiate can_top module
226 
can_top i_can_top
227 
(
228 
`ifdef CAN_WISHBONE_IF
229 
  .wb_clk_i(wb_clk_i),
230 
  .wb_rst_i(wb_rst_i),
231 
  .wb_dat_i(wb_dat_i),
232 
  .wb_dat_o(wb_dat_o),
233 
  .wb_cyc_i(wb_cyc_i),
234 
  .wb_stb_i(wb_stb_i),
235 
  .wb_we_i(wb_we_i),
236 
  .wb_adr_i(wb_adr_i),
237 
  .wb_ack_o(wb_ack_o),
238 
`else
239 
  .cs_can_i(cs_can),
240 
  .rst_i(rst_i),
241 
  .ale_i(ale_i),
242 
  .rd_i(rd_i),
243 
  .wr_i(wr_i),
244 
  .port_0_io(port_0),
245 
`endif
246 
  .clk_i(clk),
247 
  .rx_i(rx_and_tx),
248 
  .tx_o(tx),
249 
  .irq_on(irq),
250 
  .clkout_o(clkout)
251 
);
252 
 
253 
 
254 
`ifdef CAN_WISHBONE_IF
255 
  // Generate wishbone clock signal 10 MHz
256 
  initial
257 
  begin
258 
    wb_clk_i=0;
259 
    forever #50 wb_clk_i = ~wb_clk_i;
260 
  end
261 
`endif
262 
 
263 
 
264 
`ifdef CAN_WISHBONE_IF
265 
`else
266 
  assign port_0_i = port_0;
267 
  assign port_0 = port_0_en? port_0_o : 8'hz;
268 
`endif
269 
 
270 
 
271 
// Generate clock signal 24 MHz
272 
initial
273 
begin
274 
  clk=0;
275 
  forever #21 clk = ~clk;
276 
end
277 
 
278 
 
279 
initial
280 
begin
281 
  start_tb = 0;
282 
  cs_can = 0;
283 
  rx = 1;
284 
  extended_mode = 0;
285 
  tx_bypassed = 0;
286 
 
287 
  `ifdef CAN_WISHBONE_IF
288 
    wb_dat_i = 'hz;
289 
    wb_cyc_i = 0;
290 
    wb_stb_i = 0;
291 
    wb_we_i = 'hz;
292 
    wb_adr_i = 'hz;
293 
    wb_free = 1;
294 
    wb_rst_i = 1;
295 
    #200 wb_rst_i = 0;
296 
    #200 start_tb = 1;
297 
  `else
298 
    rst_i = 1'b0;
299 
    ale_i = 1'b0;
300 
    rd_i  = 1'b0;
301 
    wr_i  = 1'b0;
302 
    port_0_o = 8'h0;
303 
    port_0_en = 0;
304 
    port_free = 1;
305 
    rst_i = 1;
306 
    #200 rst_i = 0;
307 
    #200 start_tb = 1;
308 
  `endif
309 
end
310 
 
311 
 
312 
 
313 
 
314 
// Generating delayed tx signal (CAN transciever delay)
315 
always
316 
begin
317 
  wait (tx);
318 
  repeat (4*BRP) @ (posedge clk);   // 4 time quants delay
319 
  #1 delayed_tx = tx;
320 
  wait (~tx);
321 
  repeat (4*BRP) @ (posedge clk);   // 4 time quants delay
322 
  #1 delayed_tx = tx;
323 
end
324 
 
325 
//assign rx_and_tx = rx & delayed_tx;   FIX ME !!!
326 
assign rx_and_tx = rx & (delayed_tx | tx_bypassed);   // When this signal is on, tx is not looped back to the rx.
327 
 
328 
 
329 
// Main testbench
330 
initial
331 
begin
332 
  wait(start_tb);
333 
 
334 
  // Set bus timing register 0
335 
  write_register(8'd6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
336 
 
337 
  // Set bus timing register 1
338 
  write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
339 
 
340 
 
341 
  // Set Clock Divider register
342 
  extended_mode = 1'b0;
343 
  write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0});   // Setting the normal mode (not extended)
344 
 
345 
 
346 
  // Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
347 
/*
348 
  // Set Acceptance Code and Acceptance Mask registers
349 
  write_register(8'd16, 8'ha6); // acceptance code 0
350 
  write_register(8'd17, 8'hb0); // acceptance code 1
351 
  write_register(8'd18, 8'h12); // acceptance code 2
352 
  write_register(8'd19, 8'h30); // acceptance code 3
353 
  write_register(8'd20, 8'h0); // acceptance mask 0
354 
  write_register(8'd21, 8'h0); // acceptance mask 1
355 
  write_register(8'd22, 8'h00); // acceptance mask 2
356 
  write_register(8'd23, 8'h00); // acceptance mask 3
357 
*/
358 
 
359 
  // Set Acceptance Code and Acceptance Mask registers
360 
  write_register(8'd4, 8'he8); // acceptance code
361 
  write_register(8'd5, 8'h0f); // acceptance mask
362 
 
363 
  #10;
364 
  repeat (1000) @ (posedge clk);
365 
 
366 
  // Switch-off reset mode
367 
  write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
368 
 
369 
  repeat (BRP) @ (posedge clk);   // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
370 
                                  // This difference is resynchronized later.
371 
 
372 
  // After exiting the reset mode sending bus free
373 
  repeat (11) send_bit(1);
374 
 
375 
//  test_synchronization;       // test currently switched off
376 
//  test_empty_fifo_ext;        // test currently switched off
377 
//  test_full_fifo_ext;         // test currently switched off
378 
//  send_frame_ext;             // test currently switched off
379 
//  test_empty_fifo;            // test currently switched off
380 
  test_full_fifo;             // test currently switched on
381 
//  send_frame;                 // test currently switched off
382 
//  bus_off_test;               // test currently switched off
383 
//  forced_bus_off;             // test currently switched off
384 
//  send_frame_basic;           // test currently switched off
385 
//  send_frame_extended;        // test currently switched off
386 
//  self_reception_request;       // test currently switched off
387 
//  manual_frame_basic;         // test currently switched off
388 
//  manual_frame_ext;           // test currently switched off
389 
 
390 
  $display("CAN Testbench finished !");
391 
  $stop;
392 
end
393 
 
394 
 
395 
task forced_bus_off;    // Forcing bus-off by writinf to tx_err_cnt register
396 
  begin
397 
 
398 
    // Switch-on reset mode
399 
    write_register(8'd0, {7'h0, `CAN_MODE_RESET});
400 
 
401 
    // Set Clock Divider register
402 
    write_register(8'd31, {1'b1, 7'h0});    // Setting the extended mode (not normal)
403 
 
404 
    // Write 255 to tx_err_cnt register - Forcing bus-off
405 
    write_register(8'd15, 255);
406 
 
407 
    // Switch-off reset mode
408 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
409 
 
410 
//    #1000000;
411 
    #2500000;
412 
 
413 
 
414 
    // Switch-on reset mode
415 
    write_register(8'd0, {7'h0, `CAN_MODE_RESET});
416 
 
417 
    // Write 245 to tx_err_cnt register
418 
    write_register(8'd15, 245);
419 
 
420 
    // Switch-off reset mode
421 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
422 
 
423 
    #1000000;
424 
 
425 
 
426 
  end
427 
endtask   // forced_bus_off
428 
 
429 
 
430 
task manual_frame_basic;    // Testbench sends a basic format frame
431 
  begin
432 
 
433 
 
434 
    // Switch-on reset mode
435 
    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
436 
 
437 
    // Set Acceptance Code and Acceptance Mask registers
438 
    write_register(8'd4, 8'h28); // acceptance code
439 
    write_register(8'd5, 8'hff); // acceptance mask
440 
 
441 
    repeat (100) @ (posedge clk);
442 
 
443 
    // Switch-off reset mode
444 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
445 
 
446 
    // After exiting the reset mode sending bus free
447 
    repeat (11) send_bit(1);
448 
 
449 
 
450 
    write_register(8'd10, 8'h55); // Writing ID[10:3] = 0x55
451 
    write_register(8'd11, 8'h57); // Writing ID[2:0] = 0x2, rtr = 1, length = 7
452 
    write_register(8'd12, 8'h00); // data byte 1
453 
    write_register(8'd13, 8'h00); // data byte 2
454 
    write_register(8'd14, 8'h00); // data byte 3
455 
    write_register(8'd15, 8'h00); // data byte 4
456 
    write_register(8'd16, 8'h00); // data byte 5
457 
    write_register(8'd17, 8'h00); // data byte 6
458 
    write_register(8'd18, 8'h00); // data byte 7
459 
    write_register(8'd19, 8'h00); // data byte 8
460 
 
461 
    tx_bypassed = 1;    // When this signal is on, tx is not looped back to the rx.
462 
 
463 
    fork
464 
      begin
465 
//        tx_request_command;
466 
        self_reception_request_command;
467 
      end
468 
 
469 
      begin
470 
        #2200;
471 
 
472 
 
473 
        repeat (1)
474 
        begin
475 
          send_bit(0);  // SOF
476 
          send_bit(0);  // ID
477 
          send_bit(1);  // ID
478 
          send_bit(0);  // ID
479 
          send_bit(1);  // ID
480 
          send_bit(0);  // ID
481 
          send_bit(1);  // ID
482 
          send_bit(0);  // ID
483 
          send_bit(1);  // ID
484 
          send_bit(0);  // ID
485 
          send_bit(1);  // ID
486 
          send_bit(0);  // ID
487 
          send_bit(1);  // RTR
488 
          send_bit(0);  // IDE
489 
          send_bit(0);  // r0
490 
          send_bit(0);  // DLC
491 
          send_bit(1);  // DLC
492 
          send_bit(1);  // DLC
493 
          send_bit(1);  // DLC
494 
          send_bit(1);  // CRC
495 
          send_bit(1);  // CRC
496 
          send_bit(0);  // CRC stuff
497 
          send_bit(0);  // CRC 6
498 
          send_bit(0);  // CRC
499 
          send_bit(0);  // CRC
500 
          send_bit(0);  // CRC
501 
          send_bit(1);  // CRC  stuff
502 
          send_bit(0);  // CRC 0
503 
          send_bit(0);  // CRC
504 
          send_bit(1);  // CRC
505 
          send_bit(0);  // CRC
506 
          send_bit(1);  // CRC 5
507 
          send_bit(1);  // CRC
508 
          send_bit(0);  // CRC
509 
          send_bit(1);  // CRC
510 
          send_bit(1);  // CRC b
511 
          send_bit(1);  // CRC DELIM
512 
          send_bit(0);  // ACK
513 
          send_bit(1);  // ACK DELIM
514 
          send_bit(1);  // EOF
515 
          send_bit(1);  // EOF
516 
          send_bit(1);  // EOF
517 
          send_bit(1);  // EOF
518 
          send_bit(1);  // EOF
519 
          send_bit(1);  // EOF
520 
          send_bit(1);  // EOF
521 
          send_bit(1);  // INTER
522 
          send_bit(1);  // INTER
523 
          send_bit(1);  // INTER
524 
        end // repeat
525 
 
526 
 
527 
 
528 
      end
529 
 
530 
 
531 
    join
532 
 
533 
 
534 
 
535 
    read_receive_buffer;
536 
    release_rx_buffer_command;
537 
 
538 
    read_receive_buffer;
539 
    release_rx_buffer_command;
540 
    read_receive_buffer;
541 
 
542 
    #4000000;
543 
 
544 
  end
545 
endtask   //  manual_frame_basic
546 
 
547 
 
548 
 
549 
task manual_frame_ext;    // Testbench sends an extended format frame
550 
  begin
551 
 
552 
 
553 
    // Switch-on reset mode
554 
    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
555 
 
556 
    // Set Clock Divider register
557 
    extended_mode = 1'b1;
558 
    write_register(8'd31, {extended_mode, 7'h0});    // Setting the extended mode
559 
 
560 
    // Set Acceptance Code and Acceptance Mask registers
561 
    write_register(8'd16, 8'ha6); // acceptance code 0
562 
    write_register(8'd17, 8'h00); // acceptance code 1
563 
    write_register(8'd18, 8'h5a); // acceptance code 2
564 
    write_register(8'd19, 8'hac); // acceptance code 3
565 
    write_register(8'd20, 8'h00); // acceptance mask 0
566 
    write_register(8'd21, 8'h00); // acceptance mask 1
567 
    write_register(8'd22, 8'h00); // acceptance mask 2
568 
    write_register(8'd23, 8'h00); // acceptance mask 3
569 
 
570 
    repeat (100) @ (posedge clk);
571 
 
572 
    // Switch-off reset mode
573 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
574 
 
575 
    // After exiting the reset mode sending bus free
576 
    repeat (11) send_bit(1);
577 
 
578 
 
579 
    // Extended frame format
580 
    // Writing TX frame information + identifier + data
581 
    write_register(8'd16, 8'hc5);   // Frame format = 1, Remote transmision request = 1, DLC = 5
582 
    write_register(8'd17, 8'ha6);   // ID[28:21] = a6
583 
    write_register(8'd18, 8'h00);   // ID[20:13] = 00
584 
    write_register(8'd19, 8'h5a);   // ID[12:5]  = 5a
585 
    write_register(8'd20, 8'ha8);   // ID[4:0]   = 15
586 
    // write_register(8'd21, 8'h78); RTR does not send any data
587 
    // write_register(8'd22, 8'h9a);
588 
    // write_register(8'd23, 8'hbc);
589 
    // write_register(8'd24, 8'hde);
590 
    // write_register(8'd25, 8'hf0);
591 
    // write_register(8'd26, 8'h0f);
592 
    // write_register(8'd27, 8'hed);
593 
    // write_register(8'd28, 8'hcb);
594 
 
595 
 
596 
    // Enabling IRQ's (extended mode)
597 
    write_register(8'd4, 8'hff);
598 
 
599 
    // tx_bypassed = 1;    // When this signal is on, tx is not looped back to the rx.
600 
 
601 
    fork
602 
      begin
603 
        tx_request_command;
604 
//        self_reception_request_command;
605 
      end
606 
 
607 
      begin
608 
        #2400;
609 
 
610 
        repeat (1)
611 
        begin
612 
          send_bit(0);  // SOF
613 
          send_bit(1);  // ID
614 
          send_bit(0);  // ID
615 
          send_bit(1);  // ID
616 
          send_bit(0);  // ID a
617 
          send_bit(0);  // ID
618 
          send_bit(1);  // ID
619 
          send_bit(1);  // ID
620 
          send_bit(0);  // ID 6
621 
          send_bit(0);  // ID
622 
          send_bit(0);  // ID
623 
          send_bit(0);  // ID
624 
          send_bit(1);  // RTR
625 
          send_bit(1);  // IDE
626 
          send_bit(0);  // ID 0
627 
          send_bit(0);  // ID
628 
          send_bit(0);  // ID
629 
          send_bit(0);  // ID
630 
          send_bit(0);  // ID 0
631 
          send_bit(1);  // ID stuff
632 
          send_bit(0);  // ID
633 
          send_bit(1);  // ID
634 
          send_bit(0);  // ID
635 
          send_bit(1);  // ID 6
636 
          send_bit(1);  // ID
637 
          send_bit(0);  // ID
638 
          send_bit(1);  // ID
639 
          send_bit(0);  // ID a
640 
          send_bit(1);  // ID 1
641 
          send_bit(0);  // ID
642 
          send_bit(1);  // ID
643 
          send_bit(0);  // ID
644 
          send_bit(1);  // ID 5
645 
          send_bit(1);  // RTR
646 
          send_bit(0);  // r1
647 
          send_bit(0);  // r0
648 
          send_bit(0);  // DLC
649 
          send_bit(1);  // DLC
650 
          send_bit(0);  // DLC
651 
          send_bit(1);  // DLC
652 
          send_bit(1);  // CRC
653 
          send_bit(0);  // CRC
654 
          send_bit(0);  // CRC 4
655 
          send_bit(1);  // CRC
656 
          send_bit(1);  // CRC
657 
          send_bit(0);  // CRC
658 
          send_bit(1);  // CRC d
659 
          send_bit(0);  // CRC
660 
          send_bit(0);  // CRC
661 
          send_bit(1);  // CRC
662 
          send_bit(1);  // CRC 3
663 
          send_bit(1);  // CRC
664 
          send_bit(0);  // CRC
665 
          send_bit(0);  // CRC
666 
          send_bit(1);  // CRC 9
667 
          send_bit(1);  // CRC DELIM
668 
          send_bit(0);  // ACK
669 
          send_bit(1);  // ACK DELIM
670 
          send_bit(1);  // EOF
671 
          send_bit(1);  // EOF
672 
          send_bit(1);  // EOF
673 
          send_bit(1);  // EOF
674 
          send_bit(1);  // EOF
675 
          send_bit(1);  // EOF
676 
          send_bit(1);  // EOF
677 
          send_bit(1);  // INTER
678 
          send_bit(1);  // INTER
679 
          send_bit(1);  // INTER
680 
        end // repeat
681 
 
682 
 
683 
      end
684 
 
685 
    join
686 
 
687 
 
688 
 
689 
    read_receive_buffer;
690 
    release_rx_buffer_command;
691 
 
692 
    read_receive_buffer;
693 
    release_rx_buffer_command;
694 
    read_receive_buffer;
695 
 
696 
    // Read irq register
697 
    #1 read_register(8'd3);
698 
 
699 
    // Read error code capture register
700 
    read_register(8'd12);
701 
 
702 
    // Read error capture code register
703 
//    read_register(8'd12);
704 
 
705 
    #4000000;
706 
 
707 
  end
708 
endtask   //  manual_frame_ext
709 
 
710 
 
711 
 
712 
task bus_off_test;    // Testbench sends a frame
713 
  begin
714 
 
715 
    write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8
716 
    write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7
717 
    write_register(8'd12, 8'h00); // data byte 1
718 
    write_register(8'd13, 8'h00); // data byte 2
719 
    write_register(8'd14, 8'h00); // data byte 3
720 
    write_register(8'd15, 8'h00); // data byte 4
721 
    write_register(8'd16, 8'h00); // data byte 5
722 
    write_register(8'd17, 8'h00); // data byte 6
723 
    write_register(8'd18, 8'h00); // data byte 7
724 
    write_register(8'd19, 8'h00); // data byte 8
725 
 
726 
    fork
727 
      begin
728 
        tx_request_command;
729 
      end
730 
 
731 
      begin
732 
        #2000;
733 
 
734 
        repeat (16)
735 
        begin
736 
          send_bit(0);  // SOF
737 
          send_bit(1);  // ID
738 
          send_bit(1);  // ID
739 
          send_bit(1);  // ID
740 
          send_bit(0);  // ID
741 
          send_bit(1);  // ID
742 
          send_bit(0);  // ID
743 
          send_bit(0);  // ID
744 
          send_bit(0);  // ID
745 
          send_bit(1);  // ID
746 
          send_bit(0);  // ID
747 
          send_bit(1);  // ID
748 
          send_bit(1);  // RTR
749 
          send_bit(0);  // IDE
750 
          send_bit(0);  // r0
751 
          send_bit(0);  // DLC
752 
          send_bit(1);  // DLC
753 
          send_bit(1);  // DLC
754 
          send_bit(1);  // DLC
755 
          send_bit(1);  // CRC
756 
          send_bit(0);  // CRC
757 
          send_bit(0);  // CRC
758 
          send_bit(1);  // CRC
759 
          send_bit(1);  // CRC
760 
          send_bit(1);  // CRC
761 
          send_bit(0);  // CRC
762 
          send_bit(1);  // CRC
763 
          send_bit(0);  // CRC
764 
          send_bit(0);  // CRC
765 
          send_bit(1);  // CRC
766 
          send_bit(1);  // CRC
767 
          send_bit(1);  // CRC
768 
          send_bit(1);  // CRC
769 
          send_bit(1);  // CRC
770 
          send_bit(1);  // CRC DELIM
771 
          send_bit(1);  // ACK            ack error
772 
          send_bit(0);  // ERROR
773 
          send_bit(0);  // ERROR
774 
          send_bit(0);  // ERROR
775 
          send_bit(0);  // ERROR
776 
          send_bit(0);  // ERROR
777 
          send_bit(0);  // ERROR
778 
          send_bit(1);  // ERROR DELIM
779 
          send_bit(1);  // ERROR DELIM
780 
          send_bit(1);  // ERROR DELIM
781 
          send_bit(1);  // ERROR DELIM
782 
          send_bit(1);  // ERROR DELIM
783 
          send_bit(1);  // ERROR DELIM
784 
          send_bit(1);  // ERROR DELIM
785 
          send_bit(1);  // ERROR DELIM
786 
          send_bit(1);  // INTER
787 
          send_bit(1);  // INTER
788 
          send_bit(1);  // INTER
789 
        end // repeat
790 
 
791 
        // Node is error passive now.
792 
 
793 
        // Read irq register (error interrupt should be cleared now.
794 
        read_register(8'd3);
795 
 
796 
        repeat (20)
797 
 
798 
        begin
799 
          send_bit(0);  // SOF
800 
          send_bit(1);  // ID
801 
          send_bit(1);  // ID
802 
          send_bit(1);  // ID
803 
          send_bit(0);  // ID
804 
          send_bit(1);  // ID
805 
          send_bit(0);  // ID
806 
          send_bit(0);  // ID
807 
          send_bit(0);  // ID
808 
          send_bit(1);  // ID
809 
          send_bit(0);  // ID
810 
          send_bit(1);  // ID
811 
          send_bit(1);  // RTR
812 
          send_bit(0);  // IDE
813 
          send_bit(0);  // r0
814 
          send_bit(0);  // DLC
815 
          send_bit(1);  // DLC
816 
          send_bit(1);  // DLC
817 
          send_bit(1);  // DLC
818 
          send_bit(1);  // CRC
819 
          send_bit(0);  // CRC
820 
          send_bit(0);  // CRC
821 
          send_bit(1);  // CRC
822 
          send_bit(1);  // CRC
823 
          send_bit(1);  // CRC
824 
          send_bit(0);  // CRC
825 
          send_bit(1);  // CRC
826 
          send_bit(0);  // CRC
827 
          send_bit(0);  // CRC
828 
          send_bit(1);  // CRC
829 
          send_bit(1);  // CRC
830 
          send_bit(1);  // CRC
831 
          send_bit(1);  // CRC
832 
          send_bit(1);  // CRC
833 
          send_bit(1);  // CRC DELIM
834 
          send_bit(1);  // ACK            ack error
835 
          send_bit(0);  // ERROR
836 
          send_bit(0);  // ERROR
837 
          send_bit(0);  // ERROR
838 
          send_bit(0);  // ERROR
839 
          send_bit(0);  // ERROR
840 
          send_bit(0);  // ERROR
841 
          send_bit(1);  // ERROR DELIM
842 
          send_bit(1);  // ERROR DELIM
843 
          send_bit(1);  // ERROR DELIM
844 
          send_bit(1);  // ERROR DELIM
845 
          send_bit(1);  // ERROR DELIM
846 
          send_bit(1);  // ERROR DELIM
847 
          send_bit(1);  // ERROR DELIM
848 
          send_bit(1);  // ERROR DELIM
849 
          send_bit(1);  // INTER
850 
          send_bit(1);  // INTER
851 
          send_bit(1);  // INTER
852 
          send_bit(1);  // SUSPEND
853 
          send_bit(1);  // SUSPEND
854 
          send_bit(1);  // SUSPEND
855 
          send_bit(1);  // SUSPEND
856 
          send_bit(1);  // SUSPEND
857 
          send_bit(1);  // SUSPEND
858 
          send_bit(1);  // SUSPEND
859 
          send_bit(1);  // SUSPEND
860 
        end // repeat
861 
 
862 
        // Node is bus-off now
863 
 
864 
 
865 
        // Read irq register (error interrupt should be cleared now.
866 
        read_register(8'd3);
867 
 
868 
 
869 
 
870 
        #100000;
871 
 
872 
        // Switch-off reset mode
873 
        write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
874 
 
875 
        repeat (64 * 11)
876 
        begin
877 
          send_bit(1);
878 
        end // repeat
879 
 
880 
        // Read irq register (error interrupt should be cleared now.
881 
        read_register(8'd3);
882 
 
883 
        repeat (64 * 11)
884 
        begin
885 
          send_bit(1);
886 
        end // repeat
887 
 
888 
 
889 
 
890 
        // Read irq register (error interrupt should be cleared now.
891 
        read_register(8'd3);
892 
 
893 
      end
894 
 
895 
 
896 
 
897 
    join
898 
 
899 
 
900 
 
901 
    fork
902 
      begin
903 
        tx_request_command;
904 
      end
905 
 
906 
      begin
907 
        #1100;
908 
 
909 
        send_bit(1);    // To spend some time before transmitter is ready.
910 
 
911 
        repeat (1)
912 
        begin
913 
          send_bit(0);  // SOF
914 
          send_bit(1);  // ID
915 
          send_bit(1);  // ID
916 
          send_bit(1);  // ID
917 
          send_bit(0);  // ID
918 
          send_bit(1);  // ID
919 
          send_bit(0);  // ID
920 
          send_bit(0);  // ID
921 
          send_bit(0);  // ID
922 
          send_bit(1);  // ID
923 
          send_bit(0);  // ID
924 
          send_bit(1);  // ID
925 
          send_bit(1);  // RTR
926 
          send_bit(0);  // IDE
927 
          send_bit(0);  // r0
928 
          send_bit(0);  // DLC
929 
          send_bit(1);  // DLC
930 
          send_bit(1);  // DLC
931 
          send_bit(1);  // DLC
932 
          send_bit(1);  // CRC
933 
          send_bit(0);  // CRC
934 
          send_bit(0);  // CRC
935 
          send_bit(1);  // CRC
936 
          send_bit(1);  // CRC
937 
          send_bit(1);  // CRC
938 
          send_bit(0);  // CRC
939 
          send_bit(1);  // CRC
940 
          send_bit(0);  // CRC
941 
          send_bit(0);  // CRC
942 
          send_bit(1);  // CRC
943 
          send_bit(1);  // CRC
944 
          send_bit(1);  // CRC
945 
          send_bit(1);  // CRC
946 
          send_bit(1);  // CRC
947 
          send_bit(1);  // CRC DELIM
948 
          send_bit(0);  // ACK
949 
          send_bit(1);  // ACK DELIM
950 
          send_bit(1);  // EOF
951 
          send_bit(1);  // EOF
952 
          send_bit(1);  // EOF
953 
          send_bit(1);  // EOF
954 
          send_bit(1);  // EOF
955 
          send_bit(1);  // EOF
956 
          send_bit(1);  // EOF
957 
          send_bit(1);  // INTER
958 
          send_bit(1);  // INTER
959 
          send_bit(1);  // INTER
960 
        end // repeat
961 
      end
962 
 
963 
    join
964 
 
965 
    read_receive_buffer;
966 
    release_rx_buffer_command;
967 
    read_receive_buffer;
968 
    release_rx_buffer_command;
969 
    read_receive_buffer;
970 
 
971 
    #4000000;
972 
 
973 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
974 
 
975 
    #1000000;
976 
 
977 
  end
978 
endtask   // bus_off_test
979 
 
980 
 
981 
 
982 
task send_frame_basic;    // CAN IP core sends frames
983 
  begin
984 
 
985 
    write_register(8'd10, 8'hea); // Writing ID[10:3] = 0xea
986 
    write_register(8'd11, 8'h28); // Writing ID[2:0] = 0x1, rtr = 0, length = 8
987 
    write_register(8'd12, 8'h56); // data byte 1
988 
    write_register(8'd13, 8'h78); // data byte 2
989 
    write_register(8'd14, 8'h9a); // data byte 3
990 
    write_register(8'd15, 8'hbc); // data byte 4
991 
    write_register(8'd16, 8'hde); // data byte 5
992 
    write_register(8'd17, 8'hf0); // data byte 6
993 
    write_register(8'd18, 8'h0f); // data byte 7
994 
    write_register(8'd19, 8'hed); // data byte 8
995 
 
996 
 
997 
    // Enable irqs (basic mode)
998 
    write_register(8'd0, 8'h1e);
999 
 
1000 
 
1001 
 
1002 
    fork
1003 
 
1004 
      begin
1005 
        #1500;
1006 
        $display("\n\nStart receiving data from CAN bus");
1007 
        receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
1008 
        receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
1009 
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc
1010 
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc
1011 
        receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc
1012 
      end
1013 
 
1014 
      begin
1015 
        tx_request_command;
1016 
      end
1017 
 
1018 
      begin
1019 
        // Transmitting acknowledge
1020 
        wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
1021 
        #1 rx = 0;
1022 
        wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim);
1023 
        #1 rx = 1;
1024 
      end
1025 
 
1026 
 
1027 
    join
1028 
 
1029 
    read_receive_buffer;
1030 
    release_rx_buffer_command;
1031 
    release_rx_buffer_command;
1032 
    read_receive_buffer;
1033 
    release_rx_buffer_command;
1034 
    read_receive_buffer;
1035 
    release_rx_buffer_command;
1036 
    read_receive_buffer;
1037 
    release_rx_buffer_command;
1038 
    read_receive_buffer;
1039 
 
1040 
    #200000;
1041 
 
1042 
    read_receive_buffer;
1043 
 
1044 
    // Read irq register
1045 
    read_register(8'd3);
1046 
    #1000;
1047 
 
1048 
  end
1049 
endtask   // send_frame_basic
1050 
 
1051 
 
1052 
 
1053 
task send_frame_extended;    // CAN IP core sends basic or extended frames in extended mode
1054 
  begin
1055 
 
1056 
    // Switch-on reset mode
1057 
    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
1058 
 
1059 
    // Set Clock Divider register
1060 
    extended_mode = 1'b1;
1061 
    write_register(8'd31, {extended_mode, 7'h0});    // Setting the extended mode
1062 
 
1063 
    // Set Acceptance Code and Acceptance Mask registers
1064 
    write_register(8'd16, 8'ha6); // acceptance code 0
1065 
    write_register(8'd17, 8'hb0); // acceptance code 1
1066 
    write_register(8'd18, 8'h12); // acceptance code 2
1067 
    write_register(8'd19, 8'h30); // acceptance code 3
1068 
    write_register(8'd20, 8'h00); // acceptance mask 0
1069 
    write_register(8'd21, 8'h00); // acceptance mask 1
1070 
    write_register(8'd22, 8'h00); // acceptance mask 2
1071 
    write_register(8'd23, 8'h00); // acceptance mask 3
1072 
 
1073 
    // Switch-off reset mode
1074 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
1075 
 
1076 
    // After exiting the reset mode sending bus free
1077 
    repeat (11) send_bit(1);
1078 
 
1079 
 
1080 
/*  Basic frame format
1081 
    // Writing TX frame information + identifier + data
1082 
    write_register(8'd16, 8'h45);   // Frame format = 0, Remote transmision request = 1, DLC = 5
1083 
    write_register(8'd17, 8'ha6);   // ID[28:21] = a6
1084 
    write_register(8'd18, 8'ha0);   // ID[20:18] = 5
1085 
    // write_register(8'd19, 8'h78); RTR does not send any data
1086 
    // write_register(8'd20, 8'h9a);
1087 
    // write_register(8'd21, 8'hbc);
1088 
    // write_register(8'd22, 8'hde);
1089 
    // write_register(8'd23, 8'hf0);
1090 
    // write_register(8'd24, 8'h0f);
1091 
    // write_register(8'd25, 8'hed);
1092 
    // write_register(8'd26, 8'hcb);
1093 
    // write_register(8'd27, 8'ha9);
1094 
    // write_register(8'd28, 8'h87);
1095 
*/
1096 
 
1097 
    // Extended frame format
1098 
    // Writing TX frame information + identifier + data
1099 
    write_register(8'd16, 8'hc5);   // Frame format = 1, Remote transmision request = 1, DLC = 5
1100 
    write_register(8'd17, 8'ha6);   // ID[28:21] = a6
1101 
    write_register(8'd18, 8'h00);   // ID[20:13] = 00
1102 
    write_register(8'd19, 8'h5a);   // ID[12:5]  = 5a
1103 
    write_register(8'd20, 8'ha8);   // ID[4:0]   = 15
1104 
    // write_register(8'd21, 8'h78); RTR does not send any data
1105 
    // write_register(8'd22, 8'h9a);
1106 
    // write_register(8'd23, 8'hbc);
1107 
    // write_register(8'd24, 8'hde);
1108 
    // write_register(8'd25, 8'hf0);
1109 
    // write_register(8'd26, 8'h0f);
1110 
    // write_register(8'd27, 8'hed);
1111 
    // write_register(8'd28, 8'hcb);
1112 
 
1113 
 
1114 
    // Enabling IRQ's (extended mode)
1115 
    write_register(8'd4, 8'hff);
1116 
 
1117 
 
1118 
    fork
1119 
      begin
1120 
        #2700;
1121 
        $display("\n\nStart receiving data from CAN bus");
1122 
        /* Standard frame format
1123 
        receive_frame(0, 0, {26'h00000a0, 3'h1}, 4'h1, 15'h2d9c); // mode, rtr, id, length, crc
1124 
        receive_frame(0, 0, {26'h00000a0, 3'h1}, 4'h2, 15'h46b4); // mode, rtr, id, length, crc
1125 
        receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h0, 15'h42cd); // mode, rtr, id, length, crc
1126 
        receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h1, 15'h555f); // mode, rtr, id, length, crc
1127 
        receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h2, 15'h6742); // mode, rtr, id, length, crc
1128 
        */
1129 
 
1130 
        // Extended frame format
1131 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h1, 15'h2d22); // mode, rtr, id, length, crc
1132 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h2, 15'h3d2d); // mode, rtr, id, length, crc
1133 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h0, 15'h23aa); // mode, rtr, id, length, crc
1134 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h1, 15'h2d22); // mode, rtr, id, length, crc
1135 
        receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h2, 15'h3d2d); // mode, rtr, id, length, crc
1136 
 
1137 
      end
1138 
 
1139 
      begin
1140 
        tx_request_command;
1141 
      end
1142 
 
1143 
      begin
1144 
        // Transmitting acknowledge
1145 
        wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
1146 
        #1 rx = 0;
1147 
        wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim);
1148 
        #1 rx = 1;
1149 
      end
1150 
 
1151 
      begin   // Reading irq and arbitration lost capture register
1152 
 
1153 
        repeat(1)
1154 
          begin
1155 
            while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
1156 
              begin
1157 
                @ (posedge clk);
1158 
              end
1159 
 
1160 
            // Read irq register
1161 
            #1 read_register(8'd3);
1162 
 
1163 
            // Read arbitration lost capture register
1164 
            read_register(8'd11);
1165 
          end
1166 
 
1167 
 
1168 
        repeat(1)
1169 
          begin
1170 
            while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
1171 
              begin
1172 
                @ (posedge clk);
1173 
              end
1174 
 
1175 
            // Read irq register
1176 
            #1 read_register(8'd3);
1177 
          end
1178 
 
1179 
        repeat(1)
1180 
          begin
1181 
            while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
1182 
              begin
1183 
                @ (posedge clk);
1184 
              end
1185 
 
1186 
            // Read arbitration lost capture register
1187 
            read_register(8'd11);
1188 
          end
1189 
 
1190 
      end
1191 
 
1192 
    join
1193 
 
1194 
    read_receive_buffer;
1195 
    release_rx_buffer_command;
1196 
    release_rx_buffer_command;
1197 
    read_receive_buffer;
1198 
    release_rx_buffer_command;
1199 
    read_receive_buffer;
1200 
    release_rx_buffer_command;
1201 
    read_receive_buffer;
1202 
    release_rx_buffer_command;
1203 
    read_receive_buffer;
1204 
 
1205 
    #200000;
1206 
 
1207 
    read_receive_buffer;
1208 
 
1209 
    // Read irq register
1210 
    read_register(8'd3);
1211 
    #1000;
1212 
 
1213 
  end
1214 
endtask   // send_frame_extended
1215 
 
1216 
 
1217 
 
1218 
task self_reception_request;    // CAN IP core sends sets self reception mode and transmits a msg. This test runs in EXTENDED mode
1219 
  begin
1220 
 
1221 
    // Switch-on reset mode
1222 
    write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
1223 
 
1224 
    // Set Clock Divider register
1225 
    extended_mode = 1'b1;
1226 
    write_register(8'd31, {extended_mode, 7'h0});    // Setting the extended mode
1227 
 
1228 
    // Set Acceptance Code and Acceptance Mask registers
1229 
    write_register(8'd16, 8'ha6); // acceptance code 0
1230 
    write_register(8'd17, 8'hb0); // acceptance code 1
1231 
    write_register(8'd18, 8'h12); // acceptance code 2
1232 
    write_register(8'd19, 8'h30); // acceptance code 3
1233 
    write_register(8'd20, 8'h00); // acceptance mask 0
1234 
    write_register(8'd21, 8'h00); // acceptance mask 1
1235 
    write_register(8'd22, 8'h00); // acceptance mask 2
1236 
    write_register(8'd23, 8'h00); // acceptance mask 3
1237 
 
1238 
    // Setting the "self test mode"
1239 
    write_register(8'd0, 8'h4);
1240 
 
1241 
    // Switch-off reset mode
1242 
    write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
1243 
 
1244 
    // After exiting the reset mode sending bus free
1245 
    repeat (11) send_bit(1);
1246 
 
1247 
 
1248 
    // Writing TX frame information + identifier + data
1249 
    write_register(8'd16, 8'h45);   // Frame format = 0, Remote transmision request = 1, DLC = 5
1250 
    write_register(8'd17, 8'ha6);   // ID[28:21] = a6
1251 
    write_register(8'd18, 8'ha0);   // ID[20:18] = 5
1252 
    // write_register(8'd19, 8'h78); RTR does not send any data
1253 
    // write_register(8'd20, 8'h9a);
1254 
    // write_register(8'd21, 8'hbc);
1255 
    // write_register(8'd22, 8'hde);
1256 
    // write_register(8'd23, 8'hf0);
1257 
    // write_register(8'd24, 8'h0f);
1258 
    // write_register(8'd25, 8'hed);
1259 
    // write_register(8'd26, 8'hcb);
1260 
    // write_register(8'd27, 8'ha9);
1261 
    // write_register(8'd28, 8'h87);
1262 
 
1263 
 
1264 
    // Enabling IRQ's (extended mode)
1265 
    write_register(8'd4, 8'hff);
1266 
 
1267 
    self_reception_request_command;
1268 
 
1269 
    #400000;
1270 
 
1271 
    read_receive_buffer;
1272 
    release_rx_buffer_command;
1273 
    release_rx_buffer_command;
1274 
    read_receive_buffer;
1275 
    release_rx_buffer_command;
1276 
    read_receive_buffer;
1277 
    release_rx_buffer_command;
1278 
    read_receive_buffer;
1279 
    release_rx_buffer_command;
1280 
    read_receive_buffer;
1281 
 
1282 
 
1283 
    read_receive_buffer;
1284 
 
1285 
    // Read irq register
1286 
    read_register(8'd3);
1287 
    #1000;
1288 
 
1289 
  end
1290 
endtask   // self_reception_request
1291 
 
1292 
 
1293 
 
1294 
task test_empty_fifo;
1295 
  begin
1296 
 
1297 
    // Enable irqs (basic mode)
1298 
    write_register(8'd0, 8'h1e);
1299 
 
1300 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h3, 15'h56a9); // mode, rtr, id, length, crc
1301 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h7, 15'h391d); // mode, rtr, id, length, crc
1302 
 
1303 
    read_receive_buffer;
1304 
    fifo_info;
1305 
 
1306 
    release_rx_buffer_command;
1307 
    $display("\n\n");
1308 
    read_receive_buffer;
1309 
    fifo_info;
1310 
 
1311 
    release_rx_buffer_command;
1312 
    $display("\n\n");
1313 
    read_receive_buffer;
1314 
    fifo_info;
1315 
 
1316 
    release_rx_buffer_command;
1317 
    $display("\n\n");
1318 
    read_receive_buffer;
1319 
    fifo_info;
1320 
 
1321 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1322 
 
1323 
    $display("\n\n");
1324 
    read_receive_buffer;
1325 
    fifo_info;
1326 
 
1327 
    release_rx_buffer_command;
1328 
    $display("\n\n");
1329 
    read_receive_buffer;
1330 
    fifo_info;
1331 
 
1332 
    release_rx_buffer_command;
1333 
    $display("\n\n");
1334 
    read_receive_buffer;
1335 
    fifo_info;
1336 
  end
1337 
endtask
1338 
 
1339 
 
1340 
 
1341 
task test_empty_fifo_ext;
1342 
  begin
1343 
    receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
1344 
    receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
1345 
 
1346 
    read_receive_buffer;
1347 
    fifo_info;
1348 
 
1349 
    release_rx_buffer_command;
1350 
    $display("\n\n");
1351 
    read_receive_buffer;
1352 
    fifo_info;
1353 
 
1354 
    release_rx_buffer_command;
1355 
    $display("\n\n");
1356 
    read_receive_buffer;
1357 
    fifo_info;
1358 
 
1359 
    release_rx_buffer_command;
1360 
    $display("\n\n");
1361 
    read_receive_buffer;
1362 
    fifo_info;
1363 
 
1364 
    receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
1365 
 
1366 
    $display("\n\n");
1367 
    read_receive_buffer;
1368 
    fifo_info;
1369 
 
1370 
    release_rx_buffer_command;
1371 
    $display("\n\n");
1372 
    read_receive_buffer;
1373 
    fifo_info;
1374 
 
1375 
    release_rx_buffer_command;
1376 
    $display("\n\n");
1377 
    read_receive_buffer;
1378 
    fifo_info;
1379 
  end
1380 
endtask
1381 
 
1382 
 
1383 
 
1384 
task test_full_fifo;
1385 
  begin
1386 
 
1387 
    // Enable irqs (basic mode)
1388 
    write_register(8'd0, 8'h1e);
1389 
 
1390 
    $display("\n\n");
1391 
 
1392 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
1393 
    fifo_info;
1394 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
1395 
    fifo_info;
1396 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
1397 
    fifo_info;
1398 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h3, 15'h56a9); // mode, rtr, id, length, crc
1399 
    fifo_info;
1400 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h4, 15'h3124); // mode, rtr, id, length, crc
1401 
    fifo_info;
1402 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h5, 15'h6944); // mode, rtr, id, length, crc
1403 
    fifo_info;
1404 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h6, 15'h5182); // mode, rtr, id, length, crc
1405 
    fifo_info;
1406 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h7, 15'h391d); // mode, rtr, id, length, crc
1407 
    fifo_info;
1408 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1409 
    fifo_info;
1410 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1411 
    fifo_info;
1412 
    $display("FIFO should be full now");
1413 
 
1414 
    // Following one is accepted with overrun
1415 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1416 
    fifo_info;
1417 
 
1418 
    release_rx_buffer_command;
1419 
    fifo_info;
1420 
 
1421 
    // Space just enough for the following frame.
1422 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
1423 
    fifo_info;
1424 
 
1425 
    // Following accepted with overrun
1426 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1427 
    fifo_info;
1428 
//    read_overrun_info(0, 15);
1429 
 
1430 
    release_rx_buffer_command;
1431 
    release_rx_buffer_command;
1432 
 
1433 
    release_rx_buffer_command;
1434 
    read_receive_buffer;
1435 
    fifo_info;
1436 
    receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
1437 
    fifo_info;
1438 
//    read_overrun_info(0, 15);
1439 
    $display("\n\n");
1440 
 
1441 
    release_rx_buffer_command;
1442 
    read_receive_buffer;
1443 
    fifo_info;
1444 
 
1445 
    release_rx_buffer_command;
1446 
    read_receive_buffer;
1447 
    fifo_info;
1448 
 
1449 
    release_rx_buffer_command;
1450 
    read_receive_buffer;
1451 
    fifo_info;
1452 
 
1453 
    release_rx_buffer_command;
1454 
    read_receive_buffer;
1455 
    fifo_info;
1456 
 
1457 
    release_rx_buffer_command;
1458 
    read_receive_buffer;
1459 
    fifo_info;
1460 
 
1461 
    release_rx_buffer_command;
1462 
    read_receive_buffer;
1463 
    fifo_info;
1464 
 
1465 
    clear_data_overrun_command;
1466 
 
1467 
    release_rx_buffer_command;
1468 
    read_receive_buffer;
1469 
    fifo_info;
1470 
 
1471 
    release_rx_buffer_command;
1472 
    read_receive_buffer;
1473 
    fifo_info;
1474 
 
1475 
    clear_data_overrun_command;
1476 
 
1477 
    release_rx_buffer_command;
1478 
    read_receive_buffer;
1479 
    fifo_info;
1480 
 
1481 
    release_rx_buffer_command;
1482 
    read_receive_buffer;
1483 
    fifo_info;
1484 
 
1485 
    release_rx_buffer_command;
1486 
    read_receive_buffer;
1487 
    fifo_info;
1488 
 
1489 
    release_rx_buffer_command;
1490 
    read_receive_buffer;
1491 
    fifo_info;
1492 
 
1493 
    release_rx_buffer_command;
1494 
    read_receive_buffer;
1495 
    fifo_info;
1496 
 
1497 
    // Read irq register
1498 
    read_register(8'd3);
1499 
 
1500 
    // Read irq register
1501 
    read_register(8'd3);
1502 
    #1000;
1503 
 
1504 
  end
1505 
endtask
1506 
 
1507 
 
1508 
 
1509 
task test_full_fifo_ext;
1510 
  begin
1511 
    release_rx_buffer_command;
1512 
    $display("\n\n");
1513 
    read_receive_buffer;
1514 
    fifo_info;
1515 
 
1516 
    receive_frame(1, 0, 29'h14d60246, 4'h0, 15'h6f54); // mode, rtr, id, length, crc
1517 
    read_receive_buffer;
1518 
    fifo_info;
1519 
    receive_frame(1, 0, 29'h14d60246, 4'h1, 15'h6d38); // mode, rtr, id, length, crc
1520 
    read_receive_buffer;
1521 
    fifo_info;
1522 
    receive_frame(1, 0, 29'h14d60246, 4'h2, 15'h053e); // mode, rtr, id, length, crc
1523 
    fifo_info;
1524 
    read_receive_buffer;
1525 
    receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
1526 
    fifo_info;
1527 
    receive_frame(1, 0, 29'h14d60246, 4'h4, 15'h4bba); // mode, rtr, id, length, crc
1528 
    fifo_info;
1529 
    receive_frame(1, 0, 29'h14d60246, 4'h5, 15'h4d7d); // mode, rtr, id, length, crc
1530 
    fifo_info;
1531 
    receive_frame(1, 0, 29'h14d60246, 4'h6, 15'h6f40); // mode, rtr, id, length, crc
1532 
    fifo_info;
1533 
    receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
1534 
    fifo_info;
1535 
//    read_overrun_info(0, 10);
1536 
 
1537 
    release_rx_buffer_command;
1538 
    release_rx_buffer_command;
1539 
    fifo_info;
1540 
    receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
1541 
    fifo_info;
1542 
//    read_overrun_info(0, 15);
1543 
    $display("\n\n");
1544 
 
1545 
    release_rx_buffer_command;
1546 
    read_receive_buffer;
1547 
    fifo_info;
1548 
 
1549 
    release_rx_buffer_command;
1550 
    read_receive_buffer;
1551 
    fifo_info;
1552 
 
1553 
    release_rx_buffer_command;
1554 
    read_receive_buffer;
1555 
    fifo_info;
1556 
 
1557 
    release_rx_buffer_command;
1558 
    read_receive_buffer;
1559 
    fifo_info;
1560 
 
1561 
    release_rx_buffer_command;
1562 
    read_receive_buffer;
1563 
    fifo_info;
1564 
 
1565 
    release_rx_buffer_command;
1566 
    read_receive_buffer;
1567 
    fifo_info;
1568 
 
1569 
    release_rx_buffer_command;
1570 
    read_receive_buffer;
1571 
    fifo_info;
1572 
 
1573 
  end
1574 
endtask
1575 
 
1576 
 
1577 
/*
1578 
task initialize_fifo;
1579 
  integer i;
1580 
  begin
1581 
    for (i=0; i<32; i=i+1)
1582 
      begin
1583 
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i] = 0;
1584 
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i] = 0;
1585 
      end
1586 
 
1587 
    for (i=0; i<64; i=i+1)
1588 
      begin
1589 
        can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo[i] = 0;
1590 
      end
1591 
 
1592 
    $display("(%0t) Fifo initialized", $time);
1593 
  end
1594 
endtask
1595 
*/
1596 
/*
1597 
task read_overrun_info;
1598 
  input [4:0] start_addr;
1599 
  input [4:0] end_addr;
1600 
  integer i;
1601 
  begin
1602 
    for (i=start_addr; i<=end_addr; i=i+1)
1603 
      begin
1604 
        $display("len[0x%0x]=0x%0x", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i]);
1605 
        $display("overrun[0x%0x]=0x%0x\n", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i]);
1606 
      end
1607 
  end
1608 
endtask
1609 
*/
1610 
 
1611 
task fifo_info;   // Displaying how many packets and how many bytes are in fifo. Not working when wr_info_pointer is smaller than rd_info_pointer.
1612 
  begin
1613 
      $display("(%0t) Currently %0d bytes in fifo (%0d packets)", $time, can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_cnt,
1614 
      (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_info_pointer - can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer));
1615 
end
1616 
endtask
1617 
 
1618 
 
1619 
task read_register;
1620 
  input [7:0] reg_addr;
1621 
 
1622 
  `ifdef CAN_WISHBONE_IF
1623 
    begin
1624 
      wait (wb_free);
1625 
      wb_free = 0;
1626 
      @ (posedge wb_clk_i);
1627 
      #1;
1628 
      cs_can = 1;
1629 
      wb_adr_i = reg_addr;
1630 
      wb_cyc_i = 1;
1631 
      wb_stb_i = 1;
1632 
      wb_we_i = 0;
1633 
      wait (wb_ack_o);
1634 
      $display("(%0t) Reading register [%0d] = 0x%0x", $time, wb_adr_i, wb_dat_o);
1635 
      @ (posedge wb_clk_i);
1636 
      #1;
1637 
      wb_adr_i = 'hz;
1638 
      wb_cyc_i = 0;
1639 
      wb_stb_i = 0;
1640 
      wb_we_i = 'hz;
1641 
      cs_can = 0;
1642 
      wb_free = 1;
1643 
    end
1644 
  `else
1645 
    begin
1646 
      wait (port_free);
1647 
      port_free = 0;
1648 
      @ (posedge clk);
1649 
      #1;
1650 
      cs_can = 1;
1651 
      @ (negedge clk);
1652 
      #1;
1653 
      ale_i = 1;
1654 
      port_0_en = 1;
1655 
      port_0_o = reg_addr;
1656 
      @ (negedge clk);
1657 
      #1;
1658 
      ale_i = 0;
1659 
      #90;            // 73 - 103 ns
1660 
      port_0_en = 0;
1661 
      rd_i = 1;
1662 
      #158;
1663 
      $display("(%0t) Reading register [%0d] = 0x%0x", $time, can_testbench.i_can_top.addr_latched, port_0_i);
1664 
      #1;
1665 
      rd_i = 0;
1666 
      cs_can = 0;
1667 
      port_free = 1;
1668 
    end
1669 
  `endif
1670 
endtask
1671 
 
1672 
 
1673 
task write_register;
1674 
  input [7:0] reg_addr;
1675 
  input [7:0] reg_data;
1676 
 
1677 
  `ifdef CAN_WISHBONE_IF
1678 
    begin
1679 
      wait (wb_free);
1680 
      wb_free = 0;
1681 
      @ (posedge wb_clk_i);
1682 
      #1;
1683 
      cs_can = 1;
1684 
      wb_adr_i = reg_addr;
1685 
      wb_dat_i = reg_data;
1686 
      wb_cyc_i = 1;
1687 
      wb_stb_i = 1;
1688 
      wb_we_i = 1;
1689 
      wait (wb_ack_o);
1690 
      @ (posedge wb_clk_i);
1691 
      #1;
1692 
      wb_adr_i = 'hz;
1693 
      wb_dat_i = 'hz;
1694 
      wb_cyc_i = 0;
1695 
      wb_stb_i = 0;
1696 
      wb_we_i = 'hz;
1697 
      cs_can = 0;
1698 
      wb_free = 1;
1699 
    end
1700 
  `else
1701 
    begin
1702 
      wait (port_free);
1703 
      port_free = 0;
1704 
      @ (posedge clk);
1705 
      #1;
1706 
      cs_can = 1;
1707 
      @ (negedge clk);
1708 
      #1;
1709 
      ale_i = 1;
1710 
      port_0_en = 1;
1711 
      port_0_o = reg_addr;
1712 
      @ (negedge clk);
1713 
      #1;
1714 
      ale_i = 0;
1715 
      #90;            // 73 - 103 ns
1716 
      port_0_o = reg_data;
1717 
      wr_i = 1;
1718 
      #158;
1719 
      wr_i = 0;
1720 
      port_0_en = 0;
1721 
      cs_can = 0;
1722 
      port_free = 1;
1723 
    end
1724 
  `endif
1725 
endtask
1726 
 
1727 
 
1728 
task read_receive_buffer;
1729 
  integer i;
1730 
  begin
1731 
    $display("\n\n(%0t)", $time);
1732 
    if(extended_mode)   // Extended mode
1733 
      begin
1734 
        for (i=8'd16; i<=8'd28; i=i+1)
1735 
          read_register(i);
1736 
        if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun)
1737 
          $display("\nWARNING: Above packet was received with overrun.");
1738 
      end
1739 
    else
1740 
      begin
1741 
        for (i=8'd20; i<=8'd29; i=i+1)
1742 
          read_register(i);
1743 
        if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun)
1744 
          $display("\nWARNING: Above packet was received with overrun.");
1745 
      end
1746 
  end
1747 
endtask
1748 
 
1749 
 
1750 
task release_rx_buffer_command;
1751 
  begin
1752 
    write_register(8'd1, 8'h4);
1753 
    $display("(%0t) Rx buffer released.", $time);
1754 
  end
1755 
endtask
1756 
 
1757 
 
1758 
task tx_request_command;
1759 
  begin
1760 
    write_register(8'd1, 8'h1);
1761 
    $display("(%0t) Tx requested.", $time);
1762 
  end
1763 
endtask
1764 
 
1765 
 
1766 
task tx_abort_command;
1767 
  begin
1768 
    write_register(8'd1, 8'h2);
1769 
    $display("(%0t) Tx abort requested.", $time);
1770 
  end
1771 
endtask
1772 
 
1773 
 
1774 
task clear_data_overrun_command;
1775 
  begin
1776 
    write_register(8'd1, 8'h8);
1777 
    $display("(%0t) Data overrun cleared.", $time);
1778 
  end
1779 
endtask
1780 
 
1781 
 
1782 
task self_reception_request_command;
1783 
  begin
1784 
    write_register(8'd1, 8'h10);
1785 
    $display("(%0t) Self reception requested.", $time);
1786 
  end
1787 
endtask
1788 
 
1789 
 
1790 
task test_synchronization;
1791 
  begin
1792 
    // Hard synchronization
1793 
    #1 rx=0;
1794 
    repeat (2*BRP) @ (posedge clk);
1795 
    repeat (8*BRP) @ (posedge clk);
1796 
    #1 rx=1;
1797 
    repeat (10*BRP) @ (posedge clk);
1798 
 
1799 
    // Resynchronization on time
1800 
    #1 rx=0;
1801 
    repeat (10*BRP) @ (posedge clk);
1802 
    #1 rx=1;
1803 
    repeat (10*BRP) @ (posedge clk);
1804 
 
1805 
    // Resynchronization late
1806 
    repeat (BRP) @ (posedge clk);
1807 
    repeat (BRP) @ (posedge clk);
1808 
    #1 rx=0;
1809 
    repeat (10*BRP) @ (posedge clk);
1810 
    #1 rx=1;
1811 
 
1812 
    // Resynchronization early
1813 
    repeat (8*BRP) @ (posedge clk);   // two frames too early
1814 
    #1 rx=0;
1815 
    repeat (10*BRP) @ (posedge clk);
1816 
    #1 rx=1;
1817 
    repeat (10*BRP) @ (posedge clk);
1818 
  end
1819 
endtask
1820 
 
1821 
 
1822 
task send_bit;
1823 
  input bit;
1824 
  integer cnt;
1825 
  begin
1826 
    #1 rx=bit;
1827 
    repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
1828 
  end
1829 
endtask
1830 
 
1831 
 
1832 
task receive_frame;           // CAN IP core receives frames
1833 
  input mode;
1834 
  input remote_trans_req;
1835 
  input [28:0] id;
1836 
  input  [3:0] length;
1837 
  input [14:0] crc;
1838 
 
1839 
  reg [117:0] data;
1840 
  reg         previous_bit;
1841 
  reg         stuff;
1842 
  reg         tmp;
1843 
  reg         arbitration_lost;
1844 
  integer     pointer;
1845 
  integer     cnt;
1846 
  integer     total_bits;
1847 
  integer     stuff_cnt;
1848 
 
1849 
  begin
1850 
 
1851 
    stuff_cnt = 1;
1852 
    stuff = 0;
1853 
 
1854 
    if(mode)          // Extended format
1855 
      data = {id[28:18], 1'b1, 1'b1, id[17:0], remote_trans_req, 2'h0, length};
1856 
    else              // Standard format
1857 
      data = {id[10:0], remote_trans_req, 1'b0, 1'b0, length};
1858 
 
1859 
    if (~remote_trans_req)
1860 
      begin
1861 
        if(length)    // Send data if length is > 0
1862 
          begin
1863 
            for (cnt=1; cnt<=(2*length); cnt=cnt+1)  // data   (we are sending nibbles)
1864 
              data = {data[113:0], cnt[3:0]};
1865 
          end
1866 
      end
1867 
 
1868 
    // Adding CRC
1869 
    data = {data[104:0], crc[14:0]};
1870 
 
1871 
 
1872 
    // Calculating pointer that points to the bit that will be send
1873 
    if (remote_trans_req)
1874 
      begin
1875 
        if(mode)          // Extended format
1876 
          pointer = 52;
1877 
        else              // Standard format
1878 
          pointer = 32;
1879 
      end
1880 
    else
1881 
      begin
1882 
        if(mode)          // Extended format
1883 
          pointer = 52 + 8 * length;
1884 
        else              // Standard format
1885 
          pointer = 32 + 8 * length;
1886 
      end
1887 
 
1888 
    // This is how many bits we need to shift
1889 
    total_bits = pointer;
1890 
 
1891 
    // Waiting until previous msg is finished before sending another one
1892 
    if (arbitration_lost)           //  Arbitration lost. Another node is transmitting. We have to wait until it is finished.
1893 
      wait ( (~can_testbench.i_can_top.i_can_bsp.error_frame) &
1894 
             (~can_testbench.i_can_top.i_can_bsp.rx_inter   ) &
1895 
             (~can_testbench.i_can_top.i_can_bsp.tx_state   )
1896 
           );
1897 
    else                            // We were transmitter of the previous frame. No need to wait for another node to finish transmission.
1898 
      wait ( (~can_testbench.i_can_top.i_can_bsp.error_frame) &
1899 
             (~can_testbench.i_can_top.i_can_bsp.rx_inter   )
1900 
           );
1901 
    arbitration_lost = 0;
1902 
 
1903 
    send_bit(0);                        // SOF
1904 
    previous_bit = 0;
1905 
 
1906 
    fork
1907 
 
1908 
    begin
1909 
      for (cnt=0; cnt<=total_bits; cnt=cnt+1)
1910 
        begin
1911 
          if (stuff_cnt == 5)
1912 
            begin
1913 
              stuff_cnt = 1;
1914 
              total_bits = total_bits + 1;
1915 
              stuff = 1;
1916 
              tmp = ~data[pointer+1];
1917 
              send_bit(~data[pointer+1]);
1918 
              previous_bit = ~data[pointer+1];
1919 
            end
1920 
          else
1921 
            begin
1922 
              if (data[pointer] == previous_bit)
1923 
                stuff_cnt <= stuff_cnt + 1;
1924 
              else
1925 
                stuff_cnt <= 1;
1926 
 
1927 
              stuff = 0;
1928 
              tmp = data[pointer];
1929 
              send_bit(data[pointer]);
1930 
              previous_bit = data[pointer];
1931 
              pointer = pointer - 1;
1932 
            end
1933 
          if (arbitration_lost)
1934 
            cnt=total_bits+1;         // Exit the for loop
1935 
        end
1936 
 
1937 
        // Nothing send after the data (just recessive bit)
1938 
        repeat (13) send_bit(1);         // CRC delimiter + ack + ack delimiter + EOF + intermission= 1 + 1 + 1 + 7 + 3
1939 
    end
1940 
 
1941 
    begin
1942 
      while (mode ? (cnt<32) : (cnt<12))
1943 
        begin
1944 
          #1 wait (can_testbench.i_can_top.sample_point);
1945 
          if (mode)
1946 
            begin
1947 
              if (cnt<32 & tmp & (~rx_and_tx))
1948 
                begin
1949 
                  arbitration_lost = 1;
1950 
                  rx = 1;       // Only recessive is send from now on.
1951 
                end
1952 
            end
1953 
          else
1954 
            begin
1955 
              if (cnt<12 & tmp & (~rx_and_tx))
1956 
                begin
1957 
                  arbitration_lost = 1;
1958 
                  rx = 1;       // Only recessive is send from now on.
1959 
                end
1960 
            end
1961 
        end
1962 
    end
1963 
 
1964 
    join
1965 
 
1966 
  end
1967 
endtask
1968 
 
1969 
 
1970 
 
1971 
// State machine monitor (btl)
1972 
always @ (posedge clk)
1973 
begin
1974 
  if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
1975 
     can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
1976 
    begin
1977 
      $display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);
1978 
      #1000;
1979 
      $stop;
1980 
    end
1981 
 
1982 
  if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
1983 
     can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
1984 
    begin
1985 
      $display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);
1986 
      #1000;
1987 
      $stop;
1988 
    end
1989 
end
1990 
 
1991 
/* stuff_error monitor (bsp)
1992 
always @ (posedge clk)
1993 
begin
1994 
  if(can_testbench.i_can_top.i_can_bsp.stuff_error)
1995 
    begin
1996 
      $display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);
1997 
      $stop;                                      After everything is finished add another condition (something like & (~idle)) and enable stop
1998 
    end
1999 
end
2000 
*/
2001 
 
2002 
//
2003 
// CRC monitor (used until proper CRC generation is used in testbench
2004 
always @ (posedge clk)
2005 
begin
2006 
  if (can_testbench.i_can_top.i_can_bsp.rx_ack       &
2007 
      can_testbench.i_can_top.i_can_bsp.sample_point &
2008 
      can_testbench.i_can_top.i_can_bsp.crc_err
2009 
     )
2010 
    $display("*E (%0t) ERROR: CRC error (Calculated crc = 0x%0x, crc_in = 0x%0x)", $time, can_testbench.i_can_top.i_can_bsp.calculated_crc, can_testbench.i_can_top.i_can_bsp.crc_in);
2011 
end
2012 
 
2013 
 
2014 
 
2015 
 
2016 
 
2017 
/*
2018 
// overrun monitor
2019 
always @ (posedge clk)
2020 
begin
2021 
  if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr & can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_full)
2022 
    $display("(%0t)overrun", $time);
2023 
end
2024 
*/
2025 
 
2026 
 
2027 
// form error monitor
2028 
always @ (posedge clk)
2029 
begin
2030 
  if (can_testbench.i_can_top.i_can_bsp.form_err)
2031 
    $display("*E (%0t) ERROR: form_error", $time);
2032 
end
2033 
 
2034 
 
2035 
 
2036 
// acknowledge error monitor
2037 
always @ (posedge clk)
2038 
begin
2039 
  if (can_testbench.i_can_top.i_can_bsp.ack_err)
2040 
    $display("*E (%0t) ERROR: acknowledge_error", $time);
2041 
end
2042 
 
2043 
/*
2044 
// bit error monitor
2045 
always @ (posedge clk)
2046 
begin
2047 
  if (can_testbench.i_can_top.i_can_bsp.bit_err)
2048 
    $display("*E (%0t) ERROR: bit_error", $time);
2049 
end
2050 
*/
2051 
 
2052 
endmodule
2053 
 

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