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mohor |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// can_testbench.v ////
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//// ////
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//// ////
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//// This file is part of the CAN Protocol Controller ////
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//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002, 2003 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// The CAN protocol is developed by Robert Bosch GmbH and ////
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//// protected by patents. Anybody who wants to implement this ////
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//// CAN IP core on silicon has to obtain a CAN protocol license ////
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//// from Bosch. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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160 |
igorm |
// Revision 1.41 2005/07/11 10:25:13 igorm
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// Fixing overrun problems.
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//
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158 |
igorm |
// Revision 1.40 2004/03/18 17:39:17 igorm
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// I forgot to thange one signal name.
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//
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140 |
igorm |
// Revision 1.39 2004/03/18 17:15:26 igorm
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// Signal bus_off_on added.
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//
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igorm |
// Revision 1.38 2003/10/17 05:55:18 markom
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// mbist signals updated according to newest convention
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//
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130 |
markom |
// Revision 1.37 2003/09/30 20:53:58 mohor
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// Fixing the core to be Bosch VHDL Reference compatible.
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//
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mohor |
// Revision 1.36 2003/08/20 10:03:20 mohor
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// Artisan RAMs added.
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//
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mohor |
// Revision 1.35 2003/06/17 15:14:48 mohor
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// cs_can_i is used only when WISHBONE interface is not used.
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//
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mohor |
// Revision 1.34 2003/03/26 11:25:39 mohor
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// CAN inturrupt is active low.
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//
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// Revision 1.33 2003/03/14 19:37:30 mohor
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// ALE changes on negedge of clk.
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//
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// Revision 1.32 2003/03/12 05:57:36 mohor
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// Bidirectional port_0_i changed to port_0_io.
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// input cs_can changed to cs_can_i.
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//
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// Revision 1.31 2003/03/12 04:40:00 mohor
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// rd_i and wr_i are active high signals. If 8051 is connected, these two signals
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// need to be negated one level higher.
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//
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// Revision 1.30 2003/03/12 04:16:40 mohor
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// 8051 interface added (besides WISHBONE interface). Selection is made in
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// can_defines.v file.
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//
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// Revision 1.29 2003/03/05 15:33:37 mohor
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// tx_o is now tristated signal. tx_oen and tx_o combined together.
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//
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// Revision 1.28 2003/03/05 15:00:49 mohor
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// Top level signal names changed.
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//
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// Revision 1.27 2003/03/01 22:48:26 mohor
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// Actel APA ram supported.
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//
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// Revision 1.26 2003/02/19 14:43:17 mohor
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// CAN core finished. Host interface added. Registers finished.
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// Synchronization to the wishbone finished.
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//
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// Revision 1.25 2003/02/18 00:19:39 mohor
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// Temporary backup version (still fully operable).
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//
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// Revision 1.24 2003/02/14 20:16:53 mohor
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// Several registers added. Not finished, yet.
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//
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// Revision 1.23 2003/02/12 14:28:30 mohor
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// Errors monitoring improved. arbitration_lost improved.
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//
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// Revision 1.22 2003/02/11 00:57:19 mohor
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// Wishbone interface added.
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//
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// Revision 1.21 2003/02/09 18:40:23 mohor
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// Overload fixed. Hard synchronization also enabled at the last bit of
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// interframe.
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//
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// Revision 1.20 2003/02/09 02:24:11 mohor
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// Bosch license warning added. Error counters finished. Overload frames
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// still need to be fixed.
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//
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// Revision 1.19 2003/02/04 17:24:33 mohor
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// Backup.
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//
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// Revision 1.18 2003/02/04 14:34:45 mohor
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// *** empty log message ***
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//
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// Revision 1.17 2003/01/31 01:13:31 mohor
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// backup.
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//
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// Revision 1.16 2003/01/16 13:36:14 mohor
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// Form error supported. When receiving messages, last bit of the end-of-frame
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// does not generate form error. Receiver goes to the idle mode one bit sooner.
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// (CAN specification ver 2.0, part B, page 57).
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//
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// Revision 1.15 2003/01/15 21:05:06 mohor
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// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
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//
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// Revision 1.14 2003/01/15 14:40:16 mohor
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// RX state machine fixed to receive "remote request" frames correctly. No
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// data bytes are written to fifo when such frames are received.
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//
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// Revision 1.13 2003/01/15 13:16:42 mohor
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// When a frame with "remote request" is received, no data is stored to
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// fifo, just the frame information (identifier, ...). Data length that
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// is stored is the received data length and not the actual data length
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// that is stored to fifo.
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//
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// Revision 1.12 2003/01/14 17:25:03 mohor
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// Addresses corrected to decimal values (previously hex).
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//
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// Revision 1.11 2003/01/14 12:19:29 mohor
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// rx_fifo is now working.
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//
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// Revision 1.10 2003/01/10 17:51:28 mohor
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// Temporary version (backup).
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//
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// Revision 1.9 2003/01/09 21:54:39 mohor
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// rx fifo added. Not 100 % verified, yet.
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//
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// Revision 1.8 2003/01/08 02:09:43 mohor
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// Acceptance filter added.
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//
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// Revision 1.7 2002/12/28 04:13:53 mohor
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// Backup version.
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//
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// Revision 1.6 2002/12/27 00:12:48 mohor
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// Header changed, testbench improved to send a frame (crc still missing).
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//
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// Revision 1.5 2002/12/26 16:00:29 mohor
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// Testbench define file added. Clock divider register added.
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//
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// Revision 1.4 2002/12/26 01:33:01 mohor
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// Tripple sampling supported.
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//
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// Revision 1.3 2002/12/25 23:44:12 mohor
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// Commented lines removed.
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//
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// Revision 1.2 2002/12/25 14:16:54 mohor
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// Synchronization working.
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//
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// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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// Initial
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "can_defines.v"
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`include "can_testbench_defines.v"
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module can_testbench();
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parameter Tp = 1;
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parameter BRP = 2*(`CAN_TIMING0_BRP + 1);
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`ifdef CAN_WISHBONE_IF
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reg wb_clk_i;
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reg wb_rst_i;
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reg [7:0] wb_dat_i;
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wire [7:0] wb_dat_o;
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reg wb_cyc_i;
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reg wb_stb_i;
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reg wb_we_i;
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reg [7:0] wb_adr_i;
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wire wb_ack_o;
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reg wb_free;
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`else
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reg rst_i;
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reg ale_i;
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reg rd_i;
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reg wr_i;
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158 |
igorm |
reg ale2_i;
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reg rd2_i;
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reg wr2_i;
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83 |
mohor |
wire [7:0] port_0;
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wire [7:0] port_0_i;
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reg [7:0] port_0_o;
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reg port_0_en;
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reg port_free;
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`endif
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reg cs_can;
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158 |
igorm |
reg cs_can2;
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83 |
mohor |
reg clk;
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reg rx;
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wire tx;
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119 |
mohor |
wire tx_i;
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139 |
igorm |
wire bus_off_on;
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83 |
mohor |
wire irq;
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wire clkout;
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wire rx_and_tx;
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integer start_tb;
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reg [7:0] tmp_data;
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reg delayed_tx;
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reg tx_bypassed;
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reg extended_mode;
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160 |
igorm |
event igor;
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83 |
mohor |
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// Instantiate can_top module
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can_top i_can_top
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(
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`ifdef CAN_WISHBONE_IF
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.wb_clk_i(wb_clk_i),
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.wb_rst_i(wb_rst_i),
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.wb_dat_i(wb_dat_i),
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.wb_dat_o(wb_dat_o),
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.wb_cyc_i(wb_cyc_i),
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.wb_stb_i(wb_stb_i),
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.wb_we_i(wb_we_i),
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.wb_adr_i(wb_adr_i),
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.wb_ack_o(wb_ack_o),
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`else
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.cs_can_i(cs_can),
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.rst_i(rst_i),
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.ale_i(ale_i),
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.rd_i(rd_i),
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.wr_i(wr_i),
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.port_0_io(port_0),
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`endif
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.clk_i(clk),
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.rx_i(rx_and_tx),
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| 275 |
119 |
mohor |
.tx_o(tx_i),
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| 276 |
139 |
igorm |
.bus_off_on(bus_off_on),
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| 277 |
83 |
mohor |
.irq_on(irq),
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.clkout_o(clkout)
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| 279 |
119 |
mohor |
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// Bist
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`ifdef CAN_BIST
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,
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// debug chain signals
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| 284 |
130 |
markom |
.mbist_si_i(1'b0), // bist scan serial in
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.mbist_so_o(), // bist scan serial out
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| 286 |
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.mbist_ctrl_i(3'b001) // mbist scan {enable, clock, reset}
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| 287 |
119 |
mohor |
`endif
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| 288 |
83 |
mohor |
);
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| 289 |
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| 290 |
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| 291 |
158 |
igorm |
// Instantiate can_top module 2
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can_top i_can_top2
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(
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| 294 |
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`ifdef CAN_WISHBONE_IF
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| 295 |
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.wb_clk_i(wb_clk_i),
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| 296 |
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.wb_rst_i(wb_rst_i),
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| 297 |
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.wb_dat_i(wb_dat_i),
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| 298 |
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.wb_dat_o(wb_dat_o),
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| 299 |
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.wb_cyc_i(wb_cyc_i),
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| 300 |
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.wb_stb_i(wb_stb_i),
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| 301 |
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.wb_we_i(wb_we_i),
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.wb_adr_i(wb_adr_i),
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.wb_ack_o(wb_ack_o),
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`else
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.cs_can_i(cs_can2),
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.rst_i(rst_i),
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.ale_i(ale2_i),
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.rd_i(rd2_i),
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.wr_i(wr2_i),
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.port_0_io(port_0),
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`endif
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.clk_i(clk),
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.rx_i(rx_and_tx),
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.tx_o(tx2_i),
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.bus_off_on(bus_off2_on),
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.irq_on(),
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.clkout_o(clkout)
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// Bist
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| 320 |
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`ifdef CAN_BIST
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,
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| 322 |
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// debug chain signals
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| 323 |
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.mbist_si_i(1'b0), // bist scan serial in
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.mbist_so_o(), // bist scan serial out
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| 325 |
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.mbist_ctrl_i(3'b001) // mbist scan {enable, clock, reset}
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`endif
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| 327 |
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);
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| 328 |
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|
| 329 |
|
|
|
| 330 |
119 |
mohor |
// Combining tx with the output enable signal.
|
| 331 |
158 |
igorm |
wire tx_tmp1;
|
| 332 |
|
|
wire tx_tmp2;
|
| 333 |
119 |
mohor |
|
| 334 |
160 |
igorm |
assign tx_tmp1 = bus_off_on? tx_i : 1'b1;
|
| 335 |
|
|
assign tx_tmp2 = bus_off2_on? tx2_i : 1'b1;
|
| 336 |
158 |
igorm |
|
| 337 |
|
|
assign tx = tx_tmp1 & tx_tmp2;
|
| 338 |
|
|
|
| 339 |
|
|
|
| 340 |
160 |
igorm |
|
| 341 |
83 |
mohor |
`ifdef CAN_WISHBONE_IF
|
| 342 |
|
|
// Generate wishbone clock signal 10 MHz
|
| 343 |
|
|
initial
|
| 344 |
|
|
begin
|
| 345 |
|
|
wb_clk_i=0;
|
| 346 |
|
|
forever #50 wb_clk_i = ~wb_clk_i;
|
| 347 |
|
|
end
|
| 348 |
|
|
`endif
|
| 349 |
|
|
|
| 350 |
|
|
|
| 351 |
|
|
`ifdef CAN_WISHBONE_IF
|
| 352 |
|
|
`else
|
| 353 |
|
|
assign port_0_i = port_0;
|
| 354 |
|
|
assign port_0 = port_0_en? port_0_o : 8'hz;
|
| 355 |
|
|
`endif
|
| 356 |
|
|
|
| 357 |
|
|
|
| 358 |
127 |
mohor |
// Generate clock signal 25 MHz
|
| 359 |
160 |
igorm |
// Generate clock signal 16 MHz
|
| 360 |
83 |
mohor |
initial
|
| 361 |
|
|
begin
|
| 362 |
|
|
clk=0;
|
| 363 |
160 |
igorm |
//forever #20 clk = ~clk;
|
| 364 |
|
|
forever #31.25 clk = ~clk;
|
| 365 |
83 |
mohor |
end
|
| 366 |
|
|
|
| 367 |
|
|
|
| 368 |
|
|
initial
|
| 369 |
|
|
begin
|
| 370 |
|
|
start_tb = 0;
|
| 371 |
|
|
cs_can = 0;
|
| 372 |
158 |
igorm |
cs_can2 = 0;
|
| 373 |
83 |
mohor |
rx = 1;
|
| 374 |
|
|
extended_mode = 0;
|
| 375 |
|
|
tx_bypassed = 0;
|
| 376 |
|
|
|
| 377 |
|
|
`ifdef CAN_WISHBONE_IF
|
| 378 |
|
|
wb_dat_i = 'hz;
|
| 379 |
|
|
wb_cyc_i = 0;
|
| 380 |
|
|
wb_stb_i = 0;
|
| 381 |
|
|
wb_we_i = 'hz;
|
| 382 |
|
|
wb_adr_i = 'hz;
|
| 383 |
|
|
wb_free = 1;
|
| 384 |
|
|
wb_rst_i = 1;
|
| 385 |
|
|
#200 wb_rst_i = 0;
|
| 386 |
|
|
#200 start_tb = 1;
|
| 387 |
|
|
`else
|
| 388 |
|
|
rst_i = 1'b0;
|
| 389 |
|
|
ale_i = 1'b0;
|
| 390 |
|
|
rd_i = 1'b0;
|
| 391 |
|
|
wr_i = 1'b0;
|
| 392 |
158 |
igorm |
ale2_i = 1'b0;
|
| 393 |
|
|
rd2_i = 1'b0;
|
| 394 |
|
|
wr2_i = 1'b0;
|
| 395 |
83 |
mohor |
port_0_o = 8'h0;
|
| 396 |
|
|
port_0_en = 0;
|
| 397 |
|
|
port_free = 1;
|
| 398 |
|
|
rst_i = 1;
|
| 399 |
|
|
#200 rst_i = 0;
|
| 400 |
|
|
#200 start_tb = 1;
|
| 401 |
|
|
`endif
|
| 402 |
|
|
end
|
| 403 |
|
|
|
| 404 |
|
|
|
| 405 |
|
|
|
| 406 |
|
|
|
| 407 |
|
|
// Generating delayed tx signal (CAN transciever delay)
|
| 408 |
|
|
always
|
| 409 |
|
|
begin
|
| 410 |
|
|
wait (tx);
|
| 411 |
158 |
igorm |
repeat (2*BRP) @ (posedge clk); // 4 time quants delay
|
| 412 |
83 |
mohor |
#1 delayed_tx = tx;
|
| 413 |
|
|
wait (~tx);
|
| 414 |
158 |
igorm |
repeat (2*BRP) @ (posedge clk); // 4 time quants delay
|
| 415 |
83 |
mohor |
#1 delayed_tx = tx;
|
| 416 |
|
|
end
|
| 417 |
|
|
|
| 418 |
|
|
//assign rx_and_tx = rx & delayed_tx; FIX ME !!!
|
| 419 |
|
|
assign rx_and_tx = rx & (delayed_tx | tx_bypassed); // When this signal is on, tx is not looped back to the rx.
|
| 420 |
|
|
|
| 421 |
|
|
|
| 422 |
|
|
// Main testbench
|
| 423 |
|
|
initial
|
| 424 |
|
|
begin
|
| 425 |
|
|
wait(start_tb);
|
| 426 |
|
|
|
| 427 |
|
|
// Set bus timing register 0
|
| 428 |
|
|
write_register(8'd6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
|
| 429 |
158 |
igorm |
write_register2(8'd6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
|
| 430 |
83 |
mohor |
|
| 431 |
|
|
// Set bus timing register 1
|
| 432 |
|
|
write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
|
| 433 |
158 |
igorm |
write_register2(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
|
| 434 |
83 |
mohor |
|
| 435 |
|
|
|
| 436 |
|
|
// Set Clock Divider register
|
| 437 |
158 |
igorm |
// extended_mode = 1'b1;
|
| 438 |
|
|
// write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended)
|
| 439 |
|
|
write_register2(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended)
|
| 440 |
83 |
mohor |
|
| 441 |
|
|
|
| 442 |
|
|
// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
|
| 443 |
158 |
igorm |
|
| 444 |
|
|
/* Set Acceptance Code and Acceptance Mask registers
|
| 445 |
83 |
mohor |
write_register(8'd16, 8'ha6); // acceptance code 0
|
| 446 |
|
|
write_register(8'd17, 8'hb0); // acceptance code 1
|
| 447 |
|
|
write_register(8'd18, 8'h12); // acceptance code 2
|
| 448 |
|
|
write_register(8'd19, 8'h30); // acceptance code 3
|
| 449 |
158 |
igorm |
write_register(8'd20, 8'hff); // acceptance mask 0
|
| 450 |
|
|
write_register(8'd21, 8'hff); // acceptance mask 1
|
| 451 |
|
|
write_register(8'd22, 8'hff); // acceptance mask 2
|
| 452 |
|
|
write_register(8'd23, 8'hff); // acceptance mask 3
|
| 453 |
|
|
|
| 454 |
|
|
write_register2(8'd16, 8'ha6); // acceptance code 0
|
| 455 |
|
|
write_register2(8'd17, 8'hb0); // acceptance code 1
|
| 456 |
|
|
write_register2(8'd18, 8'h12); // acceptance code 2
|
| 457 |
|
|
write_register2(8'd19, 8'h30); // acceptance code 3
|
| 458 |
|
|
write_register2(8'd20, 8'hff); // acceptance mask 0
|
| 459 |
|
|
write_register2(8'd21, 8'hff); // acceptance mask 1
|
| 460 |
|
|
write_register2(8'd22, 8'hff); // acceptance mask 2
|
| 461 |
|
|
write_register2(8'd23, 8'hff); // acceptance mask 3
|
| 462 |
83 |
mohor |
*/
|
| 463 |
|
|
|
| 464 |
|
|
// Set Acceptance Code and Acceptance Mask registers
|
| 465 |
|
|
write_register(8'd4, 8'he8); // acceptance code
|
| 466 |
|
|
write_register(8'd5, 8'h0f); // acceptance mask
|
| 467 |
|
|
|
| 468 |
|
|
#10;
|
| 469 |
|
|
repeat (1000) @ (posedge clk);
|
| 470 |
|
|
|
| 471 |
|
|
// Switch-off reset mode
|
| 472 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 473 |
158 |
igorm |
write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 474 |
83 |
mohor |
|
| 475 |
|
|
repeat (BRP) @ (posedge clk); // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
|
| 476 |
|
|
// This difference is resynchronized later.
|
| 477 |
|
|
|
| 478 |
|
|
// After exiting the reset mode sending bus free
|
| 479 |
|
|
repeat (11) send_bit(1);
|
| 480 |
|
|
|
| 481 |
158 |
igorm |
// test_synchronization; // test currently switched off
|
| 482 |
83 |
mohor |
// test_empty_fifo_ext; // test currently switched off
|
| 483 |
|
|
// test_full_fifo_ext; // test currently switched off
|
| 484 |
|
|
// send_frame_ext; // test currently switched off
|
| 485 |
|
|
// test_empty_fifo; // test currently switched off
|
| 486 |
160 |
igorm |
// test_full_fifo; // test currently switched off
|
| 487 |
158 |
igorm |
// test_reset_mode; // test currently switched off
|
| 488 |
83 |
mohor |
// bus_off_test; // test currently switched off
|
| 489 |
|
|
// forced_bus_off; // test currently switched off
|
| 490 |
158 |
igorm |
// send_frame_basic; // test currently switched on
|
| 491 |
83 |
mohor |
// send_frame_extended; // test currently switched off
|
| 492 |
|
|
// self_reception_request; // test currently switched off
|
| 493 |
|
|
// manual_frame_basic; // test currently switched off
|
| 494 |
|
|
// manual_frame_ext; // test currently switched off
|
| 495 |
160 |
igorm |
// error_test;
|
| 496 |
|
|
// register_test;
|
| 497 |
|
|
bus_off_recovery_test;
|
| 498 |
83 |
mohor |
|
| 499 |
160 |
igorm |
|
| 500 |
|
|
/*
|
| 501 |
|
|
#5000;
|
| 502 |
|
|
$display("\n\nStart rx/tx err cnt\n");
|
| 503 |
|
|
-> igor;
|
| 504 |
|
|
|
| 505 |
|
|
// Switch-off reset mode
|
| 506 |
|
|
$display("Rest mode ON");
|
| 507 |
|
|
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 508 |
|
|
|
| 509 |
|
|
$display("Set extended mode");
|
| 510 |
|
|
extended_mode = 1'b1;
|
| 511 |
|
|
write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the extended mode
|
| 512 |
|
|
|
| 513 |
|
|
$display("Rest mode OFF");
|
| 514 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 515 |
|
|
|
| 516 |
|
|
write_register(8'd14, 8'hde); // rx err cnt
|
| 517 |
|
|
write_register(8'd15, 8'had); // tx err cnt
|
| 518 |
|
|
|
| 519 |
|
|
read_register(8'd14, tmp_data); // rx err cnt
|
| 520 |
|
|
read_register(8'd15, tmp_data); // tx err cnt
|
| 521 |
|
|
|
| 522 |
|
|
// Switch-on reset mode
|
| 523 |
|
|
$display("Switch-on reset mode");
|
| 524 |
|
|
write_register(8'd0, {7'h0, `CAN_MODE_RESET});
|
| 525 |
|
|
|
| 526 |
|
|
write_register(8'd14, 8'h12); // rx err cnt
|
| 527 |
|
|
write_register(8'd15, 8'h34); // tx err cnt
|
| 528 |
|
|
|
| 529 |
|
|
read_register(8'd14, tmp_data); // rx err cnt
|
| 530 |
|
|
read_register(8'd15, tmp_data); // tx err cnt
|
| 531 |
|
|
|
| 532 |
|
|
// Switch-off reset mode
|
| 533 |
|
|
$display("Switch-off reset mode");
|
| 534 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 535 |
|
|
|
| 536 |
|
|
read_register(8'd14, tmp_data); // rx err cnt
|
| 537 |
|
|
read_register(8'd15, tmp_data); // tx err cnt
|
| 538 |
|
|
|
| 539 |
|
|
// Switch-on reset mode
|
| 540 |
|
|
$display("Switch-on reset mode");
|
| 541 |
|
|
write_register(8'd0, {7'h0, `CAN_MODE_RESET});
|
| 542 |
|
|
|
| 543 |
|
|
write_register(8'd14, 8'h56); // rx err cnt
|
| 544 |
|
|
write_register(8'd15, 8'h78); // tx err cnt
|
| 545 |
|
|
|
| 546 |
|
|
// Switch-off reset mode
|
| 547 |
|
|
$display("Switch-off reset mode");
|
| 548 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 549 |
|
|
|
| 550 |
|
|
read_register(8'd14, tmp_data); // rx err cnt
|
| 551 |
|
|
read_register(8'd15, tmp_data); // tx err cnt
|
| 552 |
|
|
*/
|
| 553 |
|
|
#1000;
|
| 554 |
83 |
mohor |
$display("CAN Testbench finished !");
|
| 555 |
|
|
$stop;
|
| 556 |
|
|
end
|
| 557 |
|
|
|
| 558 |
|
|
|
| 559 |
160 |
igorm |
task bus_off_recovery_test;
|
| 560 |
|
|
begin
|
| 561 |
|
|
-> igor;
|
| 562 |
|
|
|
| 563 |
|
|
// Switch-on reset mode
|
| 564 |
|
|
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 565 |
|
|
write_register2(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 566 |
|
|
|
| 567 |
|
|
// Set Clock Divider register
|
| 568 |
|
|
extended_mode = 1'b1;
|
| 569 |
|
|
write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended)
|
| 570 |
|
|
write_register2(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended)
|
| 571 |
|
|
|
| 572 |
|
|
write_register(8'd16, 8'h00); // acceptance code 0
|
| 573 |
|
|
write_register(8'd17, 8'h00); // acceptance code 1
|
| 574 |
|
|
write_register(8'd18, 8'h00); // acceptance code 2
|
| 575 |
|
|
write_register(8'd19, 8'h00); // acceptance code 3
|
| 576 |
|
|
write_register(8'd20, 8'hff); // acceptance mask 0
|
| 577 |
|
|
write_register(8'd21, 8'hff); // acceptance mask 1
|
| 578 |
|
|
write_register(8'd22, 8'hff); // acceptance mask 2
|
| 579 |
|
|
write_register(8'd23, 8'hff); // acceptance mask 3
|
| 580 |
|
|
|
| 581 |
|
|
write_register2(8'd16, 8'h00); // acceptance code 0
|
| 582 |
|
|
write_register2(8'd17, 8'h00); // acceptance code 1
|
| 583 |
|
|
write_register2(8'd18, 8'h00); // acceptance code 2
|
| 584 |
|
|
write_register2(8'd19, 8'h00); // acceptance code 3
|
| 585 |
|
|
write_register2(8'd20, 8'hff); // acceptance mask 0
|
| 586 |
|
|
write_register2(8'd21, 8'hff); // acceptance mask 1
|
| 587 |
|
|
write_register2(8'd22, 8'hff); // acceptance mask 2
|
| 588 |
|
|
write_register2(8'd23, 8'hff); // acceptance mask 3
|
| 589 |
|
|
|
| 590 |
|
|
// Switch-off reset mode
|
| 591 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 592 |
|
|
write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 593 |
|
|
|
| 594 |
|
|
// Enable all interrupts
|
| 595 |
|
|
write_register(8'd4, 8'hff); // irq enable register
|
| 596 |
|
|
|
| 597 |
|
|
repeat (30) send_bit(1);
|
| 598 |
|
|
-> igor;
|
| 599 |
|
|
$display("(%0t) CAN should be idle now", $time);
|
| 600 |
|
|
|
| 601 |
|
|
// Node 2 sends a message
|
| 602 |
|
|
write_register2(8'd16, 8'h83); // tx registers
|
| 603 |
|
|
write_register2(8'd17, 8'h12); // tx registers
|
| 604 |
|
|
write_register2(8'd18, 8'h34); // tx registers
|
| 605 |
|
|
write_register2(8'd19, 8'h45); // tx registers
|
| 606 |
|
|
write_register2(8'd20, 8'h56); // tx registers
|
| 607 |
|
|
write_register2(8'd21, 8'hde); // tx registers
|
| 608 |
|
|
write_register2(8'd22, 8'had); // tx registers
|
| 609 |
|
|
write_register2(8'd23, 8'hbe); // tx registers
|
| 610 |
|
|
|
| 611 |
|
|
write_register2(8'd1, 8'h1); // tx request
|
| 612 |
|
|
|
| 613 |
|
|
// Wait until node 1 receives rx irq
|
| 614 |
|
|
read_register(8'd3, tmp_data);
|
| 615 |
|
|
while (!(tmp_data & 8'h01)) begin
|
| 616 |
|
|
read_register(8'd3, tmp_data);
|
| 617 |
|
|
end
|
| 618 |
|
|
|
| 619 |
|
|
$display("Frame received by node 1.");
|
| 620 |
|
|
|
| 621 |
|
|
// Node 1 will send a message and will receive many errors
|
| 622 |
|
|
write_register(8'd16, 8'haa); // tx registers
|
| 623 |
|
|
write_register(8'd17, 8'haa); // tx registers
|
| 624 |
|
|
write_register(8'd18, 8'haa); // tx registers
|
| 625 |
|
|
write_register(8'd19, 8'haa); // tx registers
|
| 626 |
|
|
write_register(8'd20, 8'haa); // tx registers
|
| 627 |
|
|
write_register(8'd21, 8'haa); // tx registers
|
| 628 |
|
|
write_register(8'd22, 8'haa); // tx registers
|
| 629 |
|
|
write_register(8'd23, 8'haa); // tx registers
|
| 630 |
|
|
|
| 631 |
|
|
fork
|
| 632 |
|
|
begin
|
| 633 |
|
|
write_register(8'd1, 8'h1); // tx request
|
| 634 |
|
|
end
|
| 635 |
|
|
|
| 636 |
|
|
begin
|
| 637 |
|
|
// Waiting until node 1 starts transmitting
|
| 638 |
|
|
wait (!tx_i);
|
| 639 |
|
|
repeat (33) send_bit(1);
|
| 640 |
|
|
repeat (330) send_bit(0);
|
| 641 |
|
|
repeat (1) send_bit(1);
|
| 642 |
|
|
end
|
| 643 |
|
|
|
| 644 |
|
|
join
|
| 645 |
|
|
|
| 646 |
|
|
// Switch-off reset mode
|
| 647 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 648 |
|
|
write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 649 |
|
|
|
| 650 |
|
|
repeat (1999) send_bit(1);
|
| 651 |
|
|
|
| 652 |
|
|
// Switch-on reset mode
|
| 653 |
|
|
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 654 |
|
|
write_register2(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 655 |
|
|
|
| 656 |
|
|
write_register(8'd14, 8'h0); // rx err cnt
|
| 657 |
|
|
|
| 658 |
|
|
// Switch-off reset mode
|
| 659 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 660 |
|
|
write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 661 |
|
|
|
| 662 |
|
|
|
| 663 |
|
|
// Wait some time before simulation ends
|
| 664 |
|
|
repeat (10000) @ (posedge clk);
|
| 665 |
|
|
end
|
| 666 |
|
|
endtask // bus_off_recovery_test
|
| 667 |
|
|
|
| 668 |
|
|
|
| 669 |
|
|
task error_test;
|
| 670 |
|
|
begin
|
| 671 |
|
|
// Switch-off reset mode
|
| 672 |
|
|
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 673 |
|
|
write_register2(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 674 |
|
|
|
| 675 |
|
|
// Set Clock Divider register
|
| 676 |
|
|
extended_mode = 1'b1;
|
| 677 |
|
|
write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended)
|
| 678 |
|
|
write_register2(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended)
|
| 679 |
|
|
|
| 680 |
|
|
// Set error warning limit register
|
| 681 |
|
|
write_register(8'd13, 8'h56); // error warning limit
|
| 682 |
|
|
|
| 683 |
|
|
// Switch-off reset mode
|
| 684 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 685 |
|
|
write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 686 |
|
|
|
| 687 |
|
|
// Enable all interrupts
|
| 688 |
|
|
write_register(8'd4, 8'hff); // irq enable register
|
| 689 |
|
|
|
| 690 |
|
|
repeat (300) send_bit(0);
|
| 691 |
|
|
|
| 692 |
|
|
$display("Kr neki");
|
| 693 |
|
|
|
| 694 |
|
|
end
|
| 695 |
|
|
endtask
|
| 696 |
|
|
|
| 697 |
|
|
|
| 698 |
|
|
task register_test;
|
| 699 |
|
|
integer i, j, tmp;
|
| 700 |
|
|
begin
|
| 701 |
|
|
$display("Change mode to extended mode and test registers");
|
| 702 |
|
|
// Switch-off reset mode
|
| 703 |
|
|
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 704 |
|
|
write_register2(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 705 |
|
|
|
| 706 |
|
|
// Set Clock Divider register
|
| 707 |
|
|
extended_mode = 1'b1;
|
| 708 |
|
|
write_register(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended)
|
| 709 |
|
|
write_register2(8'd31, {extended_mode, 3'h0, 1'b0, 3'h0}); // Setting the normal mode (not extended)
|
| 710 |
|
|
|
| 711 |
|
|
// Switch-off reset mode
|
| 712 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 713 |
|
|
write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 714 |
|
|
|
| 715 |
|
|
for (i=1; i<128; i=i+1) begin
|
| 716 |
|
|
for (j=0; j<8; j=j+1) begin
|
| 717 |
|
|
read_register(i, tmp_data);
|
| 718 |
|
|
write_register(i, tmp_data | (1 << j));
|
| 719 |
|
|
end
|
| 720 |
|
|
end
|
| 721 |
|
|
|
| 722 |
|
|
end
|
| 723 |
|
|
endtask
|
| 724 |
|
|
|
| 725 |
83 |
mohor |
task forced_bus_off; // Forcing bus-off by writinf to tx_err_cnt register
|
| 726 |
|
|
begin
|
| 727 |
|
|
|
| 728 |
|
|
// Switch-on reset mode
|
| 729 |
|
|
write_register(8'd0, {7'h0, `CAN_MODE_RESET});
|
| 730 |
|
|
|
| 731 |
|
|
// Set Clock Divider register
|
| 732 |
|
|
write_register(8'd31, {1'b1, 7'h0}); // Setting the extended mode (not normal)
|
| 733 |
|
|
|
| 734 |
|
|
// Write 255 to tx_err_cnt register - Forcing bus-off
|
| 735 |
|
|
write_register(8'd15, 255);
|
| 736 |
|
|
|
| 737 |
|
|
// Switch-off reset mode
|
| 738 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 739 |
|
|
|
| 740 |
|
|
// #1000000;
|
| 741 |
|
|
#2500000;
|
| 742 |
|
|
|
| 743 |
|
|
|
| 744 |
|
|
// Switch-on reset mode
|
| 745 |
|
|
write_register(8'd0, {7'h0, `CAN_MODE_RESET});
|
| 746 |
|
|
|
| 747 |
|
|
// Write 245 to tx_err_cnt register
|
| 748 |
|
|
write_register(8'd15, 245);
|
| 749 |
|
|
|
| 750 |
|
|
// Switch-off reset mode
|
| 751 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 752 |
|
|
|
| 753 |
|
|
#1000000;
|
| 754 |
|
|
|
| 755 |
|
|
|
| 756 |
|
|
end
|
| 757 |
|
|
endtask // forced_bus_off
|
| 758 |
|
|
|
| 759 |
|
|
|
| 760 |
|
|
task manual_frame_basic; // Testbench sends a basic format frame
|
| 761 |
|
|
begin
|
| 762 |
|
|
|
| 763 |
|
|
|
| 764 |
|
|
// Switch-on reset mode
|
| 765 |
|
|
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 766 |
|
|
|
| 767 |
|
|
// Set Acceptance Code and Acceptance Mask registers
|
| 768 |
|
|
write_register(8'd4, 8'h28); // acceptance code
|
| 769 |
|
|
write_register(8'd5, 8'hff); // acceptance mask
|
| 770 |
|
|
|
| 771 |
|
|
repeat (100) @ (posedge clk);
|
| 772 |
|
|
|
| 773 |
|
|
// Switch-off reset mode
|
| 774 |
158 |
igorm |
// write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 775 |
|
|
write_register(8'd0, 8'h1e); // reset_off, all irqs enabled.
|
| 776 |
83 |
mohor |
|
| 777 |
|
|
// After exiting the reset mode sending bus free
|
| 778 |
|
|
repeat (11) send_bit(1);
|
| 779 |
|
|
|
| 780 |
|
|
write_register(8'd10, 8'h55); // Writing ID[10:3] = 0x55
|
| 781 |
158 |
igorm |
write_register(8'd11, 8'h77); // Writing ID[2:0] = 0x3, rtr = 1, length = 7
|
| 782 |
83 |
mohor |
write_register(8'd12, 8'h00); // data byte 1
|
| 783 |
|
|
write_register(8'd13, 8'h00); // data byte 2
|
| 784 |
|
|
write_register(8'd14, 8'h00); // data byte 3
|
| 785 |
|
|
write_register(8'd15, 8'h00); // data byte 4
|
| 786 |
|
|
write_register(8'd16, 8'h00); // data byte 5
|
| 787 |
|
|
write_register(8'd17, 8'h00); // data byte 6
|
| 788 |
|
|
write_register(8'd18, 8'h00); // data byte 7
|
| 789 |
|
|
write_register(8'd19, 8'h00); // data byte 8
|
| 790 |
|
|
|
| 791 |
158 |
igorm |
tx_bypassed = 0; // When this signal is on, tx is not looped back to the rx.
|
| 792 |
83 |
mohor |
|
| 793 |
158 |
igorm |
|
| 794 |
83 |
mohor |
fork
|
| 795 |
|
|
begin
|
| 796 |
158 |
igorm |
tx_request_command;
|
| 797 |
|
|
// self_reception_request_command;
|
| 798 |
83 |
mohor |
end
|
| 799 |
|
|
|
| 800 |
|
|
begin
|
| 801 |
158 |
igorm |
#931;
|
| 802 |
83 |
mohor |
|
| 803 |
|
|
|
| 804 |
|
|
repeat (1)
|
| 805 |
|
|
begin
|
| 806 |
|
|
send_bit(0); // SOF
|
| 807 |
|
|
send_bit(0); // ID
|
| 808 |
|
|
send_bit(1); // ID
|
| 809 |
|
|
send_bit(0); // ID
|
| 810 |
|
|
send_bit(1); // ID
|
| 811 |
|
|
send_bit(0); // ID
|
| 812 |
|
|
send_bit(1); // ID
|
| 813 |
|
|
send_bit(0); // ID
|
| 814 |
|
|
send_bit(1); // ID
|
| 815 |
|
|
send_bit(0); // ID
|
| 816 |
|
|
send_bit(1); // ID
|
| 817 |
158 |
igorm |
send_bit(0); // ID arbi lost
|
| 818 |
83 |
mohor |
send_bit(1); // RTR
|
| 819 |
|
|
send_bit(0); // IDE
|
| 820 |
|
|
send_bit(0); // r0
|
| 821 |
|
|
send_bit(0); // DLC
|
| 822 |
|
|
send_bit(1); // DLC
|
| 823 |
|
|
send_bit(1); // DLC
|
| 824 |
|
|
send_bit(1); // DLC
|
| 825 |
|
|
send_bit(1); // CRC
|
| 826 |
|
|
send_bit(1); // CRC
|
| 827 |
|
|
send_bit(0); // CRC stuff
|
| 828 |
|
|
send_bit(0); // CRC 6
|
| 829 |
|
|
send_bit(0); // CRC
|
| 830 |
|
|
send_bit(0); // CRC
|
| 831 |
|
|
send_bit(0); // CRC
|
| 832 |
|
|
send_bit(1); // CRC stuff
|
| 833 |
|
|
send_bit(0); // CRC 0
|
| 834 |
|
|
send_bit(0); // CRC
|
| 835 |
|
|
send_bit(1); // CRC
|
| 836 |
|
|
send_bit(0); // CRC
|
| 837 |
|
|
send_bit(1); // CRC 5
|
| 838 |
|
|
send_bit(1); // CRC
|
| 839 |
|
|
send_bit(0); // CRC
|
| 840 |
|
|
send_bit(1); // CRC
|
| 841 |
|
|
send_bit(1); // CRC b
|
| 842 |
|
|
send_bit(1); // CRC DELIM
|
| 843 |
|
|
send_bit(0); // ACK
|
| 844 |
|
|
send_bit(1); // ACK DELIM
|
| 845 |
|
|
send_bit(1); // EOF
|
| 846 |
|
|
send_bit(1); // EOF
|
| 847 |
|
|
send_bit(1); // EOF
|
| 848 |
|
|
send_bit(1); // EOF
|
| 849 |
|
|
send_bit(1); // EOF
|
| 850 |
|
|
send_bit(1); // EOF
|
| 851 |
|
|
send_bit(1); // EOF
|
| 852 |
|
|
send_bit(1); // INTER
|
| 853 |
|
|
send_bit(1); // INTER
|
| 854 |
|
|
send_bit(1); // INTER
|
| 855 |
158 |
igorm |
#400;
|
| 856 |
|
|
|
| 857 |
|
|
send_bit(0); // SOF
|
| 858 |
|
|
send_bit(0); // ID
|
| 859 |
|
|
send_bit(1); // ID
|
| 860 |
|
|
send_bit(0); // ID
|
| 861 |
|
|
send_bit(1); // ID
|
| 862 |
|
|
send_bit(0); // ID
|
| 863 |
|
|
send_bit(1); // ID
|
| 864 |
|
|
send_bit(0); // ID
|
| 865 |
|
|
send_bit(1); // ID
|
| 866 |
|
|
send_bit(0); // ID
|
| 867 |
|
|
send_bit(1); // ID
|
| 868 |
|
|
send_bit(1); // ID
|
| 869 |
|
|
send_bit(1); // RTR
|
| 870 |
|
|
send_bit(0); // IDE
|
| 871 |
|
|
send_bit(0); // r0
|
| 872 |
|
|
send_bit(0); // DLC
|
| 873 |
|
|
send_bit(1); // DLC
|
| 874 |
|
|
send_bit(1); // DLC
|
| 875 |
|
|
send_bit(1); // DLC
|
| 876 |
|
|
send_bit(1); // CRC
|
| 877 |
|
|
send_bit(0); // CRC
|
| 878 |
|
|
send_bit(0); // CRC 6
|
| 879 |
|
|
send_bit(0); // CRC
|
| 880 |
|
|
send_bit(0); // CRC
|
| 881 |
|
|
send_bit(1); // CRC
|
| 882 |
|
|
send_bit(0); // CRC 0
|
| 883 |
|
|
send_bit(0); // CRC
|
| 884 |
|
|
send_bit(1); // CRC
|
| 885 |
|
|
send_bit(0); // CRC
|
| 886 |
|
|
send_bit(0); // CRC 5
|
| 887 |
|
|
send_bit(1); // CRC
|
| 888 |
|
|
send_bit(0); // CRC
|
| 889 |
|
|
send_bit(0); // CRC
|
| 890 |
|
|
send_bit(0); // CRC b
|
| 891 |
|
|
send_bit(1); // CRC DELIM
|
| 892 |
|
|
send_bit(0); // ACK
|
| 893 |
|
|
send_bit(1); // ACK DELIM
|
| 894 |
|
|
send_bit(1); // EOF
|
| 895 |
|
|
send_bit(1); // EOF
|
| 896 |
|
|
send_bit(1); // EOF
|
| 897 |
|
|
send_bit(1); // EOF
|
| 898 |
|
|
send_bit(1); // EOF
|
| 899 |
|
|
send_bit(1); // EOF
|
| 900 |
|
|
send_bit(1); // EOF
|
| 901 |
|
|
send_bit(1); // INTER
|
| 902 |
|
|
send_bit(1); // INTER
|
| 903 |
|
|
send_bit(1); // INTER
|
| 904 |
83 |
mohor |
end // repeat
|
| 905 |
|
|
|
| 906 |
|
|
|
| 907 |
|
|
|
| 908 |
|
|
end
|
| 909 |
|
|
|
| 910 |
|
|
|
| 911 |
|
|
join
|
| 912 |
|
|
|
| 913 |
|
|
|
| 914 |
|
|
|
| 915 |
|
|
read_receive_buffer;
|
| 916 |
|
|
release_rx_buffer_command;
|
| 917 |
|
|
|
| 918 |
160 |
igorm |
#1000 read_register(8'd3, tmp_data);
|
| 919 |
83 |
mohor |
read_receive_buffer;
|
| 920 |
|
|
release_rx_buffer_command;
|
| 921 |
|
|
read_receive_buffer;
|
| 922 |
|
|
|
| 923 |
158 |
igorm |
// First we receive a msg
|
| 924 |
|
|
send_bit(0); // SOF
|
| 925 |
|
|
send_bit(0); // ID
|
| 926 |
|
|
send_bit(1); // ID
|
| 927 |
|
|
send_bit(0); // ID
|
| 928 |
|
|
send_bit(1); // ID
|
| 929 |
|
|
send_bit(0); // ID
|
| 930 |
|
|
send_bit(1); // ID
|
| 931 |
|
|
send_bit(0); // ID
|
| 932 |
|
|
send_bit(1); // ID
|
| 933 |
|
|
send_bit(0); // ID
|
| 934 |
|
|
send_bit(1); // ID
|
| 935 |
|
|
send_bit(1); // ID
|
| 936 |
|
|
send_bit(1); // RTR
|
| 937 |
|
|
send_bit(0); // IDE
|
| 938 |
|
|
send_bit(0); // r0
|
| 939 |
|
|
send_bit(0); // DLC
|
| 940 |
|
|
send_bit(1); // DLC
|
| 941 |
|
|
send_bit(1); // DLC
|
| 942 |
|
|
send_bit(1); // DLC
|
| 943 |
|
|
send_bit(1); // CRC
|
| 944 |
|
|
send_bit(0); // CRC
|
| 945 |
|
|
send_bit(0); // CRC 6
|
| 946 |
|
|
send_bit(0); // CRC
|
| 947 |
|
|
send_bit(0); // CRC
|
| 948 |
|
|
send_bit(1); // CRC
|
| 949 |
|
|
send_bit(0); // CRC 0
|
| 950 |
|
|
send_bit(0); // CRC
|
| 951 |
|
|
send_bit(1); // CRC
|
| 952 |
|
|
send_bit(0); // CRC
|
| 953 |
|
|
send_bit(0); // CRC 5
|
| 954 |
|
|
send_bit(1); // CRC
|
| 955 |
|
|
send_bit(0); // CRC
|
| 956 |
|
|
send_bit(0); // CRC
|
| 957 |
|
|
send_bit(0); // CRC b
|
| 958 |
|
|
send_bit(1); // CRC DELIM
|
| 959 |
|
|
send_bit(0); // ACK
|
| 960 |
|
|
send_bit(1); // ACK DELIM
|
| 961 |
|
|
send_bit(1); // EOF
|
| 962 |
|
|
send_bit(1); // EOF
|
| 963 |
|
|
send_bit(1); // EOF
|
| 964 |
|
|
send_bit(1); // EOF
|
| 965 |
|
|
send_bit(1); // EOF
|
| 966 |
|
|
send_bit(1); // EOF
|
| 967 |
|
|
send_bit(1); // EOF
|
| 968 |
|
|
send_bit(1); // INTER
|
| 969 |
|
|
send_bit(1); // INTER
|
| 970 |
|
|
send_bit(1); // INTER
|
| 971 |
|
|
|
| 972 |
|
|
|
| 973 |
|
|
|
| 974 |
|
|
|
| 975 |
|
|
|
| 976 |
|
|
fork
|
| 977 |
|
|
begin
|
| 978 |
|
|
tx_request_command;
|
| 979 |
|
|
// self_reception_request_command;
|
| 980 |
|
|
end
|
| 981 |
|
|
|
| 982 |
|
|
begin
|
| 983 |
|
|
#931;
|
| 984 |
|
|
|
| 985 |
|
|
|
| 986 |
|
|
repeat (1)
|
| 987 |
|
|
begin
|
| 988 |
|
|
send_bit(0); // SOF
|
| 989 |
|
|
send_bit(0); // ID
|
| 990 |
|
|
send_bit(1); // ID
|
| 991 |
|
|
send_bit(0); // ID
|
| 992 |
|
|
send_bit(1); // ID
|
| 993 |
|
|
send_bit(0); // ID
|
| 994 |
|
|
send_bit(1); // ID
|
| 995 |
|
|
send_bit(0); // ID
|
| 996 |
|
|
send_bit(1); // ID
|
| 997 |
|
|
send_bit(0); // ID
|
| 998 |
|
|
send_bit(1); // ID
|
| 999 |
|
|
send_bit(0); // ID arbi lost
|
| 1000 |
|
|
send_bit(1); // RTR
|
| 1001 |
|
|
send_bit(0); // IDE
|
| 1002 |
|
|
send_bit(0); // r0
|
| 1003 |
|
|
send_bit(0); // DLC
|
| 1004 |
|
|
send_bit(1); // DLC
|
| 1005 |
|
|
send_bit(1); // DLC
|
| 1006 |
|
|
send_bit(1); // DLC
|
| 1007 |
|
|
send_bit(1); // CRC
|
| 1008 |
|
|
send_bit(0); // CRC
|
| 1009 |
|
|
send_bit(0); // CRC 6
|
| 1010 |
|
|
send_bit(0); // CRC
|
| 1011 |
|
|
send_bit(0); // CRC
|
| 1012 |
|
|
send_bit(1); // CRC
|
| 1013 |
|
|
send_bit(0); // CRC 0
|
| 1014 |
|
|
send_bit(0); // CRC
|
| 1015 |
|
|
send_bit(1); // CRC
|
| 1016 |
|
|
send_bit(0); // CRC
|
| 1017 |
|
|
send_bit(0); // CRC 5
|
| 1018 |
|
|
send_bit(1); // CRC
|
| 1019 |
|
|
send_bit(0); // CRC
|
| 1020 |
|
|
send_bit(0); // CRC
|
| 1021 |
|
|
send_bit(0); // CRC b
|
| 1022 |
|
|
send_bit(1); // CRC DELIM
|
| 1023 |
|
|
send_bit(0); // ACK
|
| 1024 |
|
|
send_bit(1); // ACK DELIM
|
| 1025 |
|
|
send_bit(1); // EOF
|
| 1026 |
|
|
send_bit(1); // EOF
|
| 1027 |
|
|
send_bit(1); // EOF
|
| 1028 |
|
|
send_bit(1); // EOF
|
| 1029 |
|
|
send_bit(1); // EOF
|
| 1030 |
|
|
send_bit(1); // EOF
|
| 1031 |
|
|
send_bit(1); // EOF
|
| 1032 |
|
|
send_bit(1); // INTER
|
| 1033 |
|
|
send_bit(1); // INTER
|
| 1034 |
|
|
send_bit(1); // INTER
|
| 1035 |
|
|
#6000;
|
| 1036 |
|
|
|
| 1037 |
|
|
send_bit(0); // SOF
|
| 1038 |
|
|
send_bit(0); // ID
|
| 1039 |
|
|
send_bit(1); // ID
|
| 1040 |
|
|
send_bit(0); // ID
|
| 1041 |
|
|
send_bit(1); // ID
|
| 1042 |
|
|
send_bit(0); // ID
|
| 1043 |
|
|
send_bit(1); // ID
|
| 1044 |
|
|
send_bit(0); // ID
|
| 1045 |
|
|
send_bit(1); // ID
|
| 1046 |
|
|
send_bit(0); // ID
|
| 1047 |
|
|
send_bit(1); // ID
|
| 1048 |
|
|
send_bit(1); // ID
|
| 1049 |
|
|
send_bit(1); // RTR
|
| 1050 |
|
|
send_bit(0); // IDE
|
| 1051 |
|
|
send_bit(0); // r0
|
| 1052 |
|
|
send_bit(0); // DLC
|
| 1053 |
|
|
send_bit(1); // DLC
|
| 1054 |
|
|
send_bit(1); // DLC
|
| 1055 |
|
|
send_bit(1); // DLC
|
| 1056 |
|
|
send_bit(1); // CRC
|
| 1057 |
|
|
send_bit(0); // CRC
|
| 1058 |
|
|
send_bit(0); // CRC 6
|
| 1059 |
|
|
send_bit(0); // CRC
|
| 1060 |
|
|
send_bit(0); // CRC
|
| 1061 |
|
|
send_bit(1); // CRC
|
| 1062 |
|
|
send_bit(0); // CRC 0
|
| 1063 |
|
|
send_bit(0); // CRC
|
| 1064 |
|
|
send_bit(1); // CRC
|
| 1065 |
|
|
send_bit(0); // CRC
|
| 1066 |
|
|
send_bit(0); // CRC 5
|
| 1067 |
|
|
send_bit(1); // CRC
|
| 1068 |
|
|
send_bit(0); // CRC
|
| 1069 |
|
|
send_bit(0); // CRC
|
| 1070 |
|
|
send_bit(0); // CRC b
|
| 1071 |
|
|
send_bit(1); // CRC DELIM
|
| 1072 |
|
|
send_bit(0); // ACK
|
| 1073 |
|
|
send_bit(1); // ACK DELIM
|
| 1074 |
|
|
send_bit(1); // EOF
|
| 1075 |
|
|
send_bit(1); // EOF
|
| 1076 |
|
|
send_bit(1); // EOF
|
| 1077 |
|
|
send_bit(1); // EOF
|
| 1078 |
|
|
send_bit(1); // EOF
|
| 1079 |
|
|
send_bit(1); // EOF
|
| 1080 |
|
|
send_bit(1); // EOF
|
| 1081 |
|
|
send_bit(1); // INTER
|
| 1082 |
|
|
send_bit(1); // INTER
|
| 1083 |
|
|
send_bit(1); // INTER
|
| 1084 |
|
|
end // repeat
|
| 1085 |
|
|
|
| 1086 |
|
|
|
| 1087 |
|
|
|
| 1088 |
|
|
end
|
| 1089 |
|
|
|
| 1090 |
|
|
|
| 1091 |
|
|
join
|
| 1092 |
|
|
|
| 1093 |
|
|
|
| 1094 |
|
|
|
| 1095 |
|
|
read_receive_buffer;
|
| 1096 |
|
|
release_rx_buffer_command;
|
| 1097 |
|
|
|
| 1098 |
160 |
igorm |
#1000 read_register(8'd3, tmp_data);
|
| 1099 |
158 |
igorm |
read_receive_buffer;
|
| 1100 |
|
|
release_rx_buffer_command;
|
| 1101 |
|
|
read_receive_buffer;
|
| 1102 |
|
|
|
| 1103 |
83 |
mohor |
#4000000;
|
| 1104 |
|
|
|
| 1105 |
|
|
end
|
| 1106 |
|
|
endtask // manual_frame_basic
|
| 1107 |
|
|
|
| 1108 |
|
|
|
| 1109 |
|
|
|
| 1110 |
|
|
task manual_frame_ext; // Testbench sends an extended format frame
|
| 1111 |
|
|
begin
|
| 1112 |
|
|
|
| 1113 |
|
|
|
| 1114 |
|
|
// Switch-on reset mode
|
| 1115 |
|
|
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 1116 |
|
|
|
| 1117 |
|
|
// Set Clock Divider register
|
| 1118 |
|
|
extended_mode = 1'b1;
|
| 1119 |
|
|
write_register(8'd31, {extended_mode, 7'h0}); // Setting the extended mode
|
| 1120 |
|
|
|
| 1121 |
|
|
// Set Acceptance Code and Acceptance Mask registers
|
| 1122 |
|
|
write_register(8'd16, 8'ha6); // acceptance code 0
|
| 1123 |
|
|
write_register(8'd17, 8'h00); // acceptance code 1
|
| 1124 |
|
|
write_register(8'd18, 8'h5a); // acceptance code 2
|
| 1125 |
|
|
write_register(8'd19, 8'hac); // acceptance code 3
|
| 1126 |
|
|
write_register(8'd20, 8'h00); // acceptance mask 0
|
| 1127 |
|
|
write_register(8'd21, 8'h00); // acceptance mask 1
|
| 1128 |
|
|
write_register(8'd22, 8'h00); // acceptance mask 2
|
| 1129 |
|
|
write_register(8'd23, 8'h00); // acceptance mask 3
|
| 1130 |
|
|
|
| 1131 |
160 |
igorm |
//write_register(8'd14, 8'h7a); // rx err cnt
|
| 1132 |
|
|
//write_register(8'd15, 8'h7a); // tx err cnt
|
| 1133 |
|
|
|
| 1134 |
|
|
//read_register(8'd14, tmp_data); // rx err cnt
|
| 1135 |
|
|
//read_register(8'd15, tmp_data); // tx err cnt
|
| 1136 |
|
|
|
| 1137 |
83 |
mohor |
repeat (100) @ (posedge clk);
|
| 1138 |
|
|
|
| 1139 |
|
|
// Switch-off reset mode
|
| 1140 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 1141 |
|
|
|
| 1142 |
|
|
// After exiting the reset mode sending bus free
|
| 1143 |
|
|
repeat (11) send_bit(1);
|
| 1144 |
|
|
|
| 1145 |
|
|
|
| 1146 |
|
|
// Extended frame format
|
| 1147 |
|
|
// Writing TX frame information + identifier + data
|
| 1148 |
|
|
write_register(8'd16, 8'hc5); // Frame format = 1, Remote transmision request = 1, DLC = 5
|
| 1149 |
|
|
write_register(8'd17, 8'ha6); // ID[28:21] = a6
|
| 1150 |
|
|
write_register(8'd18, 8'h00); // ID[20:13] = 00
|
| 1151 |
|
|
write_register(8'd19, 8'h5a); // ID[12:5] = 5a
|
| 1152 |
|
|
write_register(8'd20, 8'ha8); // ID[4:0] = 15
|
| 1153 |
|
|
// write_register(8'd21, 8'h78); RTR does not send any data
|
| 1154 |
|
|
// write_register(8'd22, 8'h9a);
|
| 1155 |
|
|
// write_register(8'd23, 8'hbc);
|
| 1156 |
|
|
// write_register(8'd24, 8'hde);
|
| 1157 |
|
|
// write_register(8'd25, 8'hf0);
|
| 1158 |
|
|
// write_register(8'd26, 8'h0f);
|
| 1159 |
|
|
// write_register(8'd27, 8'hed);
|
| 1160 |
|
|
// write_register(8'd28, 8'hcb);
|
| 1161 |
|
|
|
| 1162 |
|
|
|
| 1163 |
|
|
// Enabling IRQ's (extended mode)
|
| 1164 |
|
|
write_register(8'd4, 8'hff);
|
| 1165 |
|
|
|
| 1166 |
|
|
// tx_bypassed = 1; // When this signal is on, tx is not looped back to the rx.
|
| 1167 |
|
|
|
| 1168 |
|
|
fork
|
| 1169 |
|
|
begin
|
| 1170 |
|
|
tx_request_command;
|
| 1171 |
|
|
// self_reception_request_command;
|
| 1172 |
|
|
end
|
| 1173 |
|
|
|
| 1174 |
|
|
begin
|
| 1175 |
158 |
igorm |
#771;
|
| 1176 |
83 |
mohor |
|
| 1177 |
|
|
repeat (1)
|
| 1178 |
|
|
begin
|
| 1179 |
|
|
send_bit(0); // SOF
|
| 1180 |
|
|
send_bit(1); // ID
|
| 1181 |
|
|
send_bit(0); // ID
|
| 1182 |
|
|
send_bit(1); // ID
|
| 1183 |
|
|
send_bit(0); // ID a
|
| 1184 |
|
|
send_bit(0); // ID
|
| 1185 |
|
|
send_bit(1); // ID
|
| 1186 |
|
|
send_bit(1); // ID
|
| 1187 |
|
|
send_bit(0); // ID 6
|
| 1188 |
|
|
send_bit(0); // ID
|
| 1189 |
|
|
send_bit(0); // ID
|
| 1190 |
|
|
send_bit(0); // ID
|
| 1191 |
|
|
send_bit(1); // RTR
|
| 1192 |
|
|
send_bit(1); // IDE
|
| 1193 |
|
|
send_bit(0); // ID 0
|
| 1194 |
|
|
send_bit(0); // ID
|
| 1195 |
|
|
send_bit(0); // ID
|
| 1196 |
|
|
send_bit(0); // ID
|
| 1197 |
|
|
send_bit(0); // ID 0
|
| 1198 |
|
|
send_bit(1); // ID stuff
|
| 1199 |
|
|
send_bit(0); // ID
|
| 1200 |
|
|
send_bit(1); // ID
|
| 1201 |
|
|
send_bit(0); // ID
|
| 1202 |
|
|
send_bit(1); // ID 6
|
| 1203 |
|
|
send_bit(1); // ID
|
| 1204 |
|
|
send_bit(0); // ID
|
| 1205 |
|
|
send_bit(1); // ID
|
| 1206 |
|
|
send_bit(0); // ID a
|
| 1207 |
|
|
send_bit(1); // ID 1
|
| 1208 |
|
|
send_bit(0); // ID
|
| 1209 |
158 |
igorm |
send_bit(1); // ID
|
| 1210 |
|
|
send_bit(0); // ID
|
| 1211 |
|
|
send_bit(0); // ID 5 // Force arbitration lost
|
| 1212 |
|
|
send_bit(1); // RTR
|
| 1213 |
|
|
send_bit(0); // r1
|
| 1214 |
|
|
send_bit(0); // r0
|
| 1215 |
|
|
send_bit(0); // DLC
|
| 1216 |
|
|
send_bit(1); // DLC
|
| 1217 |
|
|
send_bit(0); // DLC
|
| 1218 |
|
|
send_bit(1); // DLC
|
| 1219 |
|
|
send_bit(1); // CRC
|
| 1220 |
|
|
send_bit(1); // CRC
|
| 1221 |
|
|
send_bit(0); // CRC 6
|
| 1222 |
|
|
send_bit(1); // CRC
|
| 1223 |
|
|
send_bit(1); // CRC
|
| 1224 |
|
|
send_bit(1); // CRC
|
| 1225 |
|
|
send_bit(1); // CRC f
|
| 1226 |
|
|
send_bit(0); // CRC
|
| 1227 |
|
|
send_bit(0); // CRC
|
| 1228 |
|
|
send_bit(1); // CRC
|
| 1229 |
|
|
send_bit(0); // CRC 2
|
| 1230 |
|
|
send_bit(1); // CRC
|
| 1231 |
|
|
send_bit(0); // CRC
|
| 1232 |
|
|
send_bit(1); // CRC
|
| 1233 |
|
|
send_bit(0); // CRC a
|
| 1234 |
|
|
send_bit(1); // CRC DELIM
|
| 1235 |
|
|
send_bit(0); // ACK
|
| 1236 |
|
|
send_bit(1); // ACK DELIM
|
| 1237 |
|
|
send_bit(1); // EOF
|
| 1238 |
|
|
send_bit(1); // EOF
|
| 1239 |
|
|
send_bit(1); // EOF
|
| 1240 |
|
|
send_bit(1); // EOF
|
| 1241 |
|
|
send_bit(1); // EOF
|
| 1242 |
|
|
send_bit(1); // EOF
|
| 1243 |
|
|
send_bit(1); // EOF
|
| 1244 |
|
|
send_bit(1); // INTER
|
| 1245 |
|
|
send_bit(1); // INTER
|
| 1246 |
|
|
send_bit(1); // INTER
|
| 1247 |
|
|
#80;
|
| 1248 |
|
|
send_bit(0); // SOF
|
| 1249 |
|
|
send_bit(1); // ID
|
| 1250 |
|
|
send_bit(0); // ID
|
| 1251 |
|
|
send_bit(1); // ID
|
| 1252 |
|
|
send_bit(0); // ID a
|
| 1253 |
|
|
send_bit(0); // ID
|
| 1254 |
|
|
send_bit(1); // ID
|
| 1255 |
|
|
send_bit(1); // ID
|
| 1256 |
|
|
send_bit(0); // ID 6
|
| 1257 |
|
|
send_bit(0); // ID
|
| 1258 |
|
|
send_bit(0); // ID
|
| 1259 |
|
|
send_bit(0); // ID
|
| 1260 |
|
|
send_bit(1); // RTR
|
| 1261 |
|
|
send_bit(1); // IDE
|
| 1262 |
|
|
send_bit(0); // ID 0
|
| 1263 |
|
|
send_bit(0); // ID
|
| 1264 |
|
|
send_bit(0); // ID
|
| 1265 |
|
|
send_bit(0); // ID
|
| 1266 |
|
|
send_bit(0); // ID 0
|
| 1267 |
|
|
send_bit(1); // ID stuff
|
| 1268 |
|
|
send_bit(0); // ID
|
| 1269 |
83 |
mohor |
send_bit(1); // ID
|
| 1270 |
|
|
send_bit(0); // ID
|
| 1271 |
158 |
igorm |
send_bit(1); // ID 6
|
| 1272 |
|
|
send_bit(1); // ID
|
| 1273 |
|
|
send_bit(0); // ID
|
| 1274 |
|
|
send_bit(1); // ID
|
| 1275 |
|
|
send_bit(0); // ID a
|
| 1276 |
|
|
send_bit(1); // ID 1
|
| 1277 |
|
|
send_bit(0); // ID
|
| 1278 |
|
|
send_bit(0); // ID // Force arbitration lost
|
| 1279 |
|
|
send_bit(0); // ID
|
| 1280 |
83 |
mohor |
send_bit(1); // ID 5
|
| 1281 |
|
|
send_bit(1); // RTR
|
| 1282 |
|
|
send_bit(0); // r1
|
| 1283 |
|
|
send_bit(0); // r0
|
| 1284 |
|
|
send_bit(0); // DLC
|
| 1285 |
|
|
send_bit(1); // DLC
|
| 1286 |
|
|
send_bit(0); // DLC
|
| 1287 |
|
|
send_bit(1); // DLC
|
| 1288 |
158 |
igorm |
send_bit(0); // CRC
|
| 1289 |
|
|
send_bit(0); // CRC
|
| 1290 |
|
|
send_bit(0); // CRC 0
|
| 1291 |
|
|
send_bit(0); // CRC
|
| 1292 |
|
|
send_bit(0); // CRC
|
| 1293 |
|
|
send_bit(1); // CRC stuff
|
| 1294 |
|
|
send_bit(0); // CRC
|
| 1295 |
|
|
send_bit(0); // CRC 0
|
| 1296 |
83 |
mohor |
send_bit(1); // CRC
|
| 1297 |
158 |
igorm |
send_bit(1); // CRC
|
| 1298 |
|
|
send_bit(1); // CRC
|
| 1299 |
|
|
send_bit(0); // CRC e
|
| 1300 |
|
|
send_bit(1); // CRC
|
| 1301 |
|
|
send_bit(1); // CRC
|
| 1302 |
83 |
mohor |
send_bit(0); // CRC
|
| 1303 |
158 |
igorm |
send_bit(0); // CRC c
|
| 1304 |
|
|
send_bit(1); // CRC DELIM
|
| 1305 |
|
|
send_bit(0); // ACK
|
| 1306 |
|
|
send_bit(1); // ACK DELIM
|
| 1307 |
|
|
send_bit(1); // EOF
|
| 1308 |
|
|
send_bit(1); // EOF
|
| 1309 |
|
|
send_bit(1); // EOF
|
| 1310 |
|
|
send_bit(1); // EOF
|
| 1311 |
|
|
send_bit(1); // EOF
|
| 1312 |
|
|
send_bit(1); // EOF
|
| 1313 |
|
|
send_bit(1); // EOF
|
| 1314 |
|
|
send_bit(1); // INTER
|
| 1315 |
|
|
send_bit(1); // INTER
|
| 1316 |
|
|
send_bit(1); // INTER
|
| 1317 |
|
|
|
| 1318 |
|
|
#80;
|
| 1319 |
|
|
send_bit(0); // SOF
|
| 1320 |
|
|
send_bit(1); // ID
|
| 1321 |
|
|
send_bit(0); // ID
|
| 1322 |
|
|
send_bit(1); // ID
|
| 1323 |
|
|
send_bit(0); // ID a
|
| 1324 |
|
|
send_bit(0); // ID
|
| 1325 |
|
|
send_bit(1); // ID
|
| 1326 |
|
|
send_bit(1); // ID
|
| 1327 |
|
|
send_bit(0); // ID 6
|
| 1328 |
|
|
send_bit(0); // ID
|
| 1329 |
|
|
send_bit(0); // ID
|
| 1330 |
|
|
send_bit(0); // ID
|
| 1331 |
|
|
send_bit(1); // RTR
|
| 1332 |
|
|
send_bit(1); // IDE
|
| 1333 |
|
|
send_bit(0); // ID 0
|
| 1334 |
|
|
send_bit(0); // ID
|
| 1335 |
|
|
send_bit(0); // ID
|
| 1336 |
|
|
send_bit(0); // ID
|
| 1337 |
|
|
send_bit(0); // ID 0
|
| 1338 |
|
|
send_bit(1); // ID stuff
|
| 1339 |
|
|
send_bit(0); // ID
|
| 1340 |
|
|
send_bit(1); // ID
|
| 1341 |
|
|
send_bit(0); // ID
|
| 1342 |
|
|
send_bit(1); // ID 6
|
| 1343 |
|
|
send_bit(1); // ID
|
| 1344 |
|
|
send_bit(0); // ID
|
| 1345 |
|
|
send_bit(1); // ID
|
| 1346 |
|
|
send_bit(0); // ID a
|
| 1347 |
|
|
send_bit(1); // ID 1
|
| 1348 |
|
|
send_bit(0); // ID
|
| 1349 |
|
|
send_bit(1); // ID
|
| 1350 |
|
|
send_bit(0); // ID
|
| 1351 |
|
|
send_bit(1); // ID 5
|
| 1352 |
|
|
send_bit(1); // RTR
|
| 1353 |
|
|
send_bit(0); // r1
|
| 1354 |
|
|
send_bit(0); // r0
|
| 1355 |
|
|
send_bit(0); // DLC
|
| 1356 |
|
|
send_bit(1); // DLC
|
| 1357 |
|
|
send_bit(0); // DLC
|
| 1358 |
|
|
send_bit(1); // DLC
|
| 1359 |
|
|
send_bit(1); // CRC
|
| 1360 |
|
|
send_bit(0); // CRC
|
| 1361 |
83 |
mohor |
send_bit(0); // CRC 4
|
| 1362 |
|
|
send_bit(1); // CRC
|
| 1363 |
|
|
send_bit(1); // CRC
|
| 1364 |
|
|
send_bit(0); // CRC
|
| 1365 |
|
|
send_bit(1); // CRC d
|
| 1366 |
|
|
send_bit(0); // CRC
|
| 1367 |
|
|
send_bit(0); // CRC
|
| 1368 |
|
|
send_bit(1); // CRC
|
| 1369 |
|
|
send_bit(1); // CRC 3
|
| 1370 |
|
|
send_bit(1); // CRC
|
| 1371 |
|
|
send_bit(0); // CRC
|
| 1372 |
|
|
send_bit(0); // CRC
|
| 1373 |
|
|
send_bit(1); // CRC 9
|
| 1374 |
|
|
send_bit(1); // CRC DELIM
|
| 1375 |
|
|
send_bit(0); // ACK
|
| 1376 |
|
|
send_bit(1); // ACK DELIM
|
| 1377 |
|
|
send_bit(1); // EOF
|
| 1378 |
|
|
send_bit(1); // EOF
|
| 1379 |
|
|
send_bit(1); // EOF
|
| 1380 |
|
|
send_bit(1); // EOF
|
| 1381 |
|
|
send_bit(1); // EOF
|
| 1382 |
|
|
send_bit(1); // EOF
|
| 1383 |
|
|
send_bit(1); // EOF
|
| 1384 |
|
|
send_bit(1); // INTER
|
| 1385 |
|
|
send_bit(1); // INTER
|
| 1386 |
|
|
send_bit(1); // INTER
|
| 1387 |
|
|
end // repeat
|
| 1388 |
|
|
|
| 1389 |
|
|
|
| 1390 |
|
|
end
|
| 1391 |
|
|
|
| 1392 |
|
|
join
|
| 1393 |
|
|
|
| 1394 |
|
|
|
| 1395 |
|
|
|
| 1396 |
|
|
read_receive_buffer;
|
| 1397 |
|
|
release_rx_buffer_command;
|
| 1398 |
|
|
|
| 1399 |
|
|
read_receive_buffer;
|
| 1400 |
|
|
release_rx_buffer_command;
|
| 1401 |
|
|
read_receive_buffer;
|
| 1402 |
|
|
|
| 1403 |
|
|
// Read irq register
|
| 1404 |
160 |
igorm |
#1 read_register(8'd3, tmp_data);
|
| 1405 |
83 |
mohor |
|
| 1406 |
|
|
// Read error code capture register
|
| 1407 |
160 |
igorm |
read_register(8'd12, tmp_data);
|
| 1408 |
83 |
mohor |
|
| 1409 |
|
|
// Read error capture code register
|
| 1410 |
160 |
igorm |
// read_register(8'd12, tmp_data);
|
| 1411 |
83 |
mohor |
|
| 1412 |
160 |
igorm |
read_register(8'd14, tmp_data); // rx err cnt
|
| 1413 |
|
|
read_register(8'd15, tmp_data); // tx err cnt
|
| 1414 |
|
|
|
| 1415 |
83 |
mohor |
#4000000;
|
| 1416 |
|
|
|
| 1417 |
|
|
end
|
| 1418 |
|
|
endtask // manual_frame_ext
|
| 1419 |
|
|
|
| 1420 |
|
|
|
| 1421 |
|
|
|
| 1422 |
|
|
task bus_off_test; // Testbench sends a frame
|
| 1423 |
|
|
begin
|
| 1424 |
|
|
|
| 1425 |
|
|
write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8
|
| 1426 |
|
|
write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7
|
| 1427 |
|
|
write_register(8'd12, 8'h00); // data byte 1
|
| 1428 |
|
|
write_register(8'd13, 8'h00); // data byte 2
|
| 1429 |
|
|
write_register(8'd14, 8'h00); // data byte 3
|
| 1430 |
|
|
write_register(8'd15, 8'h00); // data byte 4
|
| 1431 |
|
|
write_register(8'd16, 8'h00); // data byte 5
|
| 1432 |
|
|
write_register(8'd17, 8'h00); // data byte 6
|
| 1433 |
|
|
write_register(8'd18, 8'h00); // data byte 7
|
| 1434 |
|
|
write_register(8'd19, 8'h00); // data byte 8
|
| 1435 |
|
|
|
| 1436 |
|
|
fork
|
| 1437 |
|
|
begin
|
| 1438 |
|
|
tx_request_command;
|
| 1439 |
|
|
end
|
| 1440 |
|
|
|
| 1441 |
|
|
begin
|
| 1442 |
|
|
#2000;
|
| 1443 |
|
|
|
| 1444 |
|
|
repeat (16)
|
| 1445 |
|
|
begin
|
| 1446 |
|
|
send_bit(0); // SOF
|
| 1447 |
|
|
send_bit(1); // ID
|
| 1448 |
|
|
send_bit(1); // ID
|
| 1449 |
|
|
send_bit(1); // ID
|
| 1450 |
|
|
send_bit(0); // ID
|
| 1451 |
|
|
send_bit(1); // ID
|
| 1452 |
|
|
send_bit(0); // ID
|
| 1453 |
|
|
send_bit(0); // ID
|
| 1454 |
|
|
send_bit(0); // ID
|
| 1455 |
|
|
send_bit(1); // ID
|
| 1456 |
|
|
send_bit(0); // ID
|
| 1457 |
|
|
send_bit(1); // ID
|
| 1458 |
|
|
send_bit(1); // RTR
|
| 1459 |
|
|
send_bit(0); // IDE
|
| 1460 |
|
|
send_bit(0); // r0
|
| 1461 |
|
|
send_bit(0); // DLC
|
| 1462 |
|
|
send_bit(1); // DLC
|
| 1463 |
|
|
send_bit(1); // DLC
|
| 1464 |
|
|
send_bit(1); // DLC
|
| 1465 |
|
|
send_bit(1); // CRC
|
| 1466 |
|
|
send_bit(0); // CRC
|
| 1467 |
|
|
send_bit(0); // CRC
|
| 1468 |
|
|
send_bit(1); // CRC
|
| 1469 |
|
|
send_bit(1); // CRC
|
| 1470 |
|
|
send_bit(1); // CRC
|
| 1471 |
|
|
send_bit(0); // CRC
|
| 1472 |
|
|
send_bit(1); // CRC
|
| 1473 |
|
|
send_bit(0); // CRC
|
| 1474 |
|
|
send_bit(0); // CRC
|
| 1475 |
|
|
send_bit(1); // CRC
|
| 1476 |
|
|
send_bit(1); // CRC
|
| 1477 |
|
|
send_bit(1); // CRC
|
| 1478 |
|
|
send_bit(1); // CRC
|
| 1479 |
|
|
send_bit(1); // CRC
|
| 1480 |
|
|
send_bit(1); // CRC DELIM
|
| 1481 |
|
|
send_bit(1); // ACK ack error
|
| 1482 |
|
|
send_bit(0); // ERROR
|
| 1483 |
|
|
send_bit(0); // ERROR
|
| 1484 |
|
|
send_bit(0); // ERROR
|
| 1485 |
|
|
send_bit(0); // ERROR
|
| 1486 |
|
|
send_bit(0); // ERROR
|
| 1487 |
|
|
send_bit(0); // ERROR
|
| 1488 |
|
|
send_bit(1); // ERROR DELIM
|
| 1489 |
|
|
send_bit(1); // ERROR DELIM
|
| 1490 |
|
|
send_bit(1); // ERROR DELIM
|
| 1491 |
|
|
send_bit(1); // ERROR DELIM
|
| 1492 |
|
|
send_bit(1); // ERROR DELIM
|
| 1493 |
|
|
send_bit(1); // ERROR DELIM
|
| 1494 |
|
|
send_bit(1); // ERROR DELIM
|
| 1495 |
|
|
send_bit(1); // ERROR DELIM
|
| 1496 |
|
|
send_bit(1); // INTER
|
| 1497 |
|
|
send_bit(1); // INTER
|
| 1498 |
|
|
send_bit(1); // INTER
|
| 1499 |
|
|
end // repeat
|
| 1500 |
|
|
|
| 1501 |
|
|
// Node is error passive now.
|
| 1502 |
|
|
|
| 1503 |
|
|
// Read irq register (error interrupt should be cleared now.
|
| 1504 |
160 |
igorm |
read_register(8'd3, tmp_data);
|
| 1505 |
83 |
mohor |
|
| 1506 |
160 |
igorm |
->igor;
|
| 1507 |
|
|
|
| 1508 |
|
|
repeat (34)
|
| 1509 |
83 |
mohor |
|
| 1510 |
|
|
begin
|
| 1511 |
|
|
send_bit(0); // SOF
|
| 1512 |
|
|
send_bit(1); // ID
|
| 1513 |
|
|
send_bit(1); // ID
|
| 1514 |
|
|
send_bit(1); // ID
|
| 1515 |
|
|
send_bit(0); // ID
|
| 1516 |
|
|
send_bit(1); // ID
|
| 1517 |
|
|
send_bit(0); // ID
|
| 1518 |
|
|
send_bit(0); // ID
|
| 1519 |
|
|
send_bit(0); // ID
|
| 1520 |
|
|
send_bit(1); // ID
|
| 1521 |
|
|
send_bit(0); // ID
|
| 1522 |
|
|
send_bit(1); // ID
|
| 1523 |
|
|
send_bit(1); // RTR
|
| 1524 |
|
|
send_bit(0); // IDE
|
| 1525 |
|
|
send_bit(0); // r0
|
| 1526 |
|
|
send_bit(0); // DLC
|
| 1527 |
|
|
send_bit(1); // DLC
|
| 1528 |
|
|
send_bit(1); // DLC
|
| 1529 |
|
|
send_bit(1); // DLC
|
| 1530 |
|
|
send_bit(1); // CRC
|
| 1531 |
|
|
send_bit(0); // CRC
|
| 1532 |
|
|
send_bit(0); // CRC
|
| 1533 |
|
|
send_bit(1); // CRC
|
| 1534 |
|
|
send_bit(1); // CRC
|
| 1535 |
|
|
send_bit(1); // CRC
|
| 1536 |
|
|
send_bit(0); // CRC
|
| 1537 |
|
|
send_bit(1); // CRC
|
| 1538 |
|
|
send_bit(0); // CRC
|
| 1539 |
|
|
send_bit(0); // CRC
|
| 1540 |
|
|
send_bit(1); // CRC
|
| 1541 |
|
|
send_bit(1); // CRC
|
| 1542 |
|
|
send_bit(1); // CRC
|
| 1543 |
|
|
send_bit(1); // CRC
|
| 1544 |
|
|
send_bit(1); // CRC
|
| 1545 |
|
|
send_bit(1); // CRC DELIM
|
| 1546 |
|
|
send_bit(1); // ACK ack error
|
| 1547 |
|
|
send_bit(0); // ERROR
|
| 1548 |
|
|
send_bit(0); // ERROR
|
| 1549 |
|
|
send_bit(0); // ERROR
|
| 1550 |
|
|
send_bit(0); // ERROR
|
| 1551 |
|
|
send_bit(0); // ERROR
|
| 1552 |
|
|
send_bit(0); // ERROR
|
| 1553 |
|
|
send_bit(1); // ERROR DELIM
|
| 1554 |
|
|
send_bit(1); // ERROR DELIM
|
| 1555 |
|
|
send_bit(1); // ERROR DELIM
|
| 1556 |
|
|
send_bit(1); // ERROR DELIM
|
| 1557 |
|
|
send_bit(1); // ERROR DELIM
|
| 1558 |
|
|
send_bit(1); // ERROR DELIM
|
| 1559 |
|
|
send_bit(1); // ERROR DELIM
|
| 1560 |
|
|
send_bit(1); // ERROR DELIM
|
| 1561 |
|
|
send_bit(1); // INTER
|
| 1562 |
|
|
send_bit(1); // INTER
|
| 1563 |
|
|
send_bit(1); // INTER
|
| 1564 |
|
|
send_bit(1); // SUSPEND
|
| 1565 |
|
|
send_bit(1); // SUSPEND
|
| 1566 |
|
|
send_bit(1); // SUSPEND
|
| 1567 |
|
|
send_bit(1); // SUSPEND
|
| 1568 |
|
|
send_bit(1); // SUSPEND
|
| 1569 |
|
|
send_bit(1); // SUSPEND
|
| 1570 |
|
|
send_bit(1); // SUSPEND
|
| 1571 |
|
|
send_bit(1); // SUSPEND
|
| 1572 |
|
|
end // repeat
|
| 1573 |
|
|
|
| 1574 |
160 |
igorm |
->igor;
|
| 1575 |
|
|
|
| 1576 |
83 |
mohor |
// Node is bus-off now
|
| 1577 |
|
|
|
| 1578 |
|
|
|
| 1579 |
|
|
// Read irq register (error interrupt should be cleared now.
|
| 1580 |
160 |
igorm |
read_register(8'd3, tmp_data);
|
| 1581 |
83 |
mohor |
|
| 1582 |
|
|
|
| 1583 |
|
|
|
| 1584 |
|
|
#100000;
|
| 1585 |
|
|
|
| 1586 |
|
|
// Switch-off reset mode
|
| 1587 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 1588 |
|
|
|
| 1589 |
|
|
repeat (64 * 11)
|
| 1590 |
|
|
begin
|
| 1591 |
|
|
send_bit(1);
|
| 1592 |
|
|
end // repeat
|
| 1593 |
|
|
|
| 1594 |
|
|
// Read irq register (error interrupt should be cleared now.
|
| 1595 |
160 |
igorm |
read_register(8'd3, tmp_data);
|
| 1596 |
83 |
mohor |
|
| 1597 |
|
|
repeat (64 * 11)
|
| 1598 |
|
|
begin
|
| 1599 |
|
|
send_bit(1);
|
| 1600 |
|
|
end // repeat
|
| 1601 |
|
|
|
| 1602 |
|
|
|
| 1603 |
|
|
|
| 1604 |
|
|
// Read irq register (error interrupt should be cleared now.
|
| 1605 |
160 |
igorm |
read_register(8'd3, tmp_data);
|
| 1606 |
83 |
mohor |
|
| 1607 |
|
|
end
|
| 1608 |
|
|
|
| 1609 |
|
|
|
| 1610 |
|
|
|
| 1611 |
|
|
join
|
| 1612 |
|
|
|
| 1613 |
|
|
|
| 1614 |
|
|
|
| 1615 |
|
|
fork
|
| 1616 |
|
|
begin
|
| 1617 |
|
|
tx_request_command;
|
| 1618 |
|
|
end
|
| 1619 |
|
|
|
| 1620 |
|
|
begin
|
| 1621 |
|
|
#1100;
|
| 1622 |
|
|
|
| 1623 |
|
|
send_bit(1); // To spend some time before transmitter is ready.
|
| 1624 |
|
|
|
| 1625 |
|
|
repeat (1)
|
| 1626 |
|
|
begin
|
| 1627 |
|
|
send_bit(0); // SOF
|
| 1628 |
|
|
send_bit(1); // ID
|
| 1629 |
|
|
send_bit(1); // ID
|
| 1630 |
|
|
send_bit(1); // ID
|
| 1631 |
|
|
send_bit(0); // ID
|
| 1632 |
|
|
send_bit(1); // ID
|
| 1633 |
|
|
send_bit(0); // ID
|
| 1634 |
|
|
send_bit(0); // ID
|
| 1635 |
|
|
send_bit(0); // ID
|
| 1636 |
|
|
send_bit(1); // ID
|
| 1637 |
|
|
send_bit(0); // ID
|
| 1638 |
|
|
send_bit(1); // ID
|
| 1639 |
|
|
send_bit(1); // RTR
|
| 1640 |
|
|
send_bit(0); // IDE
|
| 1641 |
|
|
send_bit(0); // r0
|
| 1642 |
|
|
send_bit(0); // DLC
|
| 1643 |
|
|
send_bit(1); // DLC
|
| 1644 |
|
|
send_bit(1); // DLC
|
| 1645 |
|
|
send_bit(1); // DLC
|
| 1646 |
|
|
send_bit(1); // CRC
|
| 1647 |
|
|
send_bit(0); // CRC
|
| 1648 |
|
|
send_bit(0); // CRC
|
| 1649 |
|
|
send_bit(1); // CRC
|
| 1650 |
|
|
send_bit(1); // CRC
|
| 1651 |
|
|
send_bit(1); // CRC
|
| 1652 |
|
|
send_bit(0); // CRC
|
| 1653 |
|
|
send_bit(1); // CRC
|
| 1654 |
|
|
send_bit(0); // CRC
|
| 1655 |
|
|
send_bit(0); // CRC
|
| 1656 |
|
|
send_bit(1); // CRC
|
| 1657 |
|
|
send_bit(1); // CRC
|
| 1658 |
|
|
send_bit(1); // CRC
|
| 1659 |
|
|
send_bit(1); // CRC
|
| 1660 |
|
|
send_bit(1); // CRC
|
| 1661 |
|
|
send_bit(1); // CRC DELIM
|
| 1662 |
|
|
send_bit(0); // ACK
|
| 1663 |
|
|
send_bit(1); // ACK DELIM
|
| 1664 |
|
|
send_bit(1); // EOF
|
| 1665 |
|
|
send_bit(1); // EOF
|
| 1666 |
|
|
send_bit(1); // EOF
|
| 1667 |
|
|
send_bit(1); // EOF
|
| 1668 |
|
|
send_bit(1); // EOF
|
| 1669 |
|
|
send_bit(1); // EOF
|
| 1670 |
|
|
send_bit(1); // EOF
|
| 1671 |
|
|
send_bit(1); // INTER
|
| 1672 |
|
|
send_bit(1); // INTER
|
| 1673 |
|
|
send_bit(1); // INTER
|
| 1674 |
|
|
end // repeat
|
| 1675 |
|
|
end
|
| 1676 |
|
|
|
| 1677 |
|
|
join
|
| 1678 |
|
|
|
| 1679 |
|
|
read_receive_buffer;
|
| 1680 |
|
|
release_rx_buffer_command;
|
| 1681 |
|
|
read_receive_buffer;
|
| 1682 |
|
|
release_rx_buffer_command;
|
| 1683 |
|
|
read_receive_buffer;
|
| 1684 |
|
|
|
| 1685 |
|
|
#4000000;
|
| 1686 |
|
|
|
| 1687 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
|
| 1688 |
|
|
|
| 1689 |
|
|
#1000000;
|
| 1690 |
|
|
|
| 1691 |
|
|
end
|
| 1692 |
|
|
endtask // bus_off_test
|
| 1693 |
|
|
|
| 1694 |
|
|
|
| 1695 |
|
|
|
| 1696 |
|
|
task send_frame_basic; // CAN IP core sends frames
|
| 1697 |
|
|
begin
|
| 1698 |
|
|
|
| 1699 |
|
|
write_register(8'd10, 8'hea); // Writing ID[10:3] = 0xea
|
| 1700 |
|
|
write_register(8'd11, 8'h28); // Writing ID[2:0] = 0x1, rtr = 0, length = 8
|
| 1701 |
|
|
write_register(8'd12, 8'h56); // data byte 1
|
| 1702 |
|
|
write_register(8'd13, 8'h78); // data byte 2
|
| 1703 |
|
|
write_register(8'd14, 8'h9a); // data byte 3
|
| 1704 |
|
|
write_register(8'd15, 8'hbc); // data byte 4
|
| 1705 |
|
|
write_register(8'd16, 8'hde); // data byte 5
|
| 1706 |
|
|
write_register(8'd17, 8'hf0); // data byte 6
|
| 1707 |
|
|
write_register(8'd18, 8'h0f); // data byte 7
|
| 1708 |
|
|
write_register(8'd19, 8'hed); // data byte 8
|
| 1709 |
|
|
|
| 1710 |
|
|
|
| 1711 |
|
|
// Enable irqs (basic mode)
|
| 1712 |
|
|
write_register(8'd0, 8'h1e);
|
| 1713 |
|
|
|
| 1714 |
|
|
|
| 1715 |
|
|
|
| 1716 |
|
|
fork
|
| 1717 |
|
|
|
| 1718 |
|
|
begin
|
| 1719 |
127 |
mohor |
#1100;
|
| 1720 |
83 |
mohor |
$display("\n\nStart receiving data from CAN bus");
|
| 1721 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
|
| 1722 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
|
| 1723 |
|
|
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc
|
| 1724 |
127 |
mohor |
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
|
| 1725 |
158 |
igorm |
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc
|
| 1726 |
83 |
mohor |
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc
|
| 1727 |
|
|
end
|
| 1728 |
|
|
|
| 1729 |
|
|
begin
|
| 1730 |
|
|
tx_request_command;
|
| 1731 |
|
|
end
|
| 1732 |
|
|
|
| 1733 |
|
|
begin
|
| 1734 |
127 |
mohor |
wait (can_testbench.i_can_top.i_can_bsp.go_tx) // waiting for tx to start
|
| 1735 |
|
|
wait (~can_testbench.i_can_top.i_can_bsp.need_to_tx) // waiting for tx to finish
|
| 1736 |
|
|
tx_request_command; // start another tx
|
| 1737 |
|
|
end
|
| 1738 |
|
|
|
| 1739 |
|
|
begin
|
| 1740 |
|
|
// Transmitting acknowledge (for first packet)
|
| 1741 |
|
|
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack & can_testbench.i_can_top.i_can_bsp.tx_point);
|
| 1742 |
83 |
mohor |
#1 rx = 0;
|
| 1743 |
127 |
mohor |
wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim & can_testbench.i_can_top.i_can_bsp.tx_point);
|
| 1744 |
83 |
mohor |
#1 rx = 1;
|
| 1745 |
127 |
mohor |
|
| 1746 |
|
|
// Transmitting acknowledge (for second packet)
|
| 1747 |
|
|
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack & can_testbench.i_can_top.i_can_bsp.tx_point);
|
| 1748 |
|
|
#1 rx = 0;
|
| 1749 |
|
|
wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim & can_testbench.i_can_top.i_can_bsp.tx_point);
|
| 1750 |
|
|
#1 rx = 1;
|
| 1751 |
83 |
mohor |
end
|
| 1752 |
|
|
|
| 1753 |
|
|
|
| 1754 |
|
|
join
|
| 1755 |
|
|
|
| 1756 |
|
|
read_receive_buffer;
|
| 1757 |
|
|
release_rx_buffer_command;
|
| 1758 |
|
|
release_rx_buffer_command;
|
| 1759 |
|
|
read_receive_buffer;
|
| 1760 |
|
|
release_rx_buffer_command;
|
| 1761 |
|
|
read_receive_buffer;
|
| 1762 |
|
|
|
| 1763 |
|
|
#200000;
|
| 1764 |
|
|
|
| 1765 |
|
|
read_receive_buffer;
|
| 1766 |
|
|
|
| 1767 |
|
|
// Read irq register
|
| 1768 |
160 |
igorm |
read_register(8'd3, tmp_data);
|
| 1769 |
83 |
mohor |
#1000;
|
| 1770 |
|
|
|
| 1771 |
|
|
end
|
| 1772 |
|
|
endtask // send_frame_basic
|
| 1773 |
|
|
|
| 1774 |
|
|
|
| 1775 |
|
|
|
| 1776 |
|
|
task send_frame_extended; // CAN IP core sends basic or extended frames in extended mode
|
| 1777 |
|
|
begin
|
| 1778 |
|
|
|
| 1779 |
|
|
// Switch-on reset mode
|
| 1780 |
|
|
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 1781 |
158 |
igorm |
write_register2(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 1782 |
83 |
mohor |
|
| 1783 |
|
|
// Set Clock Divider register
|
| 1784 |
|
|
extended_mode = 1'b1;
|
| 1785 |
|
|
write_register(8'd31, {extended_mode, 7'h0}); // Setting the extended mode
|
| 1786 |
158 |
igorm |
write_register2(8'd31, {extended_mode, 7'h0}); // Setting the extended mode
|
| 1787 |
83 |
mohor |
|
| 1788 |
|
|
// Set Acceptance Code and Acceptance Mask registers
|
| 1789 |
|
|
write_register(8'd16, 8'ha6); // acceptance code 0
|
| 1790 |
|
|
write_register(8'd17, 8'hb0); // acceptance code 1
|
| 1791 |
|
|
write_register(8'd18, 8'h12); // acceptance code 2
|
| 1792 |
|
|
write_register(8'd19, 8'h30); // acceptance code 3
|
| 1793 |
|
|
write_register(8'd20, 8'h00); // acceptance mask 0
|
| 1794 |
|
|
write_register(8'd21, 8'h00); // acceptance mask 1
|
| 1795 |
|
|
write_register(8'd22, 8'h00); // acceptance mask 2
|
| 1796 |
|
|
write_register(8'd23, 8'h00); // acceptance mask 3
|
| 1797 |
|
|
|
| 1798 |
158 |
igorm |
write_register2(8'd16, 8'ha6); // acceptance code 0
|
| 1799 |
|
|
write_register2(8'd17, 8'hb0); // acceptance code 1
|
| 1800 |
|
|
write_register2(8'd18, 8'h12); // acceptance code 2
|
| 1801 |
|
|
write_register2(8'd19, 8'h30); // acceptance code 3
|
| 1802 |
|
|
write_register2(8'd20, 8'h00); // acceptance mask 0
|
| 1803 |
|
|
write_register2(8'd21, 8'h00); // acceptance mask 1
|
| 1804 |
|
|
write_register2(8'd22, 8'h00); // acceptance mask 2
|
| 1805 |
|
|
write_register2(8'd23, 8'h00); // acceptance mask 3
|
| 1806 |
|
|
|
| 1807 |
83 |
mohor |
// Switch-off reset mode
|
| 1808 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 1809 |
158 |
igorm |
write_register2(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 1810 |
83 |
mohor |
|
| 1811 |
|
|
// After exiting the reset mode sending bus free
|
| 1812 |
|
|
repeat (11) send_bit(1);
|
| 1813 |
|
|
|
| 1814 |
|
|
|
| 1815 |
|
|
/* Basic frame format
|
| 1816 |
|
|
// Writing TX frame information + identifier + data
|
| 1817 |
|
|
write_register(8'd16, 8'h45); // Frame format = 0, Remote transmision request = 1, DLC = 5
|
| 1818 |
|
|
write_register(8'd17, 8'ha6); // ID[28:21] = a6
|
| 1819 |
|
|
write_register(8'd18, 8'ha0); // ID[20:18] = 5
|
| 1820 |
|
|
// write_register(8'd19, 8'h78); RTR does not send any data
|
| 1821 |
|
|
// write_register(8'd20, 8'h9a);
|
| 1822 |
|
|
// write_register(8'd21, 8'hbc);
|
| 1823 |
|
|
// write_register(8'd22, 8'hde);
|
| 1824 |
|
|
// write_register(8'd23, 8'hf0);
|
| 1825 |
|
|
// write_register(8'd24, 8'h0f);
|
| 1826 |
|
|
// write_register(8'd25, 8'hed);
|
| 1827 |
|
|
// write_register(8'd26, 8'hcb);
|
| 1828 |
|
|
// write_register(8'd27, 8'ha9);
|
| 1829 |
|
|
// write_register(8'd28, 8'h87);
|
| 1830 |
|
|
*/
|
| 1831 |
|
|
|
| 1832 |
|
|
// Extended frame format
|
| 1833 |
|
|
// Writing TX frame information + identifier + data
|
| 1834 |
|
|
write_register(8'd16, 8'hc5); // Frame format = 1, Remote transmision request = 1, DLC = 5
|
| 1835 |
|
|
write_register(8'd17, 8'ha6); // ID[28:21] = a6
|
| 1836 |
|
|
write_register(8'd18, 8'h00); // ID[20:13] = 00
|
| 1837 |
|
|
write_register(8'd19, 8'h5a); // ID[12:5] = 5a
|
| 1838 |
|
|
write_register(8'd20, 8'ha8); // ID[4:0] = 15
|
| 1839 |
158 |
igorm |
write_register2(8'd16, 8'hc5); // Frame format = 1, Remote transmision request = 1, DLC = 5
|
| 1840 |
|
|
write_register2(8'd17, 8'ha6); // ID[28:21] = a6
|
| 1841 |
|
|
write_register2(8'd18, 8'h00); // ID[20:13] = 00
|
| 1842 |
|
|
write_register2(8'd19, 8'h5a); // ID[12:5] = 5a
|
| 1843 |
|
|
write_register2(8'd20, 8'ha8); // ID[4:0] = 15
|
| 1844 |
83 |
mohor |
// write_register(8'd21, 8'h78); RTR does not send any data
|
| 1845 |
|
|
// write_register(8'd22, 8'h9a);
|
| 1846 |
|
|
// write_register(8'd23, 8'hbc);
|
| 1847 |
|
|
// write_register(8'd24, 8'hde);
|
| 1848 |
|
|
// write_register(8'd25, 8'hf0);
|
| 1849 |
|
|
// write_register(8'd26, 8'h0f);
|
| 1850 |
|
|
// write_register(8'd27, 8'hed);
|
| 1851 |
|
|
// write_register(8'd28, 8'hcb);
|
| 1852 |
|
|
|
| 1853 |
|
|
|
| 1854 |
|
|
// Enabling IRQ's (extended mode)
|
| 1855 |
|
|
write_register(8'd4, 8'hff);
|
| 1856 |
158 |
igorm |
write_register2(8'd4, 8'hff);
|
| 1857 |
83 |
mohor |
|
| 1858 |
|
|
|
| 1859 |
|
|
fork
|
| 1860 |
|
|
begin
|
| 1861 |
158 |
igorm |
#1251;
|
| 1862 |
83 |
mohor |
$display("\n\nStart receiving data from CAN bus");
|
| 1863 |
|
|
/* Standard frame format
|
| 1864 |
|
|
receive_frame(0, 0, {26'h00000a0, 3'h1}, 4'h1, 15'h2d9c); // mode, rtr, id, length, crc
|
| 1865 |
|
|
receive_frame(0, 0, {26'h00000a0, 3'h1}, 4'h2, 15'h46b4); // mode, rtr, id, length, crc
|
| 1866 |
|
|
receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h0, 15'h42cd); // mode, rtr, id, length, crc
|
| 1867 |
|
|
receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h1, 15'h555f); // mode, rtr, id, length, crc
|
| 1868 |
|
|
receive_frame(0, 0, {26'h00000af, 3'h1}, 4'h2, 15'h6742); // mode, rtr, id, length, crc
|
| 1869 |
|
|
*/
|
| 1870 |
|
|
|
| 1871 |
|
|
// Extended frame format
|
| 1872 |
158 |
igorm |
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h14}, 4'h1, 15'h1528); // mode, rtr, id, length, crc
|
| 1873 |
83 |
mohor |
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h2, 15'h3d2d); // mode, rtr, id, length, crc
|
| 1874 |
|
|
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h0, 15'h23aa); // mode, rtr, id, length, crc
|
| 1875 |
|
|
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h1, 15'h2d22); // mode, rtr, id, length, crc
|
| 1876 |
|
|
receive_frame(1, 0, {8'ha6, 8'h00, 8'h5a, 5'h15}, 4'h2, 15'h3d2d); // mode, rtr, id, length, crc
|
| 1877 |
|
|
|
| 1878 |
|
|
end
|
| 1879 |
|
|
|
| 1880 |
|
|
begin
|
| 1881 |
|
|
tx_request_command;
|
| 1882 |
|
|
end
|
| 1883 |
|
|
|
| 1884 |
|
|
begin
|
| 1885 |
|
|
// Transmitting acknowledge
|
| 1886 |
127 |
mohor |
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack & can_testbench.i_can_top.i_can_bsp.tx_point);
|
| 1887 |
83 |
mohor |
#1 rx = 0;
|
| 1888 |
127 |
mohor |
wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim & can_testbench.i_can_top.i_can_bsp.tx_point);
|
| 1889 |
83 |
mohor |
#1 rx = 1;
|
| 1890 |
|
|
end
|
| 1891 |
|
|
|
| 1892 |
|
|
begin // Reading irq and arbitration lost capture register
|
| 1893 |
|
|
|
| 1894 |
|
|
repeat(1)
|
| 1895 |
|
|
begin
|
| 1896 |
|
|
while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
|
| 1897 |
|
|
begin
|
| 1898 |
|
|
@ (posedge clk);
|
| 1899 |
|
|
end
|
| 1900 |
|
|
|
| 1901 |
|
|
// Read irq register
|
| 1902 |
160 |
igorm |
#1 read_register(8'd3, tmp_data);
|
| 1903 |
83 |
mohor |
|
| 1904 |
|
|
// Read arbitration lost capture register
|
| 1905 |
160 |
igorm |
read_register(8'd11, tmp_data);
|
| 1906 |
83 |
mohor |
end
|
| 1907 |
|
|
|
| 1908 |
|
|
|
| 1909 |
|
|
repeat(1)
|
| 1910 |
|
|
begin
|
| 1911 |
|
|
while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
|
| 1912 |
|
|
begin
|
| 1913 |
|
|
@ (posedge clk);
|
| 1914 |
|
|
end
|
| 1915 |
|
|
|
| 1916 |
|
|
// Read irq register
|
| 1917 |
160 |
igorm |
#1 read_register(8'd3, tmp_data);
|
| 1918 |
83 |
mohor |
end
|
| 1919 |
|
|
|
| 1920 |
|
|
repeat(1)
|
| 1921 |
|
|
begin
|
| 1922 |
|
|
while (~(can_testbench.i_can_top.i_can_bsp.rx_crc_lim & can_testbench.i_can_top.i_can_bsp.sample_point))
|
| 1923 |
|
|
begin
|
| 1924 |
|
|
@ (posedge clk);
|
| 1925 |
|
|
end
|
| 1926 |
|
|
|
| 1927 |
|
|
// Read arbitration lost capture register
|
| 1928 |
160 |
igorm |
read_register(8'd11, tmp_data);
|
| 1929 |
83 |
mohor |
end
|
| 1930 |
|
|
|
| 1931 |
|
|
end
|
| 1932 |
|
|
|
| 1933 |
158 |
igorm |
begin
|
| 1934 |
|
|
# 344000;
|
| 1935 |
|
|
|
| 1936 |
|
|
// Switch-on reset mode
|
| 1937 |
|
|
$display("expect: SW reset ON\n");
|
| 1938 |
|
|
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 1939 |
|
|
|
| 1940 |
|
|
#40000;
|
| 1941 |
|
|
// Switch-off reset mode
|
| 1942 |
|
|
$display("expect: SW reset OFF\n");
|
| 1943 |
|
|
write_register(8'd0, {7'h0, (~`CAN_MODE_RESET)});
|
| 1944 |
|
|
end
|
| 1945 |
|
|
|
| 1946 |
83 |
mohor |
join
|
| 1947 |
|
|
|
| 1948 |
|
|
read_receive_buffer;
|
| 1949 |
|
|
release_rx_buffer_command;
|
| 1950 |
|
|
release_rx_buffer_command;
|
| 1951 |
|
|
read_receive_buffer;
|
| 1952 |
|
|
release_rx_buffer_command;
|
| 1953 |
|
|
read_receive_buffer;
|
| 1954 |
|
|
release_rx_buffer_command;
|
| 1955 |
|
|
read_receive_buffer;
|
| 1956 |
|
|
release_rx_buffer_command;
|
| 1957 |
|
|
read_receive_buffer;
|
| 1958 |
|
|
|
| 1959 |
|
|
#200000;
|
| 1960 |
|
|
|
| 1961 |
|
|
read_receive_buffer;
|
| 1962 |
|
|
|
| 1963 |
|
|
// Read irq register
|
| 1964 |
160 |
igorm |
read_register(8'd3, tmp_data);
|
| 1965 |
83 |
mohor |
#1000;
|
| 1966 |
|
|
|
| 1967 |
|
|
end
|
| 1968 |
|
|
endtask // send_frame_extended
|
| 1969 |
|
|
|
| 1970 |
|
|
|
| 1971 |
|
|
|
| 1972 |
|
|
task self_reception_request; // CAN IP core sends sets self reception mode and transmits a msg. This test runs in EXTENDED mode
|
| 1973 |
|
|
begin
|
| 1974 |
|
|
|
| 1975 |
|
|
// Switch-on reset mode
|
| 1976 |
|
|
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
| 1977 |
|
|
|
| 1978 |
|
|
// Set Clock Divider register
|
| 1979 |
|
|
extended_mode = 1'b1;
|
| 1980 |
|
|
write_register(8'd31, {extended_mode, 7'h0}); // Setting the extended mode
|
| 1981 |
|
|
|
| 1982 |
|
|
// Set Acceptance Code and Acceptance Mask registers
|
| 1983 |
|
|
write_register(8'd16, 8'ha6); // acceptance code 0
|
| 1984 |
|
|
write_register(8'd17, 8'hb0); // acceptance code 1
|
| 1985 |
|
|
write_register(8'd18, 8'h12); // acceptance code 2
|
| 1986 |
|
|
write_register(8'd19, 8'h30); // acceptance code 3
|
| 1987 |
|
|
write_register(8'd20, 8'h00); // acceptance mask 0
|
| 1988 |
|
|
write_register(8'd21, 8'h00); // acceptance mask 1
|
| 1989 |
|
|
write_register(8'd22, 8'h00); // acceptance mask 2
|
| 1990 |
|
|
write_register(8'd23, 8'h00); // acceptance mask 3
|
| 1991 |
|
|
|
| 1992 |
|
|
// Setting the "self test mode"
|
| 1993 |
|
|
write_register(8'd0, 8'h4);
|
| 1994 |
|
|
|
| 1995 |
|
|
// Switch-off reset mode
|
| 1996 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 1997 |
|
|
|
| 1998 |
|
|
// After exiting the reset mode sending bus free
|
| 1999 |
|
|
repeat (11) send_bit(1);
|
| 2000 |
|
|
|
| 2001 |
|
|
|
| 2002 |
|
|
// Writing TX frame information + identifier + data
|
| 2003 |
|
|
write_register(8'd16, 8'h45); // Frame format = 0, Remote transmision request = 1, DLC = 5
|
| 2004 |
|
|
write_register(8'd17, 8'ha6); // ID[28:21] = a6
|
| 2005 |
|
|
write_register(8'd18, 8'ha0); // ID[20:18] = 5
|
| 2006 |
|
|
// write_register(8'd19, 8'h78); RTR does not send any data
|
| 2007 |
|
|
// write_register(8'd20, 8'h9a);
|
| 2008 |
|
|
// write_register(8'd21, 8'hbc);
|
| 2009 |
|
|
// write_register(8'd22, 8'hde);
|
| 2010 |
|
|
// write_register(8'd23, 8'hf0);
|
| 2011 |
|
|
// write_register(8'd24, 8'h0f);
|
| 2012 |
|
|
// write_register(8'd25, 8'hed);
|
| 2013 |
|
|
// write_register(8'd26, 8'hcb);
|
| 2014 |
|
|
// write_register(8'd27, 8'ha9);
|
| 2015 |
|
|
// write_register(8'd28, 8'h87);
|
| 2016 |
|
|
|
| 2017 |
|
|
|
| 2018 |
|
|
// Enabling IRQ's (extended mode)
|
| 2019 |
|
|
write_register(8'd4, 8'hff);
|
| 2020 |
|
|
|
| 2021 |
|
|
self_reception_request_command;
|
| 2022 |
|
|
|
| 2023 |
|
|
#400000;
|
| 2024 |
|
|
|
| 2025 |
|
|
read_receive_buffer;
|
| 2026 |
|
|
release_rx_buffer_command;
|
| 2027 |
|
|
release_rx_buffer_command;
|
| 2028 |
|
|
read_receive_buffer;
|
| 2029 |
|
|
release_rx_buffer_command;
|
| 2030 |
|
|
read_receive_buffer;
|
| 2031 |
|
|
release_rx_buffer_command;
|
| 2032 |
|
|
read_receive_buffer;
|
| 2033 |
|
|
release_rx_buffer_command;
|
| 2034 |
|
|
read_receive_buffer;
|
| 2035 |
|
|
|
| 2036 |
|
|
|
| 2037 |
|
|
read_receive_buffer;
|
| 2038 |
|
|
|
| 2039 |
|
|
// Read irq register
|
| 2040 |
160 |
igorm |
read_register(8'd3, tmp_data);
|
| 2041 |
83 |
mohor |
#1000;
|
| 2042 |
|
|
|
| 2043 |
|
|
end
|
| 2044 |
|
|
endtask // self_reception_request
|
| 2045 |
|
|
|
| 2046 |
|
|
|
| 2047 |
|
|
|
| 2048 |
|
|
task test_empty_fifo;
|
| 2049 |
|
|
begin
|
| 2050 |
|
|
|
| 2051 |
|
|
// Enable irqs (basic mode)
|
| 2052 |
|
|
write_register(8'd0, 8'h1e);
|
| 2053 |
|
|
|
| 2054 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h3, 15'h56a9); // mode, rtr, id, length, crc
|
| 2055 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h7, 15'h391d); // mode, rtr, id, length, crc
|
| 2056 |
|
|
|
| 2057 |
|
|
read_receive_buffer;
|
| 2058 |
|
|
fifo_info;
|
| 2059 |
|
|
|
| 2060 |
|
|
release_rx_buffer_command;
|
| 2061 |
|
|
$display("\n\n");
|
| 2062 |
|
|
read_receive_buffer;
|
| 2063 |
|
|
fifo_info;
|
| 2064 |
|
|
|
| 2065 |
|
|
release_rx_buffer_command;
|
| 2066 |
|
|
$display("\n\n");
|
| 2067 |
|
|
read_receive_buffer;
|
| 2068 |
|
|
fifo_info;
|
| 2069 |
|
|
|
| 2070 |
|
|
release_rx_buffer_command;
|
| 2071 |
|
|
$display("\n\n");
|
| 2072 |
|
|
read_receive_buffer;
|
| 2073 |
|
|
fifo_info;
|
| 2074 |
|
|
|
| 2075 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
| 2076 |
|
|
|
| 2077 |
|
|
$display("\n\n");
|
| 2078 |
|
|
read_receive_buffer;
|
| 2079 |
|
|
fifo_info;
|
| 2080 |
|
|
|
| 2081 |
|
|
release_rx_buffer_command;
|
| 2082 |
|
|
$display("\n\n");
|
| 2083 |
|
|
read_receive_buffer;
|
| 2084 |
|
|
fifo_info;
|
| 2085 |
|
|
|
| 2086 |
|
|
release_rx_buffer_command;
|
| 2087 |
|
|
$display("\n\n");
|
| 2088 |
|
|
read_receive_buffer;
|
| 2089 |
|
|
fifo_info;
|
| 2090 |
|
|
end
|
| 2091 |
|
|
endtask
|
| 2092 |
|
|
|
| 2093 |
|
|
|
| 2094 |
|
|
|
| 2095 |
|
|
task test_empty_fifo_ext;
|
| 2096 |
|
|
begin
|
| 2097 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
|
| 2098 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
|
| 2099 |
|
|
|
| 2100 |
|
|
read_receive_buffer;
|
| 2101 |
|
|
fifo_info;
|
| 2102 |
|
|
|
| 2103 |
|
|
release_rx_buffer_command;
|
| 2104 |
|
|
$display("\n\n");
|
| 2105 |
|
|
read_receive_buffer;
|
| 2106 |
|
|
fifo_info;
|
| 2107 |
|
|
|
| 2108 |
|
|
release_rx_buffer_command;
|
| 2109 |
|
|
$display("\n\n");
|
| 2110 |
|
|
read_receive_buffer;
|
| 2111 |
|
|
fifo_info;
|
| 2112 |
|
|
|
| 2113 |
|
|
release_rx_buffer_command;
|
| 2114 |
|
|
$display("\n\n");
|
| 2115 |
|
|
read_receive_buffer;
|
| 2116 |
|
|
fifo_info;
|
| 2117 |
|
|
|
| 2118 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
|
| 2119 |
|
|
|
| 2120 |
|
|
$display("\n\n");
|
| 2121 |
|
|
read_receive_buffer;
|
| 2122 |
|
|
fifo_info;
|
| 2123 |
|
|
|
| 2124 |
|
|
release_rx_buffer_command;
|
| 2125 |
|
|
$display("\n\n");
|
| 2126 |
|
|
read_receive_buffer;
|
| 2127 |
|
|
fifo_info;
|
| 2128 |
|
|
|
| 2129 |
|
|
release_rx_buffer_command;
|
| 2130 |
|
|
$display("\n\n");
|
| 2131 |
|
|
read_receive_buffer;
|
| 2132 |
|
|
fifo_info;
|
| 2133 |
|
|
end
|
| 2134 |
|
|
endtask
|
| 2135 |
|
|
|
| 2136 |
|
|
|
| 2137 |
|
|
|
| 2138 |
|
|
task test_full_fifo;
|
| 2139 |
|
|
begin
|
| 2140 |
|
|
|
| 2141 |
|
|
// Enable irqs (basic mode)
|
| 2142 |
158 |
igorm |
// write_register(8'd0, 8'h1e);
|
| 2143 |
|
|
write_register(8'd0, 8'h10); // enable only overrun irq
|
| 2144 |
83 |
mohor |
|
| 2145 |
|
|
$display("\n\n");
|
| 2146 |
|
|
|
| 2147 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
|
| 2148 |
|
|
fifo_info;
|
| 2149 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
|
| 2150 |
|
|
fifo_info;
|
| 2151 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
|
| 2152 |
|
|
fifo_info;
|
| 2153 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h3, 15'h56a9); // mode, rtr, id, length, crc
|
| 2154 |
|
|
fifo_info;
|
| 2155 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h4, 15'h3124); // mode, rtr, id, length, crc
|
| 2156 |
|
|
fifo_info;
|
| 2157 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h5, 15'h6944); // mode, rtr, id, length, crc
|
| 2158 |
|
|
fifo_info;
|
| 2159 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h6, 15'h5182); // mode, rtr, id, length, crc
|
| 2160 |
|
|
fifo_info;
|
| 2161 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h7, 15'h391d); // mode, rtr, id, length, crc
|
| 2162 |
|
|
fifo_info;
|
| 2163 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
| 2164 |
|
|
fifo_info;
|
| 2165 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
| 2166 |
|
|
fifo_info;
|
| 2167 |
|
|
$display("FIFO should be full now");
|
| 2168 |
158 |
igorm |
$display("2 packets won't be received because of the overrun. IRQ should be set");
|
| 2169 |
83 |
mohor |
|
| 2170 |
|
|
// Following one is accepted with overrun
|
| 2171 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
| 2172 |
|
|
fifo_info;
|
| 2173 |
|
|
|
| 2174 |
158 |
igorm |
// Following one is accepted with overrun
|
| 2175 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
| 2176 |
|
|
fifo_info;
|
| 2177 |
|
|
|
| 2178 |
|
|
$display("Now we'll release 1 packet.");
|
| 2179 |
83 |
mohor |
release_rx_buffer_command;
|
| 2180 |
|
|
fifo_info;
|
| 2181 |
|
|
|
| 2182 |
|
|
// Space just enough for the following frame.
|
| 2183 |
158 |
igorm |
$display("Getting 1 small packet (just big enough). Fifo is full again");
|
| 2184 |
83 |
mohor |
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
|
| 2185 |
|
|
fifo_info;
|
| 2186 |
|
|
|
| 2187 |
|
|
// Following accepted with overrun
|
| 2188 |
158 |
igorm |
$display("1 packets won't be received because of the overrun. IRQ should be set");
|
| 2189 |
83 |
mohor |
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
| 2190 |
|
|
fifo_info;
|
| 2191 |
158 |
igorm |
|
| 2192 |
|
|
// Following accepted with overrun
|
| 2193 |
|
|
$display("1 packets won't be received because of the overrun. IRQ should be set");
|
| 2194 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
| 2195 |
|
|
fifo_info;
|
| 2196 |
83 |
mohor |
// read_overrun_info(0, 15);
|
| 2197 |
|
|
|
| 2198 |
158 |
igorm |
$display("Releasing 3 packets.");
|
| 2199 |
83 |
mohor |
release_rx_buffer_command;
|
| 2200 |
|
|
release_rx_buffer_command;
|
| 2201 |
|
|
|
| 2202 |
|
|
release_rx_buffer_command;
|
| 2203 |
|
|
read_receive_buffer;
|
| 2204 |
|
|
fifo_info;
|
| 2205 |
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
| 2206 |
|
|
fifo_info;
|
| 2207 |
|
|
// read_overrun_info(0, 15);
|
| 2208 |
|
|
$display("\n\n");
|
| 2209 |
|
|
|
| 2210 |
|
|
release_rx_buffer_command;
|
| 2211 |
|
|
read_receive_buffer;
|
| 2212 |
|
|
fifo_info;
|
| 2213 |
|
|
|
| 2214 |
|
|
release_rx_buffer_command;
|
| 2215 |
|
|
read_receive_buffer;
|
| 2216 |
|
|
fifo_info;
|
| 2217 |
|
|
|
| 2218 |
|
|
release_rx_buffer_command;
|
| 2219 |
|
|
read_receive_buffer;
|
| 2220 |
|
|
fifo_info;
|
| 2221 |
|
|
|
| 2222 |
|
|
release_rx_buffer_command;
|
| 2223 |
|
|
read_receive_buffer;
|
| 2224 |
|
|
fifo_info;
|
| 2225 |
|
|
|
| 2226 |
|
|
release_rx_buffer_command;
|
| 2227 |
|
|
read_receive_buffer;
|
| 2228 |
|
|
fifo_info;
|
| 2229 |
|
|
|
| 2230 |
|
|
release_rx_buffer_command;
|
| 2231 |
|
|
read_receive_buffer;
|
| 2232 |
|
|
fifo_info;
|
| 2233 |
|
|
|
| 2234 |
|
|
clear_data_overrun_command;
|
| 2235 |
|
|
|
| 2236 |
|
|
release_rx_buffer_command;
|
| 2237 |
|
|
read_receive_buffer;
|
| 2238 |
|
|
fifo_info;
|
| 2239 |
|
|
|
| 2240 |
|
|
release_rx_buffer_command;
|
| 2241 |
|
|
read_receive_buffer;
|
| 2242 |
|
|
fifo_info;
|
| 2243 |
|
|
|
| 2244 |
|
|
clear_data_overrun_command;
|
| 2245 |
|
|
|
| 2246 |
|
|
release_rx_buffer_command;
|
| 2247 |
|
|
read_receive_buffer;
|
| 2248 |
|
|
fifo_info;
|
| 2249 |
|
|
|
| 2250 |
|
|
release_rx_buffer_command;
|
| 2251 |
|
|
read_receive_buffer;
|
| 2252 |
|
|
fifo_info;
|
| 2253 |
|
|
|
| 2254 |
|
|
release_rx_buffer_command;
|
| 2255 |
|
|
read_receive_buffer;
|
| 2256 |
|
|
fifo_info;
|
| 2257 |
|
|
|
| 2258 |
|
|
release_rx_buffer_command;
|
| 2259 |
|
|
read_receive_buffer;
|
| 2260 |
|
|
fifo_info;
|
| 2261 |
|
|
|
| 2262 |
|
|
release_rx_buffer_command;
|
| 2263 |
|
|
read_receive_buffer;
|
| 2264 |
|
|
fifo_info;
|
| 2265 |
|
|
|
| 2266 |
|
|
// Read irq register
|
| 2267 |
160 |
igorm |
read_register(8'd3, tmp_data);
|
| 2268 |
83 |
mohor |
|
| 2269 |
|
|
// Read irq register
|
| 2270 |
160 |
igorm |
read_register(8'd3, tmp_data);
|
| 2271 |
83 |
mohor |
#1000;
|
| 2272 |
|
|
|
| 2273 |
|
|
end
|
| 2274 |
|
|
endtask
|
| 2275 |
|
|
|
| 2276 |
|
|
|
| 2277 |
|
|
|
| 2278 |
|
|
task test_full_fifo_ext;
|
| 2279 |
|
|
begin
|
| 2280 |
|
|
release_rx_buffer_command;
|
| 2281 |
|
|
$display("\n\n");
|
| 2282 |
|
|
read_receive_buffer;
|
| 2283 |
|
|
fifo_info;
|
| 2284 |
|
|
|
| 2285 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h0, 15'h6f54); // mode, rtr, id, length, crc
|
| 2286 |
|
|
read_receive_buffer;
|
| 2287 |
|
|
fifo_info;
|
| 2288 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h1, 15'h6d38); // mode, rtr, id, length, crc
|
| 2289 |
|
|
read_receive_buffer;
|
| 2290 |
|
|
fifo_info;
|
| 2291 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h2, 15'h053e); // mode, rtr, id, length, crc
|
| 2292 |
|
|
fifo_info;
|
| 2293 |
|
|
read_receive_buffer;
|
| 2294 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
|
| 2295 |
|
|
fifo_info;
|
| 2296 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h4, 15'h4bba); // mode, rtr, id, length, crc
|
| 2297 |
|
|
fifo_info;
|
| 2298 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h5, 15'h4d7d); // mode, rtr, id, length, crc
|
| 2299 |
|
|
fifo_info;
|
| 2300 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h6, 15'h6f40); // mode, rtr, id, length, crc
|
| 2301 |
|
|
fifo_info;
|
| 2302 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
|
| 2303 |
|
|
fifo_info;
|
| 2304 |
|
|
// read_overrun_info(0, 10);
|
| 2305 |
|
|
|
| 2306 |
|
|
release_rx_buffer_command;
|
| 2307 |
|
|
release_rx_buffer_command;
|
| 2308 |
|
|
fifo_info;
|
| 2309 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
|
| 2310 |
|
|
fifo_info;
|
| 2311 |
|
|
// read_overrun_info(0, 15);
|
| 2312 |
|
|
$display("\n\n");
|
| 2313 |
|
|
|
| 2314 |
|
|
release_rx_buffer_command;
|
| 2315 |
|
|
read_receive_buffer;
|
| 2316 |
|
|
fifo_info;
|
| 2317 |
|
|
|
| 2318 |
|
|
release_rx_buffer_command;
|
| 2319 |
|
|
read_receive_buffer;
|
| 2320 |
|
|
fifo_info;
|
| 2321 |
|
|
|
| 2322 |
|
|
release_rx_buffer_command;
|
| 2323 |
|
|
read_receive_buffer;
|
| 2324 |
|
|
fifo_info;
|
| 2325 |
|
|
|
| 2326 |
|
|
release_rx_buffer_command;
|
| 2327 |
|
|
read_receive_buffer;
|
| 2328 |
|
|
fifo_info;
|
| 2329 |
|
|
|
| 2330 |
|
|
release_rx_buffer_command;
|
| 2331 |
|
|
read_receive_buffer;
|
| 2332 |
|
|
fifo_info;
|
| 2333 |
|
|
|
| 2334 |
|
|
release_rx_buffer_command;
|
| 2335 |
|
|
read_receive_buffer;
|
| 2336 |
|
|
fifo_info;
|
| 2337 |
|
|
|
| 2338 |
|
|
release_rx_buffer_command;
|
| 2339 |
|
|
read_receive_buffer;
|
| 2340 |
|
|
fifo_info;
|
| 2341 |
|
|
|
| 2342 |
|
|
end
|
| 2343 |
|
|
endtask
|
| 2344 |
|
|
|
| 2345 |
|
|
|
| 2346 |
158 |
igorm |
task test_reset_mode;
|
| 2347 |
|
|
begin
|
| 2348 |
|
|
release_rx_buffer_command;
|
| 2349 |
|
|
$display("\n\n");
|
| 2350 |
|
|
read_receive_buffer;
|
| 2351 |
|
|
fifo_info;
|
| 2352 |
|
|
$display("expect: Until now no data was received\n");
|
| 2353 |
|
|
|
| 2354 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h0, 15'h6f54); // mode, rtr, id, length, crc
|
| 2355 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h1, 15'h6d38); // mode, rtr, id, length, crc
|
| 2356 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h2, 15'h053e); // mode, rtr, id, length, crc
|
| 2357 |
|
|
|
| 2358 |
|
|
fifo_info;
|
| 2359 |
|
|
read_receive_buffer;
|
| 2360 |
|
|
$display("expect: 3 packets should be received (totally 18 bytes)\n");
|
| 2361 |
|
|
|
| 2362 |
|
|
release_rx_buffer_command;
|
| 2363 |
|
|
fifo_info;
|
| 2364 |
|
|
read_receive_buffer;
|
| 2365 |
|
|
$display("expect: 2 packets should be received (totally 13 bytes)\n");
|
| 2366 |
|
|
|
| 2367 |
|
|
|
| 2368 |
|
|
$display("expect: SW reset performed\n");
|
| 2369 |
|
|
|
| 2370 |
|
|
// Switch-on reset mode
|
| 2371 |
|
|
write_register(8'd0, {7'h0, `CAN_MODE_RESET});
|
| 2372 |
|
|
|
| 2373 |
|
|
// Switch-off reset mode
|
| 2374 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 2375 |
|
|
|
| 2376 |
|
|
fifo_info;
|
| 2377 |
|
|
read_receive_buffer;
|
| 2378 |
|
|
$display("expect: The above read was after the SW reset.\n");
|
| 2379 |
|
|
|
| 2380 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc
|
| 2381 |
|
|
fifo_info;
|
| 2382 |
|
|
read_receive_buffer;
|
| 2383 |
|
|
$display("expect: 1 packets should be received (totally 8 bytes). See above.\n");
|
| 2384 |
|
|
|
| 2385 |
|
|
// Switch-on reset mode
|
| 2386 |
|
|
$display("expect: SW reset ON\n");
|
| 2387 |
|
|
write_register(8'd0, {7'h0, `CAN_MODE_RESET});
|
| 2388 |
|
|
|
| 2389 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h5, 15'h4d7d); // mode, rtr, id, length, crc
|
| 2390 |
|
|
|
| 2391 |
|
|
fifo_info;
|
| 2392 |
|
|
read_receive_buffer;
|
| 2393 |
|
|
$display("expect: 0 packets should be received because we are in reset. (totally 0 bytes). See above.\n");
|
| 2394 |
|
|
|
| 2395 |
83 |
mohor |
/*
|
| 2396 |
158 |
igorm |
fork
|
| 2397 |
|
|
begin
|
| 2398 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h4, 15'h4bba); // mode, rtr, id, length, crc
|
| 2399 |
|
|
end
|
| 2400 |
|
|
begin
|
| 2401 |
|
|
// Switch-on reset mode
|
| 2402 |
|
|
write_register(8'd0, {7'h0, `CAN_MODE_RESET});
|
| 2403 |
|
|
|
| 2404 |
|
|
// Switch-off reset mode
|
| 2405 |
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
| 2406 |
|
|
|
| 2407 |
|
|
|
| 2408 |
|
|
end
|
| 2409 |
|
|
|
| 2410 |
|
|
join
|
| 2411 |
|
|
*/
|
| 2412 |
|
|
|
| 2413 |
|
|
|
| 2414 |
|
|
|
| 2415 |
|
|
|
| 2416 |
|
|
fifo_info;
|
| 2417 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h5, 15'h4d7d); // mode, rtr, id, length, crc
|
| 2418 |
|
|
fifo_info;
|
| 2419 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h6, 15'h6f40); // mode, rtr, id, length, crc
|
| 2420 |
|
|
fifo_info;
|
| 2421 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
|
| 2422 |
|
|
fifo_info;
|
| 2423 |
|
|
// read_overrun_info(0, 10);
|
| 2424 |
|
|
|
| 2425 |
|
|
release_rx_buffer_command;
|
| 2426 |
|
|
release_rx_buffer_command;
|
| 2427 |
|
|
fifo_info;
|
| 2428 |
|
|
|
| 2429 |
|
|
|
| 2430 |
|
|
|
| 2431 |
|
|
// Switch-off reset mode
|
| 2432 |
|
|
$display("expect: SW reset OFF\n");
|
| 2433 |
|
|
write_register(8'd0, {7'h0, (~`CAN_MODE_RESET)});
|
| 2434 |
|
|
|
| 2435 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
|
| 2436 |
|
|
fifo_info;
|
| 2437 |
|
|
read_receive_buffer;
|
| 2438 |
|
|
$display("expect: 1 packets should be received (totally 13 bytes). See above.\n");
|
| 2439 |
|
|
|
| 2440 |
|
|
release_rx_buffer_command;
|
| 2441 |
|
|
fifo_info;
|
| 2442 |
|
|
read_receive_buffer;
|
| 2443 |
|
|
$display("expect: 0 packets should be received (totally 0 bytes). See above.\n");
|
| 2444 |
|
|
$display("\n\n");
|
| 2445 |
|
|
|
| 2446 |
|
|
|
| 2447 |
|
|
fork
|
| 2448 |
|
|
receive_frame(1, 0, 29'h14d60246, 4'h5, 15'h4d7d); // mode, rtr, id, length, crc
|
| 2449 |
|
|
|
| 2450 |
|
|
begin
|
| 2451 |
|
|
#8000;
|
| 2452 |
|
|
// Switch-off reset mode
|
| 2453 |
|
|
$display("expect: SW reset ON while receiving a packet\n");
|
| 2454 |
|
|
write_register(8'd0, {7'h0, `CAN_MODE_RESET});
|
| 2455 |
|
|
end
|
| 2456 |
|
|
join
|
| 2457 |
|
|
|
| 2458 |
|
|
|
| 2459 |
|
|
read_receive_buffer;
|
| 2460 |
|
|
fifo_info;
|
| 2461 |
|
|
$display("expect: 0 packets should be received (totally 0 bytes) because CAN was in reset. See above.\n");
|
| 2462 |
|
|
|
| 2463 |
|
|
release_rx_buffer_command;
|
| 2464 |
|
|
read_receive_buffer;
|
| 2465 |
|
|
fifo_info;
|
| 2466 |
|
|
|
| 2467 |
|
|
end
|
| 2468 |
|
|
endtask // test_reset_mode
|
| 2469 |
|
|
|
| 2470 |
|
|
|
| 2471 |
|
|
/*
|
| 2472 |
83 |
mohor |
task initialize_fifo;
|
| 2473 |
|
|
integer i;
|
| 2474 |
|
|
begin
|
| 2475 |
|
|
for (i=0; i<32; i=i+1)
|
| 2476 |
|
|
begin
|
| 2477 |
|
|
can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i] = 0;
|
| 2478 |
|
|
can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i] = 0;
|
| 2479 |
|
|
end
|
| 2480 |
|
|
|
| 2481 |
|
|
for (i=0; i<64; i=i+1)
|
| 2482 |
|
|
begin
|
| 2483 |
|
|
can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo[i] = 0;
|
| 2484 |
|
|
end
|
| 2485 |
|
|
|
| 2486 |
|
|
$display("(%0t) Fifo initialized", $time);
|
| 2487 |
|
|
end
|
| 2488 |
|
|
endtask
|
| 2489 |
|
|
*/
|
| 2490 |
|
|
/*
|
| 2491 |
|
|
task read_overrun_info;
|
| 2492 |
|
|
input [4:0] start_addr;
|
| 2493 |
|
|
input [4:0] end_addr;
|
| 2494 |
|
|
integer i;
|
| 2495 |
|
|
begin
|
| 2496 |
|
|
for (i=start_addr; i<=end_addr; i=i+1)
|
| 2497 |
|
|
begin
|
| 2498 |
|
|
$display("len[0x%0x]=0x%0x", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i]);
|
| 2499 |
|
|
$display("overrun[0x%0x]=0x%0x\n", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i]);
|
| 2500 |
|
|
end
|
| 2501 |
|
|
end
|
| 2502 |
|
|
endtask
|
| 2503 |
|
|
*/
|
| 2504 |
|
|
|
| 2505 |
|
|
task fifo_info; // Displaying how many packets and how many bytes are in fifo. Not working when wr_info_pointer is smaller than rd_info_pointer.
|
| 2506 |
|
|
begin
|
| 2507 |
|
|
$display("(%0t) Currently %0d bytes in fifo (%0d packets)", $time, can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_cnt,
|
| 2508 |
|
|
(can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_info_pointer - can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer));
|
| 2509 |
|
|
end
|
| 2510 |
|
|
endtask
|
| 2511 |
|
|
|
| 2512 |
|
|
|
| 2513 |
|
|
task read_register;
|
| 2514 |
|
|
input [7:0] reg_addr;
|
| 2515 |
160 |
igorm |
output [7:0] data;
|
| 2516 |
83 |
mohor |
|
| 2517 |
|
|
`ifdef CAN_WISHBONE_IF
|
| 2518 |
|
|
begin
|
| 2519 |
|
|
wait (wb_free);
|
| 2520 |
|
|
wb_free = 0;
|
| 2521 |
|
|
@ (posedge wb_clk_i);
|
| 2522 |
|
|
#1;
|
| 2523 |
|
|
cs_can = 1;
|
| 2524 |
|
|
wb_adr_i = reg_addr;
|
| 2525 |
|
|
wb_cyc_i = 1;
|
| 2526 |
|
|
wb_stb_i = 1;
|
| 2527 |
|
|
wb_we_i = 0;
|
| 2528 |
|
|
wait (wb_ack_o);
|
| 2529 |
|
|
$display("(%0t) Reading register [%0d] = 0x%0x", $time, wb_adr_i, wb_dat_o);
|
| 2530 |
160 |
igorm |
data = wb_dat_o;
|
| 2531 |
83 |
mohor |
@ (posedge wb_clk_i);
|
| 2532 |
|
|
#1;
|
| 2533 |
|
|
wb_adr_i = 'hz;
|
| 2534 |
|
|
wb_cyc_i = 0;
|
| 2535 |
|
|
wb_stb_i = 0;
|
| 2536 |
|
|
wb_we_i = 'hz;
|
| 2537 |
|
|
cs_can = 0;
|
| 2538 |
|
|
wb_free = 1;
|
| 2539 |
|
|
end
|
| 2540 |
|
|
`else
|
| 2541 |
|
|
begin
|
| 2542 |
|
|
wait (port_free);
|
| 2543 |
|
|
port_free = 0;
|
| 2544 |
|
|
@ (posedge clk);
|
| 2545 |
|
|
#1;
|
| 2546 |
|
|
cs_can = 1;
|
| 2547 |
|
|
@ (negedge clk);
|
| 2548 |
|
|
#1;
|
| 2549 |
|
|
ale_i = 1;
|
| 2550 |
|
|
port_0_en = 1;
|
| 2551 |
|
|
port_0_o = reg_addr;
|
| 2552 |
|
|
@ (negedge clk);
|
| 2553 |
|
|
#1;
|
| 2554 |
|
|
ale_i = 0;
|
| 2555 |
|
|
#90; // 73 - 103 ns
|
| 2556 |
|
|
port_0_en = 0;
|
| 2557 |
|
|
rd_i = 1;
|
| 2558 |
|
|
#158;
|
| 2559 |
|
|
$display("(%0t) Reading register [%0d] = 0x%0x", $time, can_testbench.i_can_top.addr_latched, port_0_i);
|
| 2560 |
160 |
igorm |
data = port_0_i;
|
| 2561 |
83 |
mohor |
#1;
|
| 2562 |
|
|
rd_i = 0;
|
| 2563 |
|
|
cs_can = 0;
|
| 2564 |
|
|
port_free = 1;
|
| 2565 |
|
|
end
|
| 2566 |
|
|
`endif
|
| 2567 |
|
|
endtask
|
| 2568 |
|
|
|
| 2569 |
|
|
|
| 2570 |
|
|
task write_register;
|
| 2571 |
|
|
input [7:0] reg_addr;
|
| 2572 |
|
|
input [7:0] reg_data;
|
| 2573 |
|
|
|
| 2574 |
|
|
`ifdef CAN_WISHBONE_IF
|
| 2575 |
|
|
begin
|
| 2576 |
|
|
wait (wb_free);
|
| 2577 |
|
|
wb_free = 0;
|
| 2578 |
|
|
@ (posedge wb_clk_i);
|
| 2579 |
|
|
#1;
|
| 2580 |
|
|
cs_can = 1;
|
| 2581 |
|
|
wb_adr_i = reg_addr;
|
| 2582 |
|
|
wb_dat_i = reg_data;
|
| 2583 |
|
|
wb_cyc_i = 1;
|
| 2584 |
|
|
wb_stb_i = 1;
|
| 2585 |
|
|
wb_we_i = 1;
|
| 2586 |
|
|
wait (wb_ack_o);
|
| 2587 |
|
|
@ (posedge wb_clk_i);
|
| 2588 |
|
|
#1;
|
| 2589 |
|
|
wb_adr_i = 'hz;
|
| 2590 |
|
|
wb_dat_i = 'hz;
|
| 2591 |
|
|
wb_cyc_i = 0;
|
| 2592 |
|
|
wb_stb_i = 0;
|
| 2593 |
|
|
wb_we_i = 'hz;
|
| 2594 |
|
|
cs_can = 0;
|
| 2595 |
|
|
wb_free = 1;
|
| 2596 |
|
|
end
|
| 2597 |
|
|
`else
|
| 2598 |
|
|
begin
|
| 2599 |
160 |
igorm |
$display("(%0t) Writing register [%0d] with 0x%0x", $time, reg_addr, reg_data);
|
| 2600 |
83 |
mohor |
wait (port_free);
|
| 2601 |
|
|
port_free = 0;
|
| 2602 |
|
|
@ (posedge clk);
|
| 2603 |
|
|
#1;
|
| 2604 |
|
|
cs_can = 1;
|
| 2605 |
|
|
@ (negedge clk);
|
| 2606 |
|
|
#1;
|
| 2607 |
|
|
ale_i = 1;
|
| 2608 |
|
|
port_0_en = 1;
|
| 2609 |
|
|
port_0_o = reg_addr;
|
| 2610 |
|
|
@ (negedge clk);
|
| 2611 |
|
|
#1;
|
| 2612 |
|
|
ale_i = 0;
|
| 2613 |
|
|
#90; // 73 - 103 ns
|
| 2614 |
|
|
port_0_o = reg_data;
|
| 2615 |
|
|
wr_i = 1;
|
| 2616 |
|
|
#158;
|
| 2617 |
|
|
wr_i = 0;
|
| 2618 |
|
|
port_0_en = 0;
|
| 2619 |
|
|
cs_can = 0;
|
| 2620 |
|
|
port_free = 1;
|
| 2621 |
|
|
end
|
| 2622 |
|
|
`endif
|
| 2623 |
|
|
endtask
|
| 2624 |
|
|
|
| 2625 |
|
|
|
| 2626 |
158 |
igorm |
task read_register2;
|
| 2627 |
|
|
input [7:0] reg_addr;
|
| 2628 |
160 |
igorm |
output [7:0] data;
|
| 2629 |
158 |
igorm |
|
| 2630 |
|
|
`ifdef CAN_WISHBONE_IF
|
| 2631 |
|
|
begin
|
| 2632 |
|
|
wait (wb_free);
|
| 2633 |
|
|
wb_free = 0;
|
| 2634 |
|
|
@ (posedge wb_clk_i);
|
| 2635 |
|
|
#1;
|
| 2636 |
|
|
cs_can = 1;
|
| 2637 |
|
|
wb_adr_i = reg_addr;
|
| 2638 |
|
|
wb_cyc_i = 1;
|
| 2639 |
|
|
wb_stb_i = 1;
|
| 2640 |
|
|
wb_we_i = 0;
|
| 2641 |
|
|
wait (wb_ack_o);
|
| 2642 |
|
|
$display("(%0t) Reading register [%0d] = 0x%0x", $time, wb_adr_i, wb_dat_o);
|
| 2643 |
160 |
igorm |
data = wb_dat_o;
|
| 2644 |
158 |
igorm |
@ (posedge wb_clk_i);
|
| 2645 |
|
|
#1;
|
| 2646 |
|
|
wb_adr_i = 'hz;
|
| 2647 |
|
|
wb_cyc_i = 0;
|
| 2648 |
|
|
wb_stb_i = 0;
|
| 2649 |
|
|
wb_we_i = 'hz;
|
| 2650 |
|
|
cs_can = 0;
|
| 2651 |
|
|
wb_free = 1;
|
| 2652 |
|
|
end
|
| 2653 |
|
|
`else
|
| 2654 |
|
|
begin
|
| 2655 |
|
|
wait (port_free);
|
| 2656 |
|
|
port_free = 0;
|
| 2657 |
|
|
@ (posedge clk);
|
| 2658 |
|
|
#1;
|
| 2659 |
|
|
cs_can2 = 1;
|
| 2660 |
|
|
@ (negedge clk);
|
| 2661 |
|
|
#1;
|
| 2662 |
|
|
ale2_i = 1;
|
| 2663 |
|
|
port_0_en = 1;
|
| 2664 |
|
|
port_0_o = reg_addr;
|
| 2665 |
|
|
@ (negedge clk);
|
| 2666 |
|
|
#1;
|
| 2667 |
|
|
ale2_i = 0;
|
| 2668 |
|
|
#90; // 73 - 103 ns
|
| 2669 |
|
|
port_0_en = 0;
|
| 2670 |
|
|
rd2_i = 1;
|
| 2671 |
|
|
#158;
|
| 2672 |
|
|
$display("(%0t) Reading register [%0d] = 0x%0x", $time, can_testbench.i_can_top.addr_latched, port_0_i);
|
| 2673 |
160 |
igorm |
data = port_0_i;
|
| 2674 |
158 |
igorm |
#1;
|
| 2675 |
|
|
rd2_i = 0;
|
| 2676 |
|
|
cs_can2 = 0;
|
| 2677 |
|
|
port_free = 1;
|
| 2678 |
|
|
end
|
| 2679 |
|
|
`endif
|
| 2680 |
|
|
endtask
|
| 2681 |
|
|
|
| 2682 |
|
|
|
| 2683 |
|
|
task write_register2;
|
| 2684 |
|
|
input [7:0] reg_addr;
|
| 2685 |
|
|
input [7:0] reg_data;
|
| 2686 |
|
|
|
| 2687 |
|
|
`ifdef CAN_WISHBONE_IF
|
| 2688 |
|
|
begin
|
| 2689 |
|
|
wait (wb_free);
|
| 2690 |
|
|
wb_free = 0;
|
| 2691 |
|
|
@ (posedge wb_clk_i);
|
| 2692 |
|
|
#1;
|
| 2693 |
|
|
cs_can = 1;
|
| 2694 |
|
|
wb_adr_i = reg_addr;
|
| 2695 |
|
|
wb_dat_i = reg_data;
|
| 2696 |
|
|
wb_cyc_i = 1;
|
| 2697 |
|
|
wb_stb_i = 1;
|
| 2698 |
|
|
wb_we_i = 1;
|
| 2699 |
|
|
wait (wb_ack_o);
|
| 2700 |
|
|
@ (posedge wb_clk_i);
|
| 2701 |
|
|
#1;
|
| 2702 |
|
|
wb_adr_i = 'hz;
|
| 2703 |
|
|
wb_dat_i = 'hz;
|
| 2704 |
|
|
wb_cyc_i = 0;
|
| 2705 |
|
|
wb_stb_i = 0;
|
| 2706 |
|
|
wb_we_i = 'hz;
|
| 2707 |
|
|
cs_can = 0;
|
| 2708 |
|
|
wb_free = 1;
|
| 2709 |
|
|
end
|
| 2710 |
|
|
`else
|
| 2711 |
|
|
begin
|
| 2712 |
|
|
wait (port_free);
|
| 2713 |
|
|
port_free = 0;
|
| 2714 |
|
|
@ (posedge clk);
|
| 2715 |
|
|
#1;
|
| 2716 |
|
|
cs_can2 = 1;
|
| 2717 |
|
|
@ (negedge clk);
|
| 2718 |
|
|
#1;
|
| 2719 |
|
|
ale2_i = 1;
|
| 2720 |
|
|
port_0_en = 1;
|
| 2721 |
|
|
port_0_o = reg_addr;
|
| 2722 |
|
|
@ (negedge clk);
|
| 2723 |
|
|
#1;
|
| 2724 |
|
|
ale2_i = 0;
|
| 2725 |
|
|
#90; // 73 - 103 ns
|
| 2726 |
|
|
port_0_o = reg_data;
|
| 2727 |
|
|
wr2_i = 1;
|
| 2728 |
|
|
#158;
|
| 2729 |
|
|
wr2_i = 0;
|
| 2730 |
|
|
port_0_en = 0;
|
| 2731 |
|
|
cs_can2 = 0;
|
| 2732 |
|
|
port_free = 1;
|
| 2733 |
|
|
end
|
| 2734 |
|
|
`endif
|
| 2735 |
|
|
endtask
|
| 2736 |
|
|
|
| 2737 |
|
|
|
| 2738 |
83 |
mohor |
task read_receive_buffer;
|
| 2739 |
|
|
integer i;
|
| 2740 |
|
|
begin
|
| 2741 |
|
|
$display("\n\n(%0t)", $time);
|
| 2742 |
|
|
if(extended_mode) // Extended mode
|
| 2743 |
|
|
begin
|
| 2744 |
|
|
for (i=8'd16; i<=8'd28; i=i+1)
|
| 2745 |
160 |
igorm |
read_register(i, tmp_data);
|
| 2746 |
158 |
igorm |
//if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun)
|
| 2747 |
|
|
// $display("\nWARNING: Above packet was received with overrun.");
|
| 2748 |
83 |
mohor |
end
|
| 2749 |
|
|
else
|
| 2750 |
|
|
begin
|
| 2751 |
|
|
for (i=8'd20; i<=8'd29; i=i+1)
|
| 2752 |
160 |
igorm |
read_register(i, tmp_data);
|
| 2753 |
158 |
igorm |
//if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun)
|
| 2754 |
|
|
// $display("\nWARNING: Above packet was received with overrun.");
|
| 2755 |
83 |
mohor |
end
|
| 2756 |
|
|
end
|
| 2757 |
|
|
endtask
|
| 2758 |
|
|
|
| 2759 |
|
|
|
| 2760 |
|
|
task release_rx_buffer_command;
|
| 2761 |
|
|
begin
|
| 2762 |
|
|
write_register(8'd1, 8'h4);
|
| 2763 |
|
|
$display("(%0t) Rx buffer released.", $time);
|
| 2764 |
|
|
end
|
| 2765 |
|
|
endtask
|
| 2766 |
|
|
|
| 2767 |
|
|
|
| 2768 |
|
|
task tx_request_command;
|
| 2769 |
|
|
begin
|
| 2770 |
|
|
write_register(8'd1, 8'h1);
|
| 2771 |
|
|
$display("(%0t) Tx requested.", $time);
|
| 2772 |
|
|
end
|
| 2773 |
|
|
endtask
|
| 2774 |
|
|
|
| 2775 |
|
|
|
| 2776 |
|
|
task tx_abort_command;
|
| 2777 |
|
|
begin
|
| 2778 |
|
|
write_register(8'd1, 8'h2);
|
| 2779 |
|
|
$display("(%0t) Tx abort requested.", $time);
|
| 2780 |
|
|
end
|
| 2781 |
|
|
endtask
|
| 2782 |
|
|
|
| 2783 |
|
|
|
| 2784 |
|
|
task clear_data_overrun_command;
|
| 2785 |
|
|
begin
|
| 2786 |
|
|
write_register(8'd1, 8'h8);
|
| 2787 |
|
|
$display("(%0t) Data overrun cleared.", $time);
|
| 2788 |
|
|
end
|
| 2789 |
|
|
endtask
|
| 2790 |
|
|
|
| 2791 |
|
|
|
| 2792 |
|
|
task self_reception_request_command;
|
| 2793 |
|
|
begin
|
| 2794 |
|
|
write_register(8'd1, 8'h10);
|
| 2795 |
|
|
$display("(%0t) Self reception requested.", $time);
|
| 2796 |
|
|
end
|
| 2797 |
|
|
endtask
|
| 2798 |
|
|
|
| 2799 |
|
|
|
| 2800 |
|
|
task test_synchronization;
|
| 2801 |
|
|
begin
|
| 2802 |
|
|
// Hard synchronization
|
| 2803 |
|
|
#1 rx=0;
|
| 2804 |
|
|
repeat (2*BRP) @ (posedge clk);
|
| 2805 |
|
|
repeat (8*BRP) @ (posedge clk);
|
| 2806 |
|
|
#1 rx=1;
|
| 2807 |
|
|
repeat (10*BRP) @ (posedge clk);
|
| 2808 |
|
|
|
| 2809 |
|
|
// Resynchronization on time
|
| 2810 |
|
|
#1 rx=0;
|
| 2811 |
|
|
repeat (10*BRP) @ (posedge clk);
|
| 2812 |
|
|
#1 rx=1;
|
| 2813 |
|
|
repeat (10*BRP) @ (posedge clk);
|
| 2814 |
|
|
|
| 2815 |
|
|
// Resynchronization late
|
| 2816 |
|
|
repeat (BRP) @ (posedge clk);
|
| 2817 |
|
|
repeat (BRP) @ (posedge clk);
|
| 2818 |
|
|
#1 rx=0;
|
| 2819 |
|
|
repeat (10*BRP) @ (posedge clk);
|
| 2820 |
|
|
#1 rx=1;
|
| 2821 |
|
|
|
| 2822 |
|
|
// Resynchronization early
|
| 2823 |
|
|
repeat (8*BRP) @ (posedge clk); // two frames too early
|
| 2824 |
|
|
#1 rx=0;
|
| 2825 |
|
|
repeat (10*BRP) @ (posedge clk);
|
| 2826 |
|
|
#1 rx=1;
|
| 2827 |
127 |
mohor |
// Resynchronization early
|
| 2828 |
|
|
repeat (11*BRP) @ (posedge clk); // one frames too late
|
| 2829 |
|
|
#1 rx=0;
|
| 2830 |
83 |
mohor |
repeat (10*BRP) @ (posedge clk);
|
| 2831 |
127 |
mohor |
#1 rx=1;
|
| 2832 |
|
|
|
| 2833 |
|
|
repeat (10*BRP) @ (posedge clk);
|
| 2834 |
|
|
#1 rx=0;
|
| 2835 |
|
|
repeat (10*BRP) @ (posedge clk);
|
| 2836 |
83 |
mohor |
end
|
| 2837 |
|
|
endtask
|
| 2838 |
|
|
|
| 2839 |
|
|
|
| 2840 |
|
|
task send_bit;
|
| 2841 |
|
|
input bit;
|
| 2842 |
|
|
integer cnt;
|
| 2843 |
|
|
begin
|
| 2844 |
|
|
#1 rx=bit;
|
| 2845 |
|
|
repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
|
| 2846 |
|
|
end
|
| 2847 |
|
|
endtask
|
| 2848 |
|
|
|
| 2849 |
|
|
|
| 2850 |
|
|
task receive_frame; // CAN IP core receives frames
|
| 2851 |
|
|
input mode;
|
| 2852 |
|
|
input remote_trans_req;
|
| 2853 |
|
|
input [28:0] id;
|
| 2854 |
|
|
input [3:0] length;
|
| 2855 |
|
|
input [14:0] crc;
|
| 2856 |
|
|
|
| 2857 |
|
|
reg [117:0] data;
|
| 2858 |
|
|
reg previous_bit;
|
| 2859 |
|
|
reg stuff;
|
| 2860 |
|
|
reg tmp;
|
| 2861 |
|
|
reg arbitration_lost;
|
| 2862 |
|
|
integer pointer;
|
| 2863 |
|
|
integer cnt;
|
| 2864 |
|
|
integer total_bits;
|
| 2865 |
|
|
integer stuff_cnt;
|
| 2866 |
|
|
|
| 2867 |
|
|
begin
|
| 2868 |
|
|
|
| 2869 |
|
|
stuff_cnt = 1;
|
| 2870 |
|
|
stuff = 0;
|
| 2871 |
|
|
|
| 2872 |
|
|
if(mode) // Extended format
|
| 2873 |
|
|
data = {id[28:18], 1'b1, 1'b1, id[17:0], remote_trans_req, 2'h0, length};
|
| 2874 |
|
|
else // Standard format
|
| 2875 |
|
|
data = {id[10:0], remote_trans_req, 1'b0, 1'b0, length};
|
| 2876 |
|
|
|
| 2877 |
|
|
if (~remote_trans_req)
|
| 2878 |
|
|
begin
|
| 2879 |
|
|
if(length) // Send data if length is > 0
|
| 2880 |
|
|
begin
|
| 2881 |
|
|
for (cnt=1; cnt<=(2*length); cnt=cnt+1) // data (we are sending nibbles)
|
| 2882 |
|
|
data = {data[113:0], cnt[3:0]};
|
| 2883 |
|
|
end
|
| 2884 |
|
|
end
|
| 2885 |
|
|
|
| 2886 |
|
|
// Adding CRC
|
| 2887 |
|
|
data = {data[104:0], crc[14:0]};
|
| 2888 |
|
|
|
| 2889 |
|
|
|
| 2890 |
|
|
// Calculating pointer that points to the bit that will be send
|
| 2891 |
|
|
if (remote_trans_req)
|
| 2892 |
|
|
begin
|
| 2893 |
|
|
if(mode) // Extended format
|
| 2894 |
|
|
pointer = 52;
|
| 2895 |
|
|
else // Standard format
|
| 2896 |
|
|
pointer = 32;
|
| 2897 |
|
|
end
|
| 2898 |
|
|
else
|
| 2899 |
|
|
begin
|
| 2900 |
|
|
if(mode) // Extended format
|
| 2901 |
|
|
pointer = 52 + 8 * length;
|
| 2902 |
|
|
else // Standard format
|
| 2903 |
|
|
pointer = 32 + 8 * length;
|
| 2904 |
|
|
end
|
| 2905 |
|
|
|
| 2906 |
|
|
// This is how many bits we need to shift
|
| 2907 |
|
|
total_bits = pointer;
|
| 2908 |
|
|
|
| 2909 |
|
|
// Waiting until previous msg is finished before sending another one
|
| 2910 |
|
|
if (arbitration_lost) // Arbitration lost. Another node is transmitting. We have to wait until it is finished.
|
| 2911 |
|
|
wait ( (~can_testbench.i_can_top.i_can_bsp.error_frame) &
|
| 2912 |
|
|
(~can_testbench.i_can_top.i_can_bsp.rx_inter ) &
|
| 2913 |
|
|
(~can_testbench.i_can_top.i_can_bsp.tx_state )
|
| 2914 |
|
|
);
|
| 2915 |
|
|
else // We were transmitter of the previous frame. No need to wait for another node to finish transmission.
|
| 2916 |
|
|
wait ( (~can_testbench.i_can_top.i_can_bsp.error_frame) &
|
| 2917 |
|
|
(~can_testbench.i_can_top.i_can_bsp.rx_inter )
|
| 2918 |
|
|
);
|
| 2919 |
|
|
arbitration_lost = 0;
|
| 2920 |
|
|
|
| 2921 |
|
|
send_bit(0); // SOF
|
| 2922 |
|
|
previous_bit = 0;
|
| 2923 |
|
|
|
| 2924 |
|
|
fork
|
| 2925 |
|
|
|
| 2926 |
|
|
begin
|
| 2927 |
|
|
for (cnt=0; cnt<=total_bits; cnt=cnt+1)
|
| 2928 |
|
|
begin
|
| 2929 |
|
|
if (stuff_cnt == 5)
|
| 2930 |
|
|
begin
|
| 2931 |
|
|
stuff_cnt = 1;
|
| 2932 |
|
|
total_bits = total_bits + 1;
|
| 2933 |
|
|
stuff = 1;
|
| 2934 |
|
|
tmp = ~data[pointer+1];
|
| 2935 |
|
|
send_bit(~data[pointer+1]);
|
| 2936 |
|
|
previous_bit = ~data[pointer+1];
|
| 2937 |
|
|
end
|
| 2938 |
|
|
else
|
| 2939 |
|
|
begin
|
| 2940 |
|
|
if (data[pointer] == previous_bit)
|
| 2941 |
|
|
stuff_cnt <= stuff_cnt + 1;
|
| 2942 |
|
|
else
|
| 2943 |
|
|
stuff_cnt <= 1;
|
| 2944 |
|
|
|
| 2945 |
|
|
stuff = 0;
|
| 2946 |
|
|
tmp = data[pointer];
|
| 2947 |
|
|
send_bit(data[pointer]);
|
| 2948 |
|
|
previous_bit = data[pointer];
|
| 2949 |
|
|
pointer = pointer - 1;
|
| 2950 |
|
|
end
|
| 2951 |
|
|
if (arbitration_lost)
|
| 2952 |
|
|
cnt=total_bits+1; // Exit the for loop
|
| 2953 |
|
|
end
|
| 2954 |
|
|
|
| 2955 |
|
|
// Nothing send after the data (just recessive bit)
|
| 2956 |
|
|
repeat (13) send_bit(1); // CRC delimiter + ack + ack delimiter + EOF + intermission= 1 + 1 + 1 + 7 + 3
|
| 2957 |
|
|
end
|
| 2958 |
|
|
|
| 2959 |
|
|
begin
|
| 2960 |
|
|
while (mode ? (cnt<32) : (cnt<12))
|
| 2961 |
|
|
begin
|
| 2962 |
|
|
#1 wait (can_testbench.i_can_top.sample_point);
|
| 2963 |
|
|
if (mode)
|
| 2964 |
|
|
begin
|
| 2965 |
|
|
if (cnt<32 & tmp & (~rx_and_tx))
|
| 2966 |
|
|
begin
|
| 2967 |
|
|
arbitration_lost = 1;
|
| 2968 |
|
|
rx = 1; // Only recessive is send from now on.
|
| 2969 |
|
|
end
|
| 2970 |
|
|
end
|
| 2971 |
|
|
else
|
| 2972 |
|
|
begin
|
| 2973 |
|
|
if (cnt<12 & tmp & (~rx_and_tx))
|
| 2974 |
|
|
begin
|
| 2975 |
|
|
arbitration_lost = 1;
|
| 2976 |
|
|
rx = 1; // Only recessive is send from now on.
|
| 2977 |
|
|
end
|
| 2978 |
|
|
end
|
| 2979 |
|
|
end
|
| 2980 |
|
|
end
|
| 2981 |
|
|
|
| 2982 |
|
|
join
|
| 2983 |
|
|
|
| 2984 |
|
|
end
|
| 2985 |
|
|
endtask
|
| 2986 |
|
|
|
| 2987 |
|
|
|
| 2988 |
|
|
|
| 2989 |
|
|
// State machine monitor (btl)
|
| 2990 |
|
|
always @ (posedge clk)
|
| 2991 |
|
|
begin
|
| 2992 |
|
|
if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
|
| 2993 |
|
|
can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
|
| 2994 |
|
|
begin
|
| 2995 |
|
|
$display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);
|
| 2996 |
|
|
#1000;
|
| 2997 |
|
|
$stop;
|
| 2998 |
|
|
end
|
| 2999 |
|
|
|
| 3000 |
|
|
if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
|
| 3001 |
|
|
can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
|
| 3002 |
|
|
begin
|
| 3003 |
|
|
$display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);
|
| 3004 |
|
|
#1000;
|
| 3005 |
|
|
$stop;
|
| 3006 |
|
|
end
|
| 3007 |
|
|
end
|
| 3008 |
|
|
|
| 3009 |
|
|
/* stuff_error monitor (bsp)
|
| 3010 |
|
|
always @ (posedge clk)
|
| 3011 |
|
|
begin
|
| 3012 |
|
|
if(can_testbench.i_can_top.i_can_bsp.stuff_error)
|
| 3013 |
|
|
begin
|
| 3014 |
|
|
$display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);
|
| 3015 |
|
|
$stop; After everything is finished add another condition (something like & (~idle)) and enable stop
|
| 3016 |
|
|
end
|
| 3017 |
|
|
end
|
| 3018 |
|
|
*/
|
| 3019 |
|
|
|
| 3020 |
|
|
//
|
| 3021 |
|
|
// CRC monitor (used until proper CRC generation is used in testbench
|
| 3022 |
|
|
always @ (posedge clk)
|
| 3023 |
|
|
begin
|
| 3024 |
|
|
if (can_testbench.i_can_top.i_can_bsp.rx_ack &
|
| 3025 |
|
|
can_testbench.i_can_top.i_can_bsp.sample_point &
|
| 3026 |
|
|
can_testbench.i_can_top.i_can_bsp.crc_err
|
| 3027 |
|
|
)
|
| 3028 |
|
|
$display("*E (%0t) ERROR: CRC error (Calculated crc = 0x%0x, crc_in = 0x%0x)", $time, can_testbench.i_can_top.i_can_bsp.calculated_crc, can_testbench.i_can_top.i_can_bsp.crc_in);
|
| 3029 |
|
|
end
|
| 3030 |
|
|
|
| 3031 |
|
|
|
| 3032 |
|
|
|
| 3033 |
|
|
|
| 3034 |
|
|
|
| 3035 |
|
|
/*
|
| 3036 |
|
|
// overrun monitor
|
| 3037 |
|
|
always @ (posedge clk)
|
| 3038 |
|
|
begin
|
| 3039 |
|
|
if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr & can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_full)
|
| 3040 |
|
|
$display("(%0t)overrun", $time);
|
| 3041 |
|
|
end
|
| 3042 |
|
|
*/
|
| 3043 |
|
|
|
| 3044 |
|
|
|
| 3045 |
|
|
// form error monitor
|
| 3046 |
|
|
always @ (posedge clk)
|
| 3047 |
|
|
begin
|
| 3048 |
|
|
if (can_testbench.i_can_top.i_can_bsp.form_err)
|
| 3049 |
|
|
$display("*E (%0t) ERROR: form_error", $time);
|
| 3050 |
|
|
end
|
| 3051 |
|
|
|
| 3052 |
|
|
|
| 3053 |
|
|
|
| 3054 |
|
|
// acknowledge error monitor
|
| 3055 |
|
|
always @ (posedge clk)
|
| 3056 |
|
|
begin
|
| 3057 |
|
|
if (can_testbench.i_can_top.i_can_bsp.ack_err)
|
| 3058 |
|
|
$display("*E (%0t) ERROR: acknowledge_error", $time);
|
| 3059 |
|
|
end
|
| 3060 |
|
|
|
| 3061 |
|
|
/*
|
| 3062 |
|
|
// bit error monitor
|
| 3063 |
|
|
always @ (posedge clk)
|
| 3064 |
|
|
begin
|
| 3065 |
|
|
if (can_testbench.i_can_top.i_can_bsp.bit_err)
|
| 3066 |
|
|
$display("*E (%0t) ERROR: bit_error", $time);
|
| 3067 |
|
|
end
|
| 3068 |
|
|
*/
|
| 3069 |
|
|
|
| 3070 |
|
|
endmodule
|
| 3071 |
|
|
|
