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1 2 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  can_bsp.v                                                   ////
4
////                                                              ////
5
////                                                              ////
6 9 mohor
////  This file is part of the CAN Protocol Controller            ////
7 2 mohor
////  http://www.opencores.org/projects/can/                      ////
8
////                                                              ////
9
////                                                              ////
10
////  Author(s):                                                  ////
11
////       Igor Mohor                                             ////
12
////       igorm@opencores.org                                    ////
13
////                                                              ////
14
////                                                              ////
15 9 mohor
////  All additional information is available in the README.txt   ////
16 2 mohor
////  file.                                                       ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20 9 mohor
//// Copyright (C) 2002, 2003 Authors                             ////
21 2 mohor
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43 28 mohor
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
44
//// protected by patents. Anybody who wants to implement this    ////
45
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
46
//// from Bosch.                                                  ////
47
////                                                              ////
48 2 mohor
//////////////////////////////////////////////////////////////////////
49
//
50
// CVS Revision History
51
//
52
// $Log: not supported by cvs2svn $
53 121 mohor
// Revision 1.41  2003/07/18 15:23:31  tadejm
54
// Tx and rx length are limited to 8 bytes regardless to the DLC value.
55
//
56 112 tadejm
// Revision 1.40  2003/07/16 15:10:17  mohor
57
// Fixed according to the linter.
58
//
59 110 mohor
// Revision 1.39  2003/07/16 13:12:46  mohor
60
// Fixed according to the linter.
61
//
62 107 mohor
// Revision 1.38  2003/07/10 01:59:04  tadejm
63
// Synchronization fixed. In some strange cases it didn't work according to
64
// the VHDL reference model.
65
//
66 104 tadejm
// Revision 1.37  2003/07/07 11:21:37  mohor
67
// Little fixes (to fix warnings).
68
//
69 102 mohor
// Revision 1.36  2003/07/03 09:32:20  mohor
70
// Synchronization changed.
71
//
72 100 mohor
// Revision 1.35  2003/06/27 20:56:12  simons
73
// Virtual silicon ram instances added.
74
//
75 95 simons
// Revision 1.34  2003/06/22 09:43:03  mohor
76 102 mohor
// synthesi full_case parallel_case fixed.
77 95 simons
//
78 93 mohor
// Revision 1.33  2003/06/21 12:16:30  mohor
79
// paralel_case and full_case compiler directives added to case statements.
80
//
81 90 mohor
// Revision 1.32  2003/06/17 14:28:32  mohor
82
// Form error was detected when stuff bit occured at the end of crc.
83
//
84 80 mohor
// Revision 1.31  2003/06/16 14:31:29  tadejm
85
// Bit stuffing corrected when stuffing comes at the end of the crc.
86
//
87 79 tadejm
// Revision 1.30  2003/06/16 13:57:58  mohor
88
// tx_point generated one clk earlier. rx_i registered. Data corrected when
89
// using extended mode.
90
//
91 78 mohor
// Revision 1.29  2003/06/11 14:21:35  mohor
92
// When switching to tx, sync stage is overjumped.
93
//
94 75 mohor
// Revision 1.28  2003/03/01 22:53:33  mohor
95
// Actel APA ram supported.
96
//
97 48 mohor
// Revision 1.27  2003/02/20 00:26:02  mohor
98
// When a dominant bit was detected at the third bit of the intermission and
99
// node had a message to transmit, bit_stuff error could occur. Fixed.
100
//
101 45 mohor
// Revision 1.26  2003/02/19 23:21:54  mohor
102
// When bit error occured while active error flag was transmitted, counter was
103
// not incremented.
104
//
105 44 mohor
// Revision 1.25  2003/02/19 14:44:03  mohor
106
// CAN core finished. Host interface added. Registers finished.
107
// Synchronization to the wishbone finished.
108
//
109 39 mohor
// Revision 1.24  2003/02/18 00:10:15  mohor
110
// Most of the registers added. Registers "arbitration lost capture", "error code
111
// capture" + few more still need to be added.
112
//
113 36 mohor
// Revision 1.23  2003/02/14 20:17:01  mohor
114
// Several registers added. Not finished, yet.
115
//
116 35 mohor
// Revision 1.22  2003/02/12 14:23:59  mohor
117
// abort_tx added. Bit destuff fixed.
118
//
119 32 mohor
// Revision 1.21  2003/02/11 00:56:06  mohor
120
// Wishbone interface added.
121
//
122 31 mohor
// Revision 1.20  2003/02/10 16:02:11  mohor
123
// CAN is working according to the specification. WB interface and more
124
// registers (status, IRQ, ...) needs to be added.
125
//
126 30 mohor
// Revision 1.19  2003/02/09 18:40:29  mohor
127
// Overload fixed. Hard synchronization also enabled at the last bit of
128
// interframe.
129
//
130 29 mohor
// Revision 1.18  2003/02/09 02:24:33  mohor
131
// Bosch license warning added. Error counters finished. Overload frames
132
// still need to be fixed.
133
//
134 28 mohor
// Revision 1.17  2003/02/04 17:24:41  mohor
135
// Backup.
136
//
137 26 mohor
// Revision 1.16  2003/02/04 14:34:52  mohor
138
// *** empty log message ***
139
//
140 25 mohor
// Revision 1.15  2003/01/31 01:13:37  mohor
141
// backup.
142
//
143 24 mohor
// Revision 1.14  2003/01/16 13:36:19  mohor
144
// Form error supported. When receiving messages, last bit of the end-of-frame
145
// does not generate form error. Receiver goes to the idle mode one bit sooner.
146
// (CAN specification ver 2.0, part B, page 57).
147
//
148 22 mohor
// Revision 1.13  2003/01/15 21:59:45  mohor
149
// Data is stored to fifo at the end of ack stage.
150
//
151 21 mohor
// Revision 1.12  2003/01/15 21:05:11  mohor
152
// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
153
//
154 20 mohor
// Revision 1.11  2003/01/15 14:40:23  mohor
155 31 mohor
// RX state machine fixed to receive "remote request" frames correctly.
156
// No data bytes are written to fifo when such frames are received.
157 20 mohor
//
158 19 mohor
// Revision 1.10  2003/01/15 13:16:47  mohor
159 31 mohor
// When a frame with "remote request" is received, no data is stored to
160
// fifo, just the frame information (identifier, ...). Data length that
161
// is stored is the received data length and not the actual data length
162
// that is stored to fifo.
163 19 mohor
//
164 18 mohor
// Revision 1.9  2003/01/14 12:19:35  mohor
165
// rx_fifo is now working.
166
//
167 16 mohor
// Revision 1.8  2003/01/10 17:51:33  mohor
168
// Temporary version (backup).
169
//
170 15 mohor
// Revision 1.7  2003/01/09 21:54:45  mohor
171
// rx fifo added. Not 100 % verified, yet.
172
//
173 14 mohor
// Revision 1.6  2003/01/09 14:46:58  mohor
174
// Temporary files (backup).
175
//
176 13 mohor
// Revision 1.5  2003/01/08 13:30:31  mohor
177
// Temp version.
178
//
179 12 mohor
// Revision 1.4  2003/01/08 02:10:53  mohor
180
// Acceptance filter added.
181
//
182 11 mohor
// Revision 1.3  2002/12/28 04:13:23  mohor
183
// Backup version.
184
//
185 10 mohor
// Revision 1.2  2002/12/27 00:12:52  mohor
186
// Header changed, testbench improved to send a frame (crc still missing).
187
//
188 9 mohor
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
189
// Initial
190 2 mohor
//
191
//
192 9 mohor
//
193 2 mohor
 
194
// synopsys translate_off
195
`include "timescale.v"
196
// synopsys translate_on
197
`include "can_defines.v"
198
 
199
module can_bsp
200
(
201
  clk,
202 10 mohor
  rst,
203
 
204
  sample_point,
205
  sampled_bit,
206
  sampled_bit_q,
207 24 mohor
  tx_point,
208 11 mohor
  hard_sync,
209
 
210 14 mohor
  addr,
211 35 mohor
  data_in,
212 14 mohor
  data_out,
213 48 mohor
  fifo_selected,
214 35 mohor
 
215 14 mohor
 
216
 
217 11 mohor
  /* Mode register */
218 10 mohor
  reset_mode,
219 36 mohor
  listen_only_mode,
220 11 mohor
  acceptance_filter_mode,
221 36 mohor
  self_test_mode,
222 11 mohor
 
223 15 mohor
  /* Command register */
224
  release_buffer,
225 25 mohor
  tx_request,
226 32 mohor
  abort_tx,
227 36 mohor
  self_rx_request,
228
  single_shot_transmission,
229 104 tadejm
  tx_state,
230
  tx_state_q,
231 15 mohor
 
232 39 mohor
  /* Arbitration Lost Capture Register */
233
  read_arbitration_lost_capture_reg,
234
 
235
  /* Error Code Capture Register */
236
  read_error_code_capture_reg,
237
  error_capture_code,
238
 
239 35 mohor
  /* Error Warning Limit register */
240
  error_warning_limit,
241
 
242
  /* Rx Error Counter register */
243
  we_rx_err_cnt,
244
 
245
  /* Tx Error Counter register */
246
  we_tx_err_cnt,
247
 
248 15 mohor
  /* Clock Divider register */
249 11 mohor
  extended_mode,
250
 
251
  rx_idle,
252 24 mohor
  transmitting,
253 100 mohor
  go_rx_inter,
254 104 tadejm
  not_first_bit_of_inter,
255 35 mohor
  set_reset_mode,
256
  node_bus_off,
257
  error_status,
258
  rx_err_cnt,
259
  tx_err_cnt,
260
  transmit_status,
261
  receive_status,
262
  tx_successful,
263
  need_to_tx,
264
  overrun,
265
  info_empty,
266 39 mohor
  set_bus_error_irq,
267
  set_arbitration_lost_irq,
268
  arbitration_lost_capture,
269 36 mohor
  node_error_passive,
270
  node_error_active,
271 39 mohor
  rx_message_counter,
272 11 mohor
 
273 35 mohor
 
274 36 mohor
 
275 11 mohor
  /* This section is for BASIC and EXTENDED mode */
276
  /* Acceptance code register */
277
  acceptance_code_0,
278
 
279
  /* Acceptance mask register */
280
  acceptance_mask_0,
281
  /* End: This section is for BASIC and EXTENDED mode */
282 10 mohor
 
283 11 mohor
  /* This section is for EXTENDED mode */
284
  /* Acceptance code register */
285
  acceptance_code_1,
286
  acceptance_code_2,
287
  acceptance_code_3,
288 10 mohor
 
289 11 mohor
  /* Acceptance mask register */
290
  acceptance_mask_1,
291
  acceptance_mask_2,
292 18 mohor
  acceptance_mask_3,
293 11 mohor
  /* End: This section is for EXTENDED mode */
294 10 mohor
 
295 18 mohor
  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
296
  tx_data_0,
297
  tx_data_1,
298
  tx_data_2,
299
  tx_data_3,
300
  tx_data_4,
301
  tx_data_5,
302
  tx_data_6,
303
  tx_data_7,
304
  tx_data_8,
305
  tx_data_9,
306
  tx_data_10,
307
  tx_data_11,
308 24 mohor
  tx_data_12,
309 18 mohor
  /* End: Tx data registers */
310 24 mohor
 
311
  /* Tx signal */
312 28 mohor
  tx,
313
  tx_oen
314 18 mohor
 
315 95 simons
  /* Bist */
316
`ifdef CAN_BIST
317
  ,
318
  scanb_rst,
319
  scanb_clk,
320
  scanb_si,
321
  scanb_so,
322
  scanb_en
323
`endif
324 2 mohor
);
325
 
326
parameter Tp = 1;
327
 
328 10 mohor
input         clk;
329
input         rst;
330
input         sample_point;
331
input         sampled_bit;
332
input         sampled_bit_q;
333 24 mohor
input         tx_point;
334 11 mohor
input         hard_sync;
335 14 mohor
input   [7:0] addr;
336 35 mohor
input   [7:0] data_in;
337 14 mohor
output  [7:0] data_out;
338 48 mohor
input         fifo_selected;
339 11 mohor
 
340 14 mohor
 
341 10 mohor
input         reset_mode;
342 36 mohor
input         listen_only_mode;
343 11 mohor
input         acceptance_filter_mode;
344
input         extended_mode;
345 36 mohor
input         self_test_mode;
346 2 mohor
 
347 35 mohor
 
348 15 mohor
/* Command register */
349
input         release_buffer;
350 25 mohor
input         tx_request;
351 32 mohor
input         abort_tx;
352 36 mohor
input         self_rx_request;
353
input         single_shot_transmission;
354 104 tadejm
output        tx_state;
355
output        tx_state_q;
356 11 mohor
 
357 39 mohor
/* Arbitration Lost Capture Register */
358
input         read_arbitration_lost_capture_reg;
359
 
360
/* Error Code Capture Register */
361
input         read_error_code_capture_reg;
362
output  [7:0] error_capture_code;
363
 
364 35 mohor
/* Error Warning Limit register */
365
input   [7:0] error_warning_limit;
366
 
367
/* Rx Error Counter register */
368
input         we_rx_err_cnt;
369
 
370
/* Tx Error Counter register */
371
input         we_tx_err_cnt;
372
 
373 10 mohor
output        rx_idle;
374 24 mohor
output        transmitting;
375 100 mohor
output        go_rx_inter;
376 104 tadejm
output        not_first_bit_of_inter;
377 35 mohor
output        set_reset_mode;
378
output        node_bus_off;
379
output        error_status;
380
output  [8:0] rx_err_cnt;
381
output  [8:0] tx_err_cnt;
382
output        transmit_status;
383
output        receive_status;
384
output        tx_successful;
385
output        need_to_tx;
386
output        overrun;
387
output        info_empty;
388 39 mohor
output        set_bus_error_irq;
389
output        set_arbitration_lost_irq;
390
output  [4:0] arbitration_lost_capture;
391 36 mohor
output        node_error_passive;
392
output        node_error_active;
393 39 mohor
output  [6:0] rx_message_counter;
394 2 mohor
 
395 29 mohor
 
396 11 mohor
/* This section is for BASIC and EXTENDED mode */
397
/* Acceptance code register */
398
input   [7:0] acceptance_code_0;
399
 
400
/* Acceptance mask register */
401
input   [7:0] acceptance_mask_0;
402
 
403
/* End: This section is for BASIC and EXTENDED mode */
404
 
405
 
406
/* This section is for EXTENDED mode */
407
/* Acceptance code register */
408
input   [7:0] acceptance_code_1;
409
input   [7:0] acceptance_code_2;
410
input   [7:0] acceptance_code_3;
411
 
412
/* Acceptance mask register */
413
input   [7:0] acceptance_mask_1;
414
input   [7:0] acceptance_mask_2;
415
input   [7:0] acceptance_mask_3;
416
/* End: This section is for EXTENDED mode */
417
 
418 24 mohor
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
419 18 mohor
input   [7:0] tx_data_0;
420
input   [7:0] tx_data_1;
421
input   [7:0] tx_data_2;
422
input   [7:0] tx_data_3;
423
input   [7:0] tx_data_4;
424
input   [7:0] tx_data_5;
425
input   [7:0] tx_data_6;
426
input   [7:0] tx_data_7;
427
input   [7:0] tx_data_8;
428
input   [7:0] tx_data_9;
429
input   [7:0] tx_data_10;
430
input   [7:0] tx_data_11;
431
input   [7:0] tx_data_12;
432 24 mohor
/* End: Tx data registers */
433 11 mohor
 
434 24 mohor
/* Tx signal */
435
output        tx;
436 28 mohor
output        tx_oen;
437 11 mohor
 
438 95 simons
/* Bist */
439
`ifdef CAN_BIST
440
input         scanb_rst;
441
input         scanb_clk;
442
input         scanb_si;
443
output        scanb_so;
444
input         scanb_en;
445
`endif
446
 
447 10 mohor
reg           reset_mode_q;
448
reg     [5:0] bit_cnt;
449 2 mohor
 
450 10 mohor
reg     [3:0] data_len;
451
reg    [28:0] id;
452
reg     [2:0] bit_stuff_cnt;
453 25 mohor
reg     [2:0] bit_stuff_cnt_tx;
454
reg           tx_point_q;
455 10 mohor
 
456
reg           rx_idle;
457
reg           rx_id1;
458
reg           rx_rtr1;
459
reg           rx_ide;
460
reg           rx_id2;
461
reg           rx_rtr2;
462
reg           rx_r1;
463
reg           rx_r0;
464
reg           rx_dlc;
465
reg           rx_data;
466
reg           rx_crc;
467 11 mohor
reg           rx_crc_lim;
468 10 mohor
reg           rx_ack;
469 11 mohor
reg           rx_ack_lim;
470 10 mohor
reg           rx_eof;
471 24 mohor
reg           rx_inter;
472 45 mohor
reg           go_early_tx_latched;
473 10 mohor
 
474 19 mohor
reg           rtr1;
475
reg           ide;
476
reg           rtr2;
477
reg    [14:0] crc_in;
478
 
479 24 mohor
reg     [7:0] tmp_data;
480
reg     [7:0] tmp_fifo [0:7];
481
reg           write_data_to_tmp_fifo;
482
reg     [2:0] byte_cnt;
483
reg           bit_stuff_cnt_en;
484 11 mohor
reg           crc_enable;
485
 
486 10 mohor
reg     [2:0] eof_cnt;
487 28 mohor
reg     [2:0] passive_cnt;
488
 
489 24 mohor
reg           transmitting;
490 10 mohor
 
491 24 mohor
reg           error_frame;
492 28 mohor
reg           error_frame_q;
493 24 mohor
reg           enable_error_cnt2;
494
reg     [2:0] error_cnt1;
495
reg     [2:0] error_cnt2;
496 29 mohor
reg     [2:0] delayed_dominant_cnt;
497
reg           enable_overload_cnt2;
498 30 mohor
reg           overload_frame;
499
reg           overload_frame_blocked;
500 29 mohor
reg     [2:0] overload_cnt1;
501
reg     [2:0] overload_cnt2;
502 24 mohor
reg           tx;
503 28 mohor
reg           crc_err;
504 24 mohor
 
505 39 mohor
reg           arbitration_lost;
506
reg           arbitration_lost_q;
507
reg     [4:0] arbitration_lost_capture;
508
reg           arbitration_cnt_en;
509
reg           arbitration_blocked;
510 25 mohor
reg           tx_q;
511
 
512 28 mohor
reg           need_to_tx;   // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
513 25 mohor
reg     [3:0] data_cnt;     // Counting the data bytes that are written to FIFO
514
reg     [2:0] header_cnt;   // Counting header length
515
reg           wr_fifo;      // Write data and header to 64-byte fifo
516
reg     [7:0] data_for_fifo;// Multiplexed data that is stored to 64-byte fifo
517
 
518
reg     [5:0] tx_pointer;
519
reg           tx_bit;
520
reg           tx_state;
521 104 tadejm
reg           tx_state_q;
522 28 mohor
reg           transmitter;
523 25 mohor
reg           finish_msg;
524
 
525 35 mohor
reg     [8:0] rx_err_cnt;
526
reg     [8:0] tx_err_cnt;
527 28 mohor
reg           rx_err_cnt_blocked;
528 35 mohor
reg     [3:0] bus_free_cnt;
529
reg           bus_free_cnt_en;
530
reg           bus_free;
531
reg           waiting_for_bus_free;
532 28 mohor
 
533
reg           node_error_passive;
534
reg           node_bus_off;
535 35 mohor
reg           node_bus_off_q;
536 28 mohor
reg           ack_err_latched;
537
reg           bit_err_latched;
538
reg           stuff_err_latched;
539
reg           form_err_latched;
540
reg           rule3_exc1_1;
541
reg           rule3_exc1_2;
542
reg           rule3_exc2;
543
reg           suspend;
544
reg           susp_cnt_en;
545
reg     [2:0] susp_cnt;
546
reg           error_flag_over_blocked;
547
 
548 39 mohor
reg     [7:0] error_capture_code;
549
reg     [7:6] error_capture_code_type;
550
reg           error_capture_code_blocked;
551
 
552
wire    [4:0] error_capture_code_segment;
553
wire          error_capture_code_direction;
554
 
555 28 mohor
wire          bit_de_stuff;
556
wire          bit_de_stuff_tx;
557
 
558 44 mohor
wire          rule5;
559 28 mohor
 
560
/* Rx state machine */
561
wire          go_rx_idle;
562
wire          go_rx_id1;
563
wire          go_rx_rtr1;
564
wire          go_rx_ide;
565
wire          go_rx_id2;
566
wire          go_rx_rtr2;
567
wire          go_rx_r1;
568
wire          go_rx_r0;
569
wire          go_rx_dlc;
570
wire          go_rx_data;
571
wire          go_rx_crc;
572
wire          go_rx_crc_lim;
573
wire          go_rx_ack;
574
wire          go_rx_ack_lim;
575
wire          go_rx_eof;
576
wire          go_overload_frame;
577
wire          go_rx_inter;
578 39 mohor
wire          go_error_frame;
579 28 mohor
 
580 104 tadejm
wire          last_bit_of_inter;
581
 
582 28 mohor
wire          go_crc_enable;
583
wire          rst_crc_enable;
584
 
585
wire          bit_de_stuff_set;
586
wire          bit_de_stuff_reset;
587
 
588
wire          go_early_tx;
589
wire          go_tx;
590
 
591
wire   [14:0] calculated_crc;
592
wire   [15:0] r_calculated_crc;
593
wire          remote_rq;
594
wire    [3:0] limited_data_len;
595
wire          form_err;
596
 
597
wire          error_frame_ended;
598
wire          overload_frame_ended;
599
wire          bit_err;
600
wire          ack_err;
601
wire          stuff_err;
602 29 mohor
                                    // of intermission, it starts reading the identifier (and transmitting its own).
603 107 mohor
wire          overload_needed =1'b0;// When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
604 36 mohor
                                    // be send in a row. This is not implemented because host can not send an overload request.
605 28 mohor
 
606 29 mohor
wire          id_ok;                // If received ID matches ID set in registers
607
wire          no_byte0;             // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
608
wire          no_byte1;             // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
609 28 mohor
 
610 25 mohor
wire    [2:0] header_len;
611
wire          storing_header;
612
wire    [3:0] limited_data_len_minus1;
613
wire          reset_wr_fifo;
614 28 mohor
wire          err;
615 25 mohor
 
616 28 mohor
wire          arbitration_field;
617 25 mohor
 
618 28 mohor
wire   [18:0] basic_chain;
619
wire   [63:0] basic_chain_data;
620
wire   [18:0] extended_chain_std;
621
wire   [38:0] extended_chain_ext;
622 78 mohor
wire   [63:0] extended_chain_data_std;
623
wire   [63:0] extended_chain_data_ext;
624 28 mohor
 
625
wire          rst_tx_pointer;
626
 
627
wire    [7:0] r_tx_data_0;
628
wire    [7:0] r_tx_data_1;
629
wire    [7:0] r_tx_data_2;
630
wire    [7:0] r_tx_data_3;
631
wire    [7:0] r_tx_data_4;
632
wire    [7:0] r_tx_data_5;
633
wire    [7:0] r_tx_data_6;
634
wire    [7:0] r_tx_data_7;
635
wire    [7:0] r_tx_data_8;
636
wire    [7:0] r_tx_data_9;
637
wire    [7:0] r_tx_data_10;
638
wire    [7:0] r_tx_data_11;
639
wire    [7:0] r_tx_data_12;
640
 
641
wire          send_ack;
642
wire          bit_err_exc1;
643
wire          bit_err_exc2;
644
wire          bit_err_exc3;
645
wire          bit_err_exc4;
646 30 mohor
wire          bit_err_exc5;
647 28 mohor
wire          error_flag_over;
648 29 mohor
wire          overload_flag_over;
649 28 mohor
 
650 112 tadejm
wire    [5:0] limited_tx_cnt_ext;
651
wire    [5:0] limited_tx_cnt_std;
652 28 mohor
 
653 35 mohor
assign go_rx_idle     =                   sample_point &  sampled_bit & last_bit_of_inter | bus_free & (~node_bus_off);
654 29 mohor
assign go_rx_id1      =                   sample_point &  (~sampled_bit) & (rx_idle | last_bit_of_inter);
655 107 mohor
assign go_rx_rtr1     = (~bit_de_stuff) & sample_point &  rx_id1  & (bit_cnt[3:0] == 4'd10);
656 11 mohor
assign go_rx_ide      = (~bit_de_stuff) & sample_point &  rx_rtr1;
657
assign go_rx_id2      = (~bit_de_stuff) & sample_point &  rx_ide  &   sampled_bit;
658 107 mohor
assign go_rx_rtr2     = (~bit_de_stuff) & sample_point &  rx_id2  & (bit_cnt[4:0] == 5'd17);
659 11 mohor
assign go_rx_r1       = (~bit_de_stuff) & sample_point &  rx_rtr2;
660
assign go_rx_r0       = (~bit_de_stuff) & sample_point & (rx_ide  & (~sampled_bit) | rx_r1);
661
assign go_rx_dlc      = (~bit_de_stuff) & sample_point &  rx_r0;
662 107 mohor
assign go_rx_data     = (~bit_de_stuff) & sample_point &  rx_dlc  & (bit_cnt[1:0] == 2'd3) &  (sampled_bit   |   (|data_len[2:0])) & (~remote_rq);
663
assign go_rx_crc      = (~bit_de_stuff) & sample_point & (rx_dlc  & (bit_cnt[1:0] == 2'd3) & ((~sampled_bit) & (~(|data_len[2:0])) | remote_rq) |
664
                                                          rx_data & (bit_cnt[5:0] == ((limited_data_len<<3) - 1'b1)));  // overflow works ok at max value (8<<3 = 64 = 0). 0-1 = 6'h3f
665
assign go_rx_crc_lim  = (~bit_de_stuff) & sample_point &  rx_crc  & (bit_cnt[3:0] == 4'd14);
666 79 tadejm
assign go_rx_ack      = (~bit_de_stuff) & sample_point &  rx_crc_lim;
667 11 mohor
assign go_rx_ack_lim  =                   sample_point &  rx_ack;
668 35 mohor
assign go_rx_eof      =                   sample_point &  rx_ack_lim;
669 107 mohor
assign go_rx_inter    =                 ((sample_point &  rx_eof  & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & (~overload_needed);
670 10 mohor
 
671 28 mohor
assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
672 107 mohor
assign error_frame_ended = (error_cnt2 == 3'd7) & tx_point;
673
assign overload_frame_ended = (overload_cnt2 == 3'd7) & tx_point;
674 24 mohor
 
675 107 mohor
assign go_overload_frame = (   ((sample_point &  rx_eof  & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & overload_needed |
676
                               sample_point & (~sampled_bit) & rx_inter & (bit_cnt[1:0] < 2'd2)                                                  |
677
                               sample_point & (~sampled_bit) & ((error_cnt2 == 3'd7) | (overload_cnt2 == 3'd7))
678 30 mohor
                           )
679
                           & (~overload_frame_blocked)
680
                           ;
681 24 mohor
 
682 25 mohor
 
683
assign go_crc_enable  = hard_sync | go_tx;
684 11 mohor
assign rst_crc_enable = go_rx_crc;
685 10 mohor
 
686 32 mohor
assign bit_de_stuff_set   = go_rx_id1 & (~go_error_frame);
687 79 tadejm
assign bit_de_stuff_reset = go_rx_ack | reset_mode | go_error_frame | go_overload_frame;
688 11 mohor
 
689 19 mohor
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
690 107 mohor
assign limited_data_len = (data_len < 4'h8)? data_len : 4'h8;
691 11 mohor
 
692 36 mohor
assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);
693 39 mohor
assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx != sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5);
694 28 mohor
assign bit_err_exc1 = tx_state & arbitration_field & tx;
695
assign bit_err_exc2 = rx_ack & tx;
696 107 mohor
assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 3'd7);
697
assign bit_err_exc4 = (error_frame & (error_cnt1 == 3'd7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 3'd7) & (~enable_overload_cnt2));
698
assign bit_err_exc5 = (error_frame & (error_cnt2 == 3'd7)) | (overload_frame & (overload_cnt2 == 3'd7));
699 19 mohor
 
700 28 mohor
assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;
701 25 mohor
 
702 107 mohor
assign last_bit_of_inter = rx_inter & (bit_cnt[1:0] == 2'd2);
703
assign not_first_bit_of_inter = rx_inter & (bit_cnt[1:0] != 2'd0);
704 25 mohor
 
705 26 mohor
 
706 10 mohor
// Rx idle state
707
always @ (posedge clk or posedge rst)
708
begin
709
  if (rst)
710 24 mohor
    rx_idle <= 1'b0;
711
  else if (reset_mode | go_rx_id1 | error_frame)
712 10 mohor
    rx_idle <=#Tp 1'b0;
713
  else if (go_rx_idle)
714
    rx_idle <=#Tp 1'b1;
715
end
716
 
717
 
718
// Rx id1 state
719
always @ (posedge clk or posedge rst)
720
begin
721
  if (rst)
722
    rx_id1 <= 1'b0;
723 24 mohor
  else if (reset_mode | go_rx_rtr1 | error_frame)
724 10 mohor
    rx_id1 <=#Tp 1'b0;
725
  else if (go_rx_id1)
726
    rx_id1 <=#Tp 1'b1;
727
end
728
 
729
 
730
// Rx rtr1 state
731
always @ (posedge clk or posedge rst)
732
begin
733
  if (rst)
734
    rx_rtr1 <= 1'b0;
735 24 mohor
  else if (reset_mode | go_rx_ide | error_frame)
736 10 mohor
    rx_rtr1 <=#Tp 1'b0;
737
  else if (go_rx_rtr1)
738
    rx_rtr1 <=#Tp 1'b1;
739
end
740
 
741
 
742
// Rx ide state
743
always @ (posedge clk or posedge rst)
744
begin
745
  if (rst)
746
    rx_ide <= 1'b0;
747 24 mohor
  else if (reset_mode | go_rx_r0 | go_rx_id2 | error_frame)
748 10 mohor
    rx_ide <=#Tp 1'b0;
749
  else if (go_rx_ide)
750
    rx_ide <=#Tp 1'b1;
751
end
752
 
753
 
754
// Rx id2 state
755
always @ (posedge clk or posedge rst)
756
begin
757
  if (rst)
758
    rx_id2 <= 1'b0;
759 24 mohor
  else if (reset_mode | go_rx_rtr2 | error_frame)
760 10 mohor
    rx_id2 <=#Tp 1'b0;
761
  else if (go_rx_id2)
762
    rx_id2 <=#Tp 1'b1;
763
end
764
 
765
 
766
// Rx rtr2 state
767
always @ (posedge clk or posedge rst)
768
begin
769
  if (rst)
770
    rx_rtr2 <= 1'b0;
771 24 mohor
  else if (reset_mode | go_rx_r1 | error_frame)
772 10 mohor
    rx_rtr2 <=#Tp 1'b0;
773
  else if (go_rx_rtr2)
774
    rx_rtr2 <=#Tp 1'b1;
775
end
776
 
777
 
778
// Rx r0 state
779
always @ (posedge clk or posedge rst)
780
begin
781
  if (rst)
782
    rx_r1 <= 1'b0;
783 24 mohor
  else if (reset_mode | go_rx_r0 | error_frame)
784 10 mohor
    rx_r1 <=#Tp 1'b0;
785
  else if (go_rx_r1)
786
    rx_r1 <=#Tp 1'b1;
787
end
788
 
789
 
790
// Rx r0 state
791
always @ (posedge clk or posedge rst)
792
begin
793
  if (rst)
794
    rx_r0 <= 1'b0;
795 24 mohor
  else if (reset_mode | go_rx_dlc | error_frame)
796 10 mohor
    rx_r0 <=#Tp 1'b0;
797
  else if (go_rx_r0)
798
    rx_r0 <=#Tp 1'b1;
799
end
800
 
801
 
802
// Rx dlc state
803
always @ (posedge clk or posedge rst)
804
begin
805
  if (rst)
806
    rx_dlc <= 1'b0;
807 24 mohor
  else if (reset_mode | go_rx_data | go_rx_crc | error_frame)
808 10 mohor
    rx_dlc <=#Tp 1'b0;
809
  else if (go_rx_dlc)
810
    rx_dlc <=#Tp 1'b1;
811
end
812
 
813
 
814
// Rx data state
815
always @ (posedge clk or posedge rst)
816
begin
817
  if (rst)
818
    rx_data <= 1'b0;
819 24 mohor
  else if (reset_mode | go_rx_crc | error_frame)
820 10 mohor
    rx_data <=#Tp 1'b0;
821
  else if (go_rx_data)
822
    rx_data <=#Tp 1'b1;
823
end
824
 
825
 
826
// Rx crc state
827
always @ (posedge clk or posedge rst)
828
begin
829
  if (rst)
830
    rx_crc <= 1'b0;
831 24 mohor
  else if (reset_mode | go_rx_crc_lim | error_frame)
832 10 mohor
    rx_crc <=#Tp 1'b0;
833
  else if (go_rx_crc)
834
    rx_crc <=#Tp 1'b1;
835
end
836
 
837
 
838 11 mohor
// Rx crc delimiter state
839
always @ (posedge clk or posedge rst)
840
begin
841
  if (rst)
842
    rx_crc_lim <= 1'b0;
843 24 mohor
  else if (reset_mode | go_rx_ack | error_frame)
844 11 mohor
    rx_crc_lim <=#Tp 1'b0;
845
  else if (go_rx_crc_lim)
846
    rx_crc_lim <=#Tp 1'b1;
847
end
848
 
849
 
850 10 mohor
// Rx ack state
851
always @ (posedge clk or posedge rst)
852
begin
853
  if (rst)
854
    rx_ack <= 1'b0;
855 24 mohor
  else if (reset_mode | go_rx_ack_lim | error_frame)
856 10 mohor
    rx_ack <=#Tp 1'b0;
857
  else if (go_rx_ack)
858
    rx_ack <=#Tp 1'b1;
859
end
860
 
861
 
862 11 mohor
// Rx ack delimiter state
863
always @ (posedge clk or posedge rst)
864
begin
865
  if (rst)
866
    rx_ack_lim <= 1'b0;
867 24 mohor
  else if (reset_mode | go_rx_eof | error_frame)
868 11 mohor
    rx_ack_lim <=#Tp 1'b0;
869
  else if (go_rx_ack_lim)
870
    rx_ack_lim <=#Tp 1'b1;
871
end
872
 
873
 
874 10 mohor
// Rx eof state
875
always @ (posedge clk or posedge rst)
876
begin
877
  if (rst)
878
    rx_eof <= 1'b0;
879 30 mohor
  else if (go_rx_inter | error_frame | go_overload_frame)
880 10 mohor
    rx_eof <=#Tp 1'b0;
881
  else if (go_rx_eof)
882
    rx_eof <=#Tp 1'b1;
883
end
884
 
885
 
886 24 mohor
 
887
// Interframe space
888
always @ (posedge clk or posedge rst)
889
begin
890
  if (rst)
891
    rx_inter <= 1'b0;
892 35 mohor
  else if (reset_mode | go_rx_idle | go_rx_id1 | go_overload_frame | go_error_frame)
893 24 mohor
    rx_inter <=#Tp 1'b0;
894
  else if (go_rx_inter)
895
    rx_inter <=#Tp 1'b1;
896
end
897
 
898
 
899 10 mohor
// ID register
900
always @ (posedge clk or posedge rst)
901
begin
902
  if (rst)
903 107 mohor
    id <= 29'h0;
904 11 mohor
  else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
905 10 mohor
    id <=#Tp {id[27:0], sampled_bit};
906
end
907
 
908 11 mohor
 
909
// rtr1 bit
910
always @ (posedge clk or posedge rst)
911
begin
912
  if (rst)
913 107 mohor
    rtr1 <= 1'b0;
914 11 mohor
  else if (sample_point & rx_rtr1 & (~bit_de_stuff))
915
    rtr1 <=#Tp sampled_bit;
916
end
917
 
918
 
919
// rtr2 bit
920
always @ (posedge clk or posedge rst)
921
begin
922
  if (rst)
923 107 mohor
    rtr2 <= 1'b0;
924 11 mohor
  else if (sample_point & rx_rtr2 & (~bit_de_stuff))
925
    rtr2 <=#Tp sampled_bit;
926
end
927
 
928
 
929
// ide bit
930
always @ (posedge clk or posedge rst)
931
begin
932
  if (rst)
933 107 mohor
    ide <= 1'b0;
934 11 mohor
  else if (sample_point & rx_ide & (~bit_de_stuff))
935
    ide <=#Tp sampled_bit;
936
end
937
 
938
 
939 10 mohor
// Data length
940
always @ (posedge clk or posedge rst)
941
begin
942
  if (rst)
943 107 mohor
    data_len <= 4'b0;
944 10 mohor
  else if (sample_point & rx_dlc & (~bit_de_stuff))
945
    data_len <=#Tp {data_len[2:0], sampled_bit};
946
end
947
 
948
 
949 11 mohor
// Data
950
always @ (posedge clk or posedge rst)
951
begin
952
  if (rst)
953 107 mohor
    tmp_data <= 8'h0;
954 11 mohor
  else if (sample_point & rx_data & (~bit_de_stuff))
955
    tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
956
end
957
 
958
 
959
always @ (posedge clk or posedge rst)
960
begin
961
  if (rst)
962 107 mohor
    write_data_to_tmp_fifo <= 1'b0;
963 11 mohor
  else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
964
    write_data_to_tmp_fifo <=#Tp 1'b1;
965
  else
966 107 mohor
    write_data_to_tmp_fifo <=#Tp 1'b0;
967 11 mohor
end
968
 
969
 
970
always @ (posedge clk or posedge rst)
971
begin
972
  if (rst)
973 107 mohor
    byte_cnt <= 3'h0;
974 36 mohor
  else if (write_data_to_tmp_fifo)
975 107 mohor
    byte_cnt <=#Tp byte_cnt + 1'b1;
976 36 mohor
  else if (reset_mode | (sample_point & go_rx_crc_lim))
977 107 mohor
    byte_cnt <=#Tp 3'h0;
978 11 mohor
end
979
 
980
 
981 24 mohor
always @ (posedge clk)
982 11 mohor
begin
983
  if (write_data_to_tmp_fifo)
984
    tmp_fifo[byte_cnt] <=#Tp tmp_data;
985
end
986
 
987
 
988
 
989
// CRC
990
always @ (posedge clk or posedge rst)
991
begin
992
  if (rst)
993 107 mohor
    crc_in <= 15'h0;
994 11 mohor
  else if (sample_point & rx_crc & (~bit_de_stuff))
995
    crc_in <=#Tp {crc_in[13:0], sampled_bit};
996
end
997
 
998
 
999 10 mohor
// bit_cnt
1000
always @ (posedge clk or posedge rst)
1001
begin
1002
  if (rst)
1003 107 mohor
    bit_cnt <= 6'd0;
1004 24 mohor
  else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc |
1005
           go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)
1006 107 mohor
    bit_cnt <=#Tp 6'd0;
1007 11 mohor
  else if (sample_point & (~bit_de_stuff))
1008 10 mohor
    bit_cnt <=#Tp bit_cnt + 1'b1;
1009
end
1010
 
1011
 
1012
// eof_cnt
1013
always @ (posedge clk or posedge rst)
1014
begin
1015
  if (rst)
1016 107 mohor
    eof_cnt <= 3'd0;
1017 10 mohor
  else if (sample_point)
1018
    begin
1019 35 mohor
      if (reset_mode | go_rx_inter | go_error_frame | go_overload_frame)
1020 107 mohor
        eof_cnt <=#Tp 3'd0;
1021 28 mohor
      else if (rx_eof)
1022 10 mohor
        eof_cnt <=#Tp eof_cnt + 1'b1;
1023
    end
1024
end
1025
 
1026
 
1027 11 mohor
// Enabling bit de-stuffing
1028
always @ (posedge clk or posedge rst)
1029
begin
1030
  if (rst)
1031
    bit_stuff_cnt_en <= 1'b0;
1032
  else if (bit_de_stuff_set)
1033
    bit_stuff_cnt_en <=#Tp 1'b1;
1034
  else if (bit_de_stuff_reset)
1035
    bit_stuff_cnt_en <=#Tp 1'b0;
1036
end
1037 10 mohor
 
1038 24 mohor
 
1039 10 mohor
// bit_stuff_cnt
1040
always @ (posedge clk or posedge rst)
1041
begin
1042
  if (rst)
1043 107 mohor
    bit_stuff_cnt <= 3'h1;
1044 15 mohor
  else if (bit_de_stuff_reset)
1045 107 mohor
    bit_stuff_cnt <=#Tp 3'h1;
1046 11 mohor
  else if (sample_point & bit_stuff_cnt_en)
1047 10 mohor
    begin
1048 107 mohor
      if (bit_stuff_cnt == 3'h5)
1049
        bit_stuff_cnt <=#Tp 3'h1;
1050 10 mohor
      else if (sampled_bit == sampled_bit_q)
1051
        bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1;
1052
      else
1053 107 mohor
        bit_stuff_cnt <=#Tp 3'h1;
1054 10 mohor
    end
1055
end
1056
 
1057
 
1058 25 mohor
// bit_stuff_cnt_tx
1059
always @ (posedge clk or posedge rst)
1060
begin
1061
  if (rst)
1062 107 mohor
    bit_stuff_cnt_tx <= 3'h1;
1063 25 mohor
  else if (bit_de_stuff_reset)
1064 107 mohor
    bit_stuff_cnt_tx <=#Tp 3'h1;
1065 25 mohor
  else if (tx_point_q & bit_stuff_cnt_en)
1066
    begin
1067 107 mohor
      if (bit_stuff_cnt_tx == 3'h5)
1068
        bit_stuff_cnt_tx <=#Tp 3'h1;
1069 25 mohor
      else if (tx == tx_q)
1070
        bit_stuff_cnt_tx <=#Tp bit_stuff_cnt_tx + 1'b1;
1071
      else
1072 107 mohor
        bit_stuff_cnt_tx <=#Tp 3'h1;
1073 25 mohor
    end
1074
end
1075
 
1076
 
1077 107 mohor
assign bit_de_stuff = bit_stuff_cnt == 3'h5;
1078
assign bit_de_stuff_tx = bit_stuff_cnt_tx == 3'h5;
1079 10 mohor
 
1080
 
1081 24 mohor
 
1082 28 mohor
// stuff_err
1083
assign stuff_err = sample_point & bit_stuff_cnt_en & bit_de_stuff & (sampled_bit == sampled_bit_q);
1084 10 mohor
 
1085
 
1086 28 mohor
 
1087 35 mohor
// Generating delayed signals
1088 107 mohor
always @ (posedge clk or posedge rst)
1089 10 mohor
begin
1090 107 mohor
  if (rst)
1091
    begin
1092
      reset_mode_q <=#Tp 1'b0;
1093
      node_bus_off_q <=#Tp 1'b0;
1094
    end
1095
  else
1096
    begin
1097
      reset_mode_q <=#Tp reset_mode;
1098
      node_bus_off_q <=#Tp node_bus_off;
1099
    end
1100 10 mohor
end
1101
 
1102
 
1103 11 mohor
 
1104
always @ (posedge clk or posedge rst)
1105
begin
1106
  if (rst)
1107
    crc_enable <= 1'b0;
1108
  else if (go_crc_enable)
1109
    crc_enable <=#Tp 1'b1;
1110
  else if (reset_mode | rst_crc_enable)
1111
    crc_enable <=#Tp 1'b0;
1112
end
1113
 
1114
 
1115
// CRC error generation
1116
always @ (posedge clk or posedge rst)
1117
begin
1118
  if (rst)
1119 28 mohor
    crc_err <= 1'b0;
1120 12 mohor
  else if (go_rx_ack)
1121 28 mohor
    crc_err <=#Tp crc_in != calculated_crc;
1122
  else if (reset_mode | error_frame_ended)
1123
    crc_err <=#Tp 1'b0;
1124 11 mohor
end
1125
 
1126
 
1127 22 mohor
// Conditions for form error
1128 28 mohor
assign form_err = sample_point & ( ((~bit_de_stuff) & rx_ide     &   sampled_bit & (~rtr1)      ) |
1129 80 mohor
                                   ((~bit_de_stuff) & rx_crc_lim & (~sampled_bit)               ) |
1130 28 mohor
                                   (                  rx_ack_lim & (~sampled_bit)               ) |
1131 107 mohor
                                   ((eof_cnt < 3'd6)& rx_eof     & (~sampled_bit) & (~tx_state) ) |
1132 28 mohor
                                   (                & rx_eof     & (~sampled_bit) &   tx_state  )
1133
                                 );
1134 11 mohor
 
1135 22 mohor
 
1136 28 mohor
always @ (posedge clk or posedge rst)
1137
begin
1138
  if (rst)
1139
    ack_err_latched <= 1'b0;
1140 30 mohor
  else if (reset_mode | error_frame_ended | go_overload_frame)
1141 28 mohor
    ack_err_latched <=#Tp 1'b0;
1142
  else if (ack_err)
1143
    ack_err_latched <=#Tp 1'b1;
1144
end
1145
 
1146
 
1147
always @ (posedge clk or posedge rst)
1148
begin
1149
  if (rst)
1150
    bit_err_latched <= 1'b0;
1151 30 mohor
  else if (reset_mode | error_frame_ended | go_overload_frame)
1152 28 mohor
    bit_err_latched <=#Tp 1'b0;
1153
  else if (bit_err)
1154
    bit_err_latched <=#Tp 1'b1;
1155
end
1156
 
1157
 
1158 44 mohor
 
1159 28 mohor
// Rule 5 (Fault confinement).
1160 107 mohor
assign rule5 = (~node_error_passive) & bit_err &  (error_frame    & (error_cnt1    < 3'd7) |
1161
                                                   overload_frame & (overload_cnt1 < 3'd7) );
1162 28 mohor
 
1163
// Rule 3 exception 1 - first part (Fault confinement).
1164
always @ (posedge clk or posedge rst)
1165
begin
1166
  if (rst)
1167
    rule3_exc1_1 <= 1'b0;
1168
  else if (reset_mode | error_flag_over | rule3_exc1_2)
1169
    rule3_exc1_1 <=#Tp 1'b0;
1170
  else if (transmitter & node_error_passive & ack_err)
1171
    rule3_exc1_1 <=#Tp 1'b1;
1172
end
1173
 
1174
 
1175
// Rule 3 exception 1 - second part (Fault confinement).
1176
always @ (posedge clk or posedge rst)
1177
begin
1178
  if (rst)
1179
    rule3_exc1_2 <= 1'b0;
1180
  else if (reset_mode | error_flag_over)
1181
    rule3_exc1_2 <=#Tp 1'b0;
1182
  else if (rule3_exc1_1)
1183
    rule3_exc1_2 <=#Tp 1'b1;
1184 107 mohor
  else if ((error_cnt1 < 3'd7) & sample_point & (~sampled_bit))
1185 28 mohor
    rule3_exc1_2 <=#Tp 1'b0;
1186
end
1187
 
1188
 
1189
// Rule 3 exception 2 (Fault confinement).
1190
always @ (posedge clk or posedge rst)
1191
begin
1192
  if (rst)
1193
    rule3_exc2 <= 1'b0;
1194
  else if (reset_mode | error_flag_over)
1195
    rule3_exc2 <=#Tp 1'b0;
1196
  else if (transmitter & stuff_err & arbitration_field & sample_point & tx & (~sampled_bit))
1197
    rule3_exc2 <=#Tp 1'b1;
1198
end
1199
 
1200
 
1201
 
1202
always @ (posedge clk or posedge rst)
1203
begin
1204
  if (rst)
1205
    stuff_err_latched <= 1'b0;
1206 30 mohor
  else if (reset_mode | error_frame_ended | go_overload_frame)
1207 28 mohor
    stuff_err_latched <=#Tp 1'b0;
1208
  else if (stuff_err)
1209
    stuff_err_latched <=#Tp 1'b1;
1210
end
1211
 
1212
 
1213
 
1214
always @ (posedge clk or posedge rst)
1215
begin
1216
  if (rst)
1217
    form_err_latched <= 1'b0;
1218 30 mohor
  else if (reset_mode | error_frame_ended | go_overload_frame)
1219 28 mohor
    form_err_latched <=#Tp 1'b0;
1220
  else if (form_err)
1221
    form_err_latched <=#Tp 1'b1;
1222
end
1223
 
1224
 
1225
 
1226 11 mohor
// Instantiation of the RX CRC module
1227
can_crc i_can_crc_rx
1228
(
1229
  .clk(clk),
1230 25 mohor
  .data(sampled_bit),
1231 11 mohor
  .enable(crc_enable & sample_point & (~bit_de_stuff)),
1232 35 mohor
  .initialize(go_crc_enable),
1233 11 mohor
  .crc(calculated_crc)
1234
);
1235
 
1236
 
1237
 
1238
 
1239 107 mohor
assign no_byte0 = rtr1 | (data_len<4'h1);
1240
assign no_byte1 = rtr1 | (data_len<4'h2);
1241 11 mohor
 
1242
can_acf i_can_acf
1243
(
1244
  .clk(clk),
1245
  .rst(rst),
1246
 
1247
  .id(id),
1248
 
1249
  /* Mode register */
1250
  .reset_mode(reset_mode),
1251
  .acceptance_filter_mode(acceptance_filter_mode),
1252
 
1253 12 mohor
  // Clock Divider register
1254 11 mohor
  .extended_mode(extended_mode),
1255
 
1256
  /* This section is for BASIC and EXTENDED mode */
1257
  /* Acceptance code register */
1258
  .acceptance_code_0(acceptance_code_0),
1259
 
1260
  /* Acceptance mask register */
1261
  .acceptance_mask_0(acceptance_mask_0),
1262
  /* End: This section is for BASIC and EXTENDED mode */
1263
 
1264
  /* This section is for EXTENDED mode */
1265
  /* Acceptance code register */
1266
  .acceptance_code_1(acceptance_code_1),
1267
  .acceptance_code_2(acceptance_code_2),
1268
  .acceptance_code_3(acceptance_code_3),
1269
 
1270
  /* Acceptance mask register */
1271
  .acceptance_mask_1(acceptance_mask_1),
1272
  .acceptance_mask_2(acceptance_mask_2),
1273
  .acceptance_mask_3(acceptance_mask_3),
1274
  /* End: This section is for EXTENDED mode */
1275
 
1276
  .go_rx_crc_lim(go_rx_crc_lim),
1277 29 mohor
  .go_rx_inter(go_rx_inter),
1278 30 mohor
  .go_error_frame(go_error_frame),
1279 11 mohor
 
1280
  .data0(tmp_fifo[0]),
1281
  .data1(tmp_fifo[1]),
1282
  .rtr1(rtr1),
1283
  .rtr2(rtr2),
1284
  .ide(ide),
1285 16 mohor
  .no_byte0(no_byte0),
1286
  .no_byte1(no_byte1),
1287 11 mohor
 
1288
  .id_ok(id_ok)
1289
 
1290
);
1291
 
1292
 
1293
 
1294
 
1295 16 mohor
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
1296 13 mohor
assign storing_header = header_cnt < header_len;
1297 107 mohor
assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 4'h8)? (data_len -1'b1) : 4'h7);   // - 1 because counter counts from 0
1298
assign reset_wr_fifo = (data_cnt == (limited_data_len_minus1 + {1'b0, header_len})) | reset_mode;
1299 12 mohor
 
1300 28 mohor
assign err = form_err | stuff_err | bit_err | ack_err | form_err_latched | stuff_err_latched | bit_err_latched | ack_err_latched | crc_err;
1301 24 mohor
 
1302
 
1303 28 mohor
 
1304 13 mohor
// Write enable signal for 64-byte rx fifo
1305
always @ (posedge clk or posedge rst)
1306
begin
1307
  if (rst)
1308
    wr_fifo <= 1'b0;
1309 16 mohor
  else if (reset_wr_fifo)
1310
    wr_fifo <=#Tp 1'b0;
1311 36 mohor
  else if (go_rx_inter & id_ok & (~error_frame_ended) & ((~tx_state) | self_rx_request))
1312 13 mohor
    wr_fifo <=#Tp 1'b1;
1313
end
1314 12 mohor
 
1315
 
1316 13 mohor
// Header counter. Header length depends on the mode of operation and frame format.
1317 12 mohor
always @ (posedge clk or posedge rst)
1318
begin
1319
  if (rst)
1320 107 mohor
    header_cnt <= 3'h0;
1321 16 mohor
  else if (reset_wr_fifo)
1322 107 mohor
    header_cnt <=#Tp 3'h0;
1323 16 mohor
  else if (wr_fifo & storing_header)
1324 107 mohor
    header_cnt <=#Tp header_cnt + 1'h1;
1325 12 mohor
end
1326
 
1327
 
1328 13 mohor
// Data counter. Length of the data is limited to 8 bytes.
1329 12 mohor
always @ (posedge clk or posedge rst)
1330
begin
1331
  if (rst)
1332 107 mohor
    data_cnt <= 4'h0;
1333 16 mohor
  else if (reset_wr_fifo)
1334 107 mohor
    data_cnt <=#Tp 4'h0;
1335 16 mohor
  else if (wr_fifo)
1336 107 mohor
    data_cnt <=#Tp data_cnt + 4'h1;
1337 12 mohor
end
1338
 
1339
 
1340 13 mohor
// Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
1341 24 mohor
always @ (extended_mode or ide or data_cnt or header_cnt or  header_len or
1342
          storing_header or id or rtr1 or rtr2 or data_len or
1343 13 mohor
          tmp_fifo[0] or tmp_fifo[2] or tmp_fifo[4] or tmp_fifo[6] or
1344
          tmp_fifo[1] or tmp_fifo[3] or tmp_fifo[5] or tmp_fifo[7])
1345 12 mohor
begin
1346 107 mohor
  casex ({storing_header, extended_mode, ide, header_cnt}) /* synthesis parallel_case */
1347
    6'b1_1_1_000  : data_for_fifo = {1'b1, rtr2, 2'h0, data_len};  // extended mode, extended format header
1348
    6'b1_1_1_001  : data_for_fifo = id[28:21];                     // extended mode, extended format header
1349
    6'b1_1_1_010  : data_for_fifo = id[20:13];                     // extended mode, extended format header
1350
    6'b1_1_1_011  : data_for_fifo = id[12:5];                      // extended mode, extended format header
1351
    6'b1_1_1_100  : data_for_fifo = {id[4:0], 3'h0};               // extended mode, extended format header
1352
    6'b1_1_0_000  : data_for_fifo = {1'b0, rtr1, 2'h0, data_len};  // extended mode, standard format header
1353
    6'b1_1_0_001  : data_for_fifo = id[10:3];                      // extended mode, standard format header
1354
    6'b1_1_0_010  : data_for_fifo = {id[2:0], 5'h0};               // extended mode, standard format header
1355
    6'b1_0_x_000  : data_for_fifo = id[10:3];                      // normal mode                    header
1356
    6'b1_0_x_001  : data_for_fifo = {id[2:0], rtr1, data_len};     // normal mode                    header
1357
    default       : data_for_fifo = tmp_fifo[data_cnt - {1'b0, header_len}]; // data 
1358
  endcase
1359 12 mohor
end
1360
 
1361
 
1362
 
1363
 
1364
// Instantiation of the RX fifo module
1365 13 mohor
can_fifo i_can_fifo
1366 12 mohor
(
1367
  .clk(clk),
1368
  .rst(rst),
1369
 
1370 13 mohor
  .wr(wr_fifo),
1371 12 mohor
 
1372 13 mohor
  .data_in(data_for_fifo),
1373 110 mohor
  .addr(addr[5:0]),
1374 14 mohor
  .data_out(data_out),
1375 48 mohor
  .fifo_selected(fifo_selected),
1376 12 mohor
 
1377
  .reset_mode(reset_mode),
1378 15 mohor
  .release_buffer(release_buffer),
1379 35 mohor
  .extended_mode(extended_mode),
1380
  .overrun(overrun),
1381 39 mohor
  .info_empty(info_empty),
1382
  .info_cnt(rx_message_counter)
1383 95 simons
 
1384
`ifdef CAN_BIST
1385
  ,
1386
  .scanb_rst(scanb_rst),
1387
  .scanb_clk(scanb_clk),
1388
  .scanb_si(scanb_si),
1389
  .scanb_so(scanb_so),
1390
  .scanb_en(scanb_en)
1391
`endif
1392 12 mohor
);
1393
 
1394
 
1395 29 mohor
// Transmitting error frame.
1396 24 mohor
always @ (posedge clk or posedge rst)
1397
begin
1398
  if (rst)
1399
    error_frame <= 1'b0;
1400 30 mohor
  else if (reset_mode | error_frame_ended | go_overload_frame)
1401 24 mohor
    error_frame <=#Tp 1'b0;
1402 28 mohor
  else if (go_error_frame)
1403 24 mohor
    error_frame <=#Tp 1'b1;
1404
end
1405 12 mohor
 
1406 13 mohor
 
1407 107 mohor
always @ (posedge clk or posedge rst)
1408 28 mohor
begin
1409 107 mohor
  if (rst)
1410
    error_frame_q <=#Tp 1'b0;
1411
  else if (sample_point)
1412 28 mohor
    error_frame_q <=#Tp error_frame;
1413
end
1414
 
1415
 
1416 24 mohor
always @ (posedge clk or posedge rst)
1417
begin
1418
  if (rst)
1419 107 mohor
    error_cnt1 <= 3'd0;
1420 30 mohor
  else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
1421 107 mohor
    error_cnt1 <=#Tp 3'd0;
1422
  else if (error_frame & tx_point & (error_cnt1 < 3'd7))
1423 24 mohor
    error_cnt1 <=#Tp error_cnt1 + 1'b1;
1424
end
1425
 
1426
 
1427 28 mohor
 
1428 107 mohor
assign error_flag_over = ((~node_error_passive) & sample_point & (error_cnt1 == 3'd7) | node_error_passive  & sample_point & (passive_cnt == 3'h5)) & (~enable_error_cnt2);
1429 28 mohor
 
1430
 
1431 24 mohor
always @ (posedge clk or posedge rst)
1432
begin
1433
  if (rst)
1434 28 mohor
    error_flag_over_blocked <= 1'b0;
1435 30 mohor
  else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
1436 28 mohor
    error_flag_over_blocked <=#Tp 1'b0;
1437
  else if (error_flag_over)
1438
    error_flag_over_blocked <=#Tp 1'b1;
1439
end
1440
 
1441
 
1442
 
1443
always @ (posedge clk or posedge rst)
1444
begin
1445
  if (rst)
1446 24 mohor
    enable_error_cnt2 <= 1'b0;
1447 30 mohor
  else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
1448 24 mohor
    enable_error_cnt2 <=#Tp 1'b0;
1449 30 mohor
  else if (error_frame & (error_flag_over & sampled_bit))
1450 24 mohor
    enable_error_cnt2 <=#Tp 1'b1;
1451
end
1452
 
1453
 
1454
always @ (posedge clk or posedge rst)
1455
begin
1456
  if (rst)
1457 107 mohor
    error_cnt2 <= 3'd0;
1458 30 mohor
  else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
1459 107 mohor
    error_cnt2 <=#Tp 3'd0;
1460 24 mohor
  else if (enable_error_cnt2 & tx_point)
1461
    error_cnt2 <=#Tp error_cnt2 + 1'b1;
1462
end
1463
 
1464
 
1465 28 mohor
always @ (posedge clk or posedge rst)
1466
begin
1467
  if (rst)
1468 107 mohor
    delayed_dominant_cnt <= 3'h0;
1469 29 mohor
  else if (reset_mode | enable_error_cnt2 | go_error_frame | enable_overload_cnt2 | go_overload_frame)
1470 107 mohor
    delayed_dominant_cnt <=#Tp 3'h0;
1471
  else if (sample_point & (~sampled_bit) & ((error_cnt1 == 3'd7) | (overload_cnt1 == 3'd7)))
1472 29 mohor
    delayed_dominant_cnt <=#Tp delayed_dominant_cnt + 1'b1;
1473 28 mohor
end
1474 24 mohor
 
1475 25 mohor
 
1476 28 mohor
// passive_cnt
1477
always @ (posedge clk or posedge rst)
1478
begin
1479
  if (rst)
1480 107 mohor
    passive_cnt <= 3'h0;
1481 30 mohor
  else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
1482 107 mohor
    passive_cnt <=#Tp 3'h0;
1483
  else if (sample_point & (passive_cnt < 3'h5))
1484 28 mohor
    begin
1485
      if (error_frame_q & (~enable_error_cnt2) & (sampled_bit == sampled_bit_q))
1486
        passive_cnt <=#Tp passive_cnt + 1'b1;
1487
      else
1488 107 mohor
        passive_cnt <=#Tp 3'h0;
1489 28 mohor
    end
1490
end
1491 25 mohor
 
1492
 
1493 29 mohor
 
1494
// Transmitting overload frame.
1495
always @ (posedge clk or posedge rst)
1496
begin
1497
  if (rst)
1498
    overload_frame <= 1'b0;
1499
  else if (reset_mode | overload_frame_ended | go_error_frame)
1500
    overload_frame <=#Tp 1'b0;
1501
  else if (go_overload_frame)
1502
    overload_frame <=#Tp 1'b1;
1503
end
1504
 
1505
 
1506
always @ (posedge clk or posedge rst)
1507
begin
1508
  if (rst)
1509 107 mohor
    overload_cnt1 <= 3'd0;
1510 30 mohor
  else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
1511 107 mohor
    overload_cnt1 <=#Tp 3'd0;
1512
  else if (overload_frame & tx_point & (overload_cnt1 < 3'd7))
1513 29 mohor
    overload_cnt1 <=#Tp overload_cnt1 + 1'b1;
1514
end
1515
 
1516
 
1517 107 mohor
assign overload_flag_over = sample_point & (overload_cnt1 == 3'd7) & (~enable_overload_cnt2);
1518 29 mohor
 
1519
 
1520
always @ (posedge clk or posedge rst)
1521
begin
1522
  if (rst)
1523
    enable_overload_cnt2 <= 1'b0;
1524 30 mohor
  else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
1525 29 mohor
    enable_overload_cnt2 <=#Tp 1'b0;
1526 30 mohor
  else if (overload_frame & (overload_flag_over & sampled_bit))
1527 29 mohor
    enable_overload_cnt2 <=#Tp 1'b1;
1528
end
1529
 
1530
 
1531
always @ (posedge clk or posedge rst)
1532
begin
1533
  if (rst)
1534 107 mohor
    overload_cnt2 <= 3'd0;
1535 30 mohor
  else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
1536 107 mohor
    overload_cnt2 <=#Tp 3'd0;
1537 29 mohor
  else if (enable_overload_cnt2 & tx_point)
1538
    overload_cnt2 <=#Tp overload_cnt2 + 1'b1;
1539
end
1540
 
1541
 
1542 30 mohor
always @ (posedge clk or posedge rst)
1543
begin
1544
  if (rst)
1545 107 mohor
    overload_frame_blocked <= 1'b0;
1546 30 mohor
  else if (reset_mode | go_error_frame | go_rx_id1)
1547 107 mohor
    overload_frame_blocked <=#Tp 1'b0;
1548 30 mohor
  else if (go_overload_frame & overload_frame)            // This is a second sequential overload
1549
    overload_frame_blocked <=#Tp 1'b1;
1550
end
1551
 
1552
 
1553 36 mohor
assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
1554 25 mohor
 
1555
 
1556 24 mohor
always @ (posedge clk or posedge rst)
1557
begin
1558
  if (rst)
1559
    tx <= 1'b1;
1560 30 mohor
  else if (reset_mode)                                                          // Reset
1561 24 mohor
    tx <=#Tp 1'b1;
1562 25 mohor
  else if (tx_point)
1563 24 mohor
    begin
1564 25 mohor
      if (tx_state)                                                             // Transmitting message
1565
        tx <=#Tp ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
1566 28 mohor
      else if (send_ack)                                                        // Acknowledge
1567 25 mohor
        tx <=#Tp 1'b0;
1568 30 mohor
      else if (overload_frame)                                                  // Transmitting overload frame
1569
        begin
1570 107 mohor
          if (overload_cnt1 < 3'd6)
1571 30 mohor
            tx <=#Tp 1'b0;
1572
          else
1573
            tx <=#Tp 1'b1;
1574
        end
1575 29 mohor
      else if (error_frame)                                                     // Transmitting error frame
1576 24 mohor
        begin
1577 107 mohor
          if (error_cnt1 < 3'd6)
1578 25 mohor
            begin
1579 29 mohor
              if (node_error_passive)
1580 25 mohor
                tx <=#Tp 1'b1;
1581
              else
1582
                tx <=#Tp 1'b0;
1583
            end
1584 29 mohor
          else
1585 24 mohor
            tx <=#Tp 1'b1;
1586
        end
1587 25 mohor
      else
1588 24 mohor
        tx <=#Tp 1'b1;
1589
    end
1590
end
1591
 
1592
 
1593 45 mohor
 
1594 107 mohor
always @ (posedge clk or posedge rst)
1595 25 mohor
begin
1596 107 mohor
  if (rst)
1597
    tx_q <=#Tp 1'b0;
1598
  else if (tx_point)
1599 45 mohor
    tx_q <=#Tp tx & (~go_early_tx_latched);
1600 25 mohor
end
1601 24 mohor
 
1602
 
1603 25 mohor
/* Delayed tx point */
1604 107 mohor
always @ (posedge clk or posedge rst)
1605 25 mohor
begin
1606 107 mohor
  if (rst)
1607
    tx_point_q <=#Tp 1'b0;
1608
  else
1609
    tx_point_q <=#Tp tx_point;
1610 25 mohor
end
1611 24 mohor
 
1612
 
1613 25 mohor
/* Changing bit order from [7:0] to [0:7] */
1614
can_ibo i_ibo_tx_data_0  (.di(tx_data_0),  .do(r_tx_data_0));
1615
can_ibo i_ibo_tx_data_1  (.di(tx_data_1),  .do(r_tx_data_1));
1616
can_ibo i_ibo_tx_data_2  (.di(tx_data_2),  .do(r_tx_data_2));
1617
can_ibo i_ibo_tx_data_3  (.di(tx_data_3),  .do(r_tx_data_3));
1618
can_ibo i_ibo_tx_data_4  (.di(tx_data_4),  .do(r_tx_data_4));
1619
can_ibo i_ibo_tx_data_5  (.di(tx_data_5),  .do(r_tx_data_5));
1620
can_ibo i_ibo_tx_data_6  (.di(tx_data_6),  .do(r_tx_data_6));
1621
can_ibo i_ibo_tx_data_7  (.di(tx_data_7),  .do(r_tx_data_7));
1622
can_ibo i_ibo_tx_data_8  (.di(tx_data_8),  .do(r_tx_data_8));
1623
can_ibo i_ibo_tx_data_9  (.di(tx_data_9),  .do(r_tx_data_9));
1624
can_ibo i_ibo_tx_data_10 (.di(tx_data_10), .do(r_tx_data_10));
1625
can_ibo i_ibo_tx_data_11 (.di(tx_data_11), .do(r_tx_data_11));
1626
can_ibo i_ibo_tx_data_12 (.di(tx_data_12), .do(r_tx_data_12));
1627 24 mohor
 
1628 25 mohor
/* Changing bit order from [14:0] to [0:14] */
1629
can_ibo i_calculated_crc0 (.di(calculated_crc[14:7]), .do(r_calculated_crc[7:0]));
1630
can_ibo i_calculated_crc1 (.di({calculated_crc[6:0], 1'b0}), .do(r_calculated_crc[15:8]));
1631 24 mohor
 
1632
 
1633 25 mohor
assign basic_chain = {r_tx_data_1[7:4], 2'h0, r_tx_data_1[3:0], r_tx_data_0[7:0], 1'b0};
1634
assign basic_chain_data = {r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3, r_tx_data_2};
1635
assign extended_chain_std = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
1636
assign extended_chain_ext = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_4[4:0], r_tx_data_3[7:0], r_tx_data_2[7:3], 1'b1, 1'b1, r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
1637 78 mohor
assign extended_chain_data_std = {r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3};
1638
assign extended_chain_data_ext = {r_tx_data_12, r_tx_data_11, r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5};
1639 25 mohor
 
1640 78 mohor
always @ (extended_mode or rx_data or tx_pointer or extended_chain_data_std or extended_chain_data_ext or rx_crc or r_calculated_crc or
1641 25 mohor
          r_tx_data_0   or extended_chain_ext or extended_chain_std or basic_chain_data or basic_chain or
1642
          finish_msg)
1643
begin
1644
  if (extended_mode)
1645
    begin
1646
      if (rx_data)  // data stage
1647 78 mohor
        if (r_tx_data_0[0])    // Extended frame
1648
          tx_bit = extended_chain_data_ext[tx_pointer];
1649
        else
1650
          tx_bit = extended_chain_data_std[tx_pointer];
1651 25 mohor
      else if (rx_crc)
1652
        tx_bit = r_calculated_crc[tx_pointer];
1653
      else if (finish_msg)
1654
        tx_bit = 1'b1;
1655
      else
1656
        begin
1657
          if (r_tx_data_0[0])    // Extended frame
1658
            tx_bit = extended_chain_ext[tx_pointer];
1659
          else
1660
            tx_bit = extended_chain_std[tx_pointer];
1661
        end
1662
    end
1663
  else  // Basic mode
1664
    begin
1665
      if (rx_data)  // data stage
1666
        tx_bit = basic_chain_data[tx_pointer];
1667
      else if (rx_crc)
1668
        tx_bit = r_calculated_crc[tx_pointer];
1669
      else if (finish_msg)
1670
        tx_bit = 1'b1;
1671
      else
1672
        tx_bit = basic_chain[tx_pointer];
1673
    end
1674
end
1675
 
1676
 
1677 112 tadejm
assign limited_tx_cnt_ext = tx_data_0[3] ? 6'h3f : ((tx_data_0[2:0] <<3) - 1'b1);
1678
assign limited_tx_cnt_std = tx_data_1[3] ? 6'h3f : ((tx_data_1[2:0] <<3) - 1'b1);
1679
 
1680
assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) &   extended_mode  &   r_tx_data_0[0]   & tx_pointer == 6'd38             ) |   // arbitration + control for extended format
1681
                        ((~bit_de_stuff_tx) & tx_point & (~rx_data) &   extended_mode  & (~r_tx_data_0[0])  & tx_pointer == 6'd18             ) |   // arbitration + control for extended format
1682
                        ((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode)                      & tx_pointer == 6'd18             ) |   // arbitration + control for standard format
1683
                        ((~bit_de_stuff_tx) & tx_point &   rx_data  &   extended_mode                       & tx_pointer == limited_tx_cnt_ext) |   // data       (overflow is OK here)
1684
                        ((~bit_de_stuff_tx) & tx_point &   rx_data  & (~extended_mode)                      & tx_pointer == limited_tx_cnt_std) |   // data       (overflow is OK here)
1685
                        (                     tx_point &   rx_crc_lim                                                                         ) |   // crc
1686
                        (go_rx_idle                                                                                                           ) |   // at the end
1687
                        (reset_mode                                                                                                           ) |
1688
                        (overload_frame                                                                                                       ) |
1689
                        (error_frame                                                                                                          ) ;
1690
 
1691 25 mohor
always @ (posedge clk or posedge rst)
1692
begin
1693
  if (rst)
1694 107 mohor
    tx_pointer <= 6'h0;
1695 25 mohor
  else if (rst_tx_pointer)
1696 107 mohor
    tx_pointer <=#Tp 6'h0;
1697 25 mohor
  else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
1698
    tx_pointer <=#Tp tx_pointer + 1'b1;
1699
end
1700
 
1701
 
1702 104 tadejm
//assign tx_successful = transmitter & go_rx_inter & ((~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost) | single_shot_transmission);
1703
assign tx_successful = transmitter & go_rx_inter & (~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost);
1704 28 mohor
 
1705
 
1706 25 mohor
always @ (posedge clk or posedge rst)
1707
begin
1708
  if (rst)
1709
    need_to_tx <= 1'b0;
1710 104 tadejm
  else if (tx_successful | reset_mode | (abort_tx & (~transmitting)) | ((~tx_state) & tx_state_q & single_shot_transmission))
1711 28 mohor
    need_to_tx <=#Tp 1'h0;
1712 32 mohor
  else if (tx_request & sample_point)
1713 25 mohor
    need_to_tx <=#Tp 1'b1;
1714
end
1715
 
1716
 
1717
 
1718 36 mohor
assign go_early_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
1719
assign go_tx       = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & (go_early_tx | rx_idle);
1720 25 mohor
 
1721
 
1722 45 mohor
// go_early_tx latched (for proper bit_de_stuff generation)
1723
always @ (posedge clk or posedge rst)
1724
begin
1725
  if (rst)
1726
    go_early_tx_latched <= 1'b0;
1727
  else if (tx_point_q)
1728
    go_early_tx_latched <=#Tp 1'b0;
1729
  else if (go_early_tx)
1730
    go_early_tx_latched <=#Tp 1'b1;
1731
end
1732
 
1733
 
1734
 
1735 25 mohor
// Tx state
1736
always @ (posedge clk or posedge rst)
1737
begin
1738
  if (rst)
1739
    tx_state <= 1'b0;
1740 39 mohor
  else if (reset_mode | go_rx_inter | error_frame | arbitration_lost)
1741 25 mohor
    tx_state <=#Tp 1'b0;
1742
  else if (go_tx)
1743
    tx_state <=#Tp 1'b1;
1744
end
1745
 
1746 107 mohor
always @ (posedge clk or posedge rst)
1747 104 tadejm
begin
1748 107 mohor
  if (rst)
1749
    tx_state_q <=#Tp 1'b0;
1750
  else
1751
    tx_state_q <=#Tp tx_state;
1752 104 tadejm
end
1753 25 mohor
 
1754
 
1755 104 tadejm
 
1756 28 mohor
// Node is a transmitter
1757 25 mohor
always @ (posedge clk or posedge rst)
1758
begin
1759
  if (rst)
1760 28 mohor
    transmitter <= 1'b0;
1761
  else if (go_tx)
1762
    transmitter <=#Tp 1'b1;
1763 104 tadejm
  else if ((reset_mode | go_rx_inter ) | ((~tx_state) & tx_state_q))
1764 28 mohor
    transmitter <=#Tp 1'b0;
1765
end
1766
 
1767
 
1768
 
1769
// Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
1770
// Node might be both transmitter or receiver (sending error or overload frame)
1771
always @ (posedge clk or posedge rst)
1772
begin
1773
  if (rst)
1774 26 mohor
    transmitting <= 1'b0;
1775 28 mohor
  else if (go_error_frame | go_overload_frame | go_tx)
1776
    transmitting <=#Tp 1'b1;
1777 39 mohor
  else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state))
1778 26 mohor
    transmitting <=#Tp 1'b0;
1779
end
1780
 
1781
 
1782 28 mohor
always @ (posedge clk or posedge rst)
1783
begin
1784
  if (rst)
1785 107 mohor
    suspend <= 1'b0;
1786
  else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
1787
    suspend <=#Tp 1'b0;
1788 28 mohor
  else if (go_rx_inter & transmitter & node_error_passive)
1789
    suspend <=#Tp 1'b1;
1790
end
1791 26 mohor
 
1792 28 mohor
 
1793 26 mohor
always @ (posedge clk or posedge rst)
1794
begin
1795
  if (rst)
1796 107 mohor
    susp_cnt_en <= 1'b0;
1797
  else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
1798
    susp_cnt_en <=#Tp 1'b0;
1799 29 mohor
  else if (suspend & sample_point & last_bit_of_inter)
1800 28 mohor
    susp_cnt_en <=#Tp 1'b1;
1801
end
1802
 
1803
 
1804
always @ (posedge clk or posedge rst)
1805
begin
1806
  if (rst)
1807 107 mohor
    susp_cnt <= 3'h0;
1808
  else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
1809
    susp_cnt <=#Tp 3'h0;
1810 28 mohor
  else if (susp_cnt_en & sample_point)
1811
    susp_cnt <=#Tp susp_cnt + 1'b1;
1812
end
1813
 
1814
 
1815
 
1816
 
1817
always @ (posedge clk or posedge rst)
1818
begin
1819
  if (rst)
1820 25 mohor
    finish_msg <= 1'b0;
1821 28 mohor
  else if (go_rx_idle | go_rx_id1 | error_frame | reset_mode)
1822 25 mohor
    finish_msg <=#Tp 1'b0;
1823
  else if (go_rx_crc_lim)
1824
    finish_msg <=#Tp 1'b1;
1825
end
1826
 
1827
 
1828
always @ (posedge clk or posedge rst)
1829
begin
1830
  if (rst)
1831 39 mohor
    arbitration_lost <= 1'b0;
1832 25 mohor
  else if (go_rx_idle | error_frame | reset_mode)
1833 39 mohor
    arbitration_lost <=#Tp 1'b0;
1834 28 mohor
  else if (tx_state & sample_point & tx & arbitration_field)
1835 39 mohor
    arbitration_lost <=#Tp (~sampled_bit);
1836 25 mohor
end
1837
 
1838
 
1839 107 mohor
always @ (posedge clk or posedge rst)
1840 39 mohor
begin
1841 107 mohor
  if (rst)
1842
    arbitration_lost_q <=#Tp 1'b0;
1843
  else
1844
    arbitration_lost_q <=#Tp arbitration_lost;
1845 39 mohor
end
1846 25 mohor
 
1847 39 mohor
 
1848
assign set_arbitration_lost_irq = arbitration_lost & (~arbitration_lost_q) & (~arbitration_blocked);
1849
 
1850
 
1851 28 mohor
always @ (posedge clk or posedge rst)
1852
begin
1853
  if (rst)
1854 39 mohor
    arbitration_cnt_en <= 1'b0;
1855
  else if (arbitration_blocked)
1856
    arbitration_cnt_en <=#Tp 1'b0;
1857
  else if (rx_id1 & sample_point & (~arbitration_blocked))
1858
    arbitration_cnt_en <=#Tp 1'b1;
1859
end
1860
 
1861
 
1862
 
1863
always @ (posedge clk or posedge rst)
1864
begin
1865
  if (rst)
1866
    arbitration_blocked <= 1'b0;
1867
  else if (read_arbitration_lost_capture_reg)
1868
    arbitration_blocked <=#Tp 1'b0;
1869
  else if (set_arbitration_lost_irq)
1870
    arbitration_blocked <=#Tp 1'b1;
1871
end
1872
 
1873
 
1874
always @ (posedge clk or posedge rst)
1875
begin
1876
  if (rst)
1877
    arbitration_lost_capture <= 5'h0;
1878
  else if (read_arbitration_lost_capture_reg)
1879
    arbitration_lost_capture <=#Tp 5'h0;
1880
  else if (sample_point & (~arbitration_blocked) & arbitration_cnt_en & (~bit_de_stuff))
1881
    arbitration_lost_capture <=#Tp arbitration_lost_capture + 1'b1;
1882
end
1883
 
1884
 
1885
 
1886
always @ (posedge clk or posedge rst)
1887
begin
1888
  if (rst)
1889 107 mohor
    rx_err_cnt <= 9'h0;
1890 35 mohor
  else if (we_rx_err_cnt & (~node_bus_off))
1891
    rx_err_cnt <=#Tp {1'b0, data_in};
1892
  else if (set_reset_mode)
1893 107 mohor
    rx_err_cnt <=#Tp 9'h0;
1894 28 mohor
  else
1895
    begin
1896 36 mohor
      if (~listen_only_mode)
1897 28 mohor
        begin
1898 107 mohor
          if ((~transmitter) & rx_ack & (~err) & (rx_err_cnt > 9'h0))
1899 36 mohor
            begin
1900 107 mohor
              if (rx_err_cnt > 9'd127)
1901
                rx_err_cnt <=#Tp 9'd127;
1902 36 mohor
              else
1903
                rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
1904
            end
1905 107 mohor
          else if ((rx_err_cnt < 9'd248) & (~transmitter))   // 248 + 8 = 256
1906 36 mohor
            begin
1907 44 mohor
              if (go_error_frame & (~rule5))                                                                            // 1  (rule 5 is just the opposite then rule 1 exception
1908 36 mohor
                rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
1909 107 mohor
              else if ( (error_frame & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) & (~rx_err_cnt_blocked)  ) |   // 2
1910 44 mohor
                        (go_error_frame & rule5                                                                   ) |   // 5
1911 107 mohor
                        (error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7)                )     // 6
1912 36 mohor
                      )
1913
                rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
1914
            end
1915 30 mohor
        end
1916 28 mohor
    end
1917
end
1918
 
1919
 
1920
always @ (posedge clk or posedge rst)
1921
begin
1922
  if (rst)
1923 107 mohor
    tx_err_cnt <= 9'h0;
1924 35 mohor
  else if (we_tx_err_cnt)
1925
    tx_err_cnt <=#Tp {1'b0, data_in};
1926 28 mohor
  else
1927
    begin
1928 35 mohor
      if (set_reset_mode)
1929 107 mohor
        tx_err_cnt <=#Tp 9'd127;
1930
      else if ((tx_err_cnt > 9'd0) & (tx_successful | bus_free))
1931 30 mohor
        tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
1932 35 mohor
      else if (transmitter)
1933 28 mohor
        begin
1934 107 mohor
          if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7)                  ) |       // 6
1935 44 mohor
               (go_error_frame & rule5                                                          ) |       // 4  (rule 5 is the same as rule 4)
1936 28 mohor
               (error_flag_over & (~error_flag_over_blocked) & (~rule3_exc1_2) & (~rule3_exc2)  )         // 3
1937
             )
1938
            tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
1939
        end
1940
    end
1941
end
1942
 
1943
 
1944
 
1945
always @ (posedge clk or posedge rst)
1946
begin
1947
  if (rst)
1948
    rx_err_cnt_blocked <= 1'b0;
1949
  else if (reset_mode | error_frame_ended)
1950
    rx_err_cnt_blocked <=#Tp 1'b0;
1951 107 mohor
  else if (sample_point & (error_cnt1 == 3'd7))
1952 28 mohor
    rx_err_cnt_blocked <=#Tp 1'b1;
1953
end
1954
 
1955
 
1956
 
1957
always @ (posedge clk or posedge rst)
1958
begin
1959
  if (rst)
1960
    node_error_passive <= 1'b0;
1961 107 mohor
  else if ((rx_err_cnt < 128) & (tx_err_cnt < 9'd128) & error_frame_ended)
1962 28 mohor
    node_error_passive <=#Tp 1'b0;
1963 107 mohor
  else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 9'd128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))
1964 28 mohor
    node_error_passive <=#Tp 1'b1;
1965
end
1966
 
1967
 
1968 36 mohor
assign node_error_active = ~(node_error_passive | node_bus_off);
1969
 
1970
 
1971 28 mohor
always @ (posedge clk or posedge rst)
1972
begin
1973
  if (rst)
1974
    node_bus_off <= 1'b0;
1975 107 mohor
  else if ((rx_err_cnt == 9'h0) & (tx_err_cnt == 9'd0) & (~reset_mode) | (we_tx_err_cnt & (data_in < 8'd255)))
1976 28 mohor
    node_bus_off <=#Tp 1'b0;
1977 107 mohor
  else if ((tx_err_cnt >= 9'd256) | (we_tx_err_cnt & (data_in == 8'd255)))
1978 28 mohor
    node_bus_off <=#Tp 1'b1;
1979
end
1980
 
1981
 
1982 35 mohor
 
1983 28 mohor
always @ (posedge clk or posedge rst)
1984
begin
1985
  if (rst)
1986 107 mohor
    bus_free_cnt <= 4'h0;
1987 35 mohor
  else if (reset_mode)
1988 107 mohor
    bus_free_cnt <=#Tp 4'h0;
1989 30 mohor
  else if (sample_point)
1990
    begin
1991 107 mohor
      if (sampled_bit & bus_free_cnt_en & (bus_free_cnt < 4'd10))
1992 35 mohor
        bus_free_cnt <=#Tp bus_free_cnt + 1'b1;
1993 30 mohor
      else
1994 107 mohor
        bus_free_cnt <=#Tp 4'h0;
1995 30 mohor
    end
1996 28 mohor
end
1997
 
1998
 
1999 35 mohor
always @ (posedge clk or posedge rst)
2000
begin
2001
  if (rst)
2002
    bus_free_cnt_en <= 1'b0;
2003
  else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
2004
    bus_free_cnt_en <=#Tp 1'b1;
2005 121 mohor
  else if (sample_point & sampled_bit & (bus_free_cnt==4'd10) & (~node_bus_off))
2006 35 mohor
    bus_free_cnt_en <=#Tp 1'b0;
2007
end
2008 28 mohor
 
2009
 
2010 35 mohor
always @ (posedge clk or posedge rst)
2011
begin
2012
  if (rst)
2013
    bus_free <= 1'b0;
2014 107 mohor
  else if (sample_point & sampled_bit & (bus_free_cnt==4'd10))
2015 35 mohor
    bus_free <=#Tp 1'b1;
2016
  else
2017
    bus_free <=#Tp 1'b0;
2018
end
2019
 
2020
 
2021
always @ (posedge clk or posedge rst)
2022
begin
2023
  if (rst)
2024
    waiting_for_bus_free <= 1'b1;
2025
  else if (bus_free & (~node_bus_off))
2026
    waiting_for_bus_free <=#Tp 1'b0;
2027
  else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
2028
    waiting_for_bus_free <=#Tp 1'b1;
2029
end
2030
 
2031
 
2032 28 mohor
assign tx_oen = node_bus_off;
2033
 
2034 35 mohor
assign set_reset_mode = node_bus_off & (~node_bus_off_q);
2035
assign error_status = (~reset_mode) & extended_mode? ((rx_err_cnt >= error_warning_limit) | (tx_err_cnt >= error_warning_limit))    :
2036 107 mohor
                                                     ((rx_err_cnt >= 9'd96) | (tx_err_cnt >= 9'd96))                                      ;
2037 28 mohor
 
2038 35 mohor
assign transmit_status = transmitting                 | (extended_mode & waiting_for_bus_free);
2039
assign receive_status  = (~rx_idle) & (~transmitting) | (extended_mode & waiting_for_bus_free);
2040
 
2041 39 mohor
 
2042
/* Error code capture register */
2043
always @ (posedge clk or posedge rst)
2044
begin
2045
  if (rst)
2046
    error_capture_code <= 8'h0;
2047
  else if (read_error_code_capture_reg)
2048
    error_capture_code <=#Tp 8'h0;
2049
  else if (set_bus_error_irq)
2050
    error_capture_code <=#Tp {error_capture_code_type[7:6], error_capture_code_direction, error_capture_code_segment[4:0]};
2051
end
2052
 
2053
 
2054
 
2055 107 mohor
assign error_capture_code_segment[0] = rx_idle | rx_ide | (rx_id2 & (bit_cnt<6'd13)) | rx_r1 | rx_r0 | rx_dlc | rx_ack | rx_ack_lim | error_frame & node_error_active;
2056 39 mohor
assign error_capture_code_segment[1] = rx_idle | rx_id1 | rx_id2 | rx_dlc | rx_data | rx_ack_lim | rx_eof | rx_inter | error_frame & node_error_passive;
2057 107 mohor
assign error_capture_code_segment[2] = (rx_id1 & (bit_cnt>6'd7)) | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2 | rx_r1 | error_frame & node_error_passive | overload_frame;
2058
assign error_capture_code_segment[3] = (rx_id2 & (bit_cnt>6'd4)) | rx_rtr2 | rx_r1 | rx_r0 | rx_dlc | rx_data | rx_crc | rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | overload_frame;
2059 39 mohor
assign error_capture_code_segment[4] = rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | rx_inter | error_frame | overload_frame;
2060
assign error_capture_code_direction  = ~transmitting;
2061
 
2062
 
2063
always @ (bit_err or form_err or stuff_err)
2064
begin
2065
  if (bit_err)
2066 107 mohor
    error_capture_code_type[7:6] = 2'b00;
2067 39 mohor
  else if (form_err)
2068 107 mohor
    error_capture_code_type[7:6] = 2'b01;
2069 39 mohor
  else if (stuff_err)
2070 107 mohor
    error_capture_code_type[7:6] = 2'b10;
2071 39 mohor
  else
2072 107 mohor
    error_capture_code_type[7:6] = 2'b11;
2073 39 mohor
end
2074
 
2075
 
2076
assign set_bus_error_irq = go_error_frame & (~error_capture_code_blocked);
2077
 
2078
 
2079
always @ (posedge clk or posedge rst)
2080
begin
2081
  if (rst)
2082
    error_capture_code_blocked <= 1'b0;
2083
  else if (read_error_code_capture_reg)
2084
    error_capture_code_blocked <=#Tp 1'b0;
2085
  else if (set_bus_error_irq)
2086
    error_capture_code_blocked <=#Tp 1'b1;
2087
end
2088
 
2089
 
2090 2 mohor
endmodule

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