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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  can_bsp.v                                                   ////

////                                                              ////

////                                                              ////

////  This file is part of the CAN Protocol Controller            ////

////  http://www.opencores.org/projects/can/                      ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////       Igor Mohor                                             ////

////       igorm@opencores.org                                    ////

////                                                              ////

////                                                              ////

////  All additional information is available in the README.txt   ////

////  file.                                                       ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2002, 2003, 2004 Authors                       ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//// The CAN protocol is developed by Robert Bosch GmbH and       ////

//// protected by patents. Anybody who wants to implement this    ////

//// CAN IP core on silicon has to obtain a CAN protocol license  ////

//// from Bosch.                                                  ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.52  2004/11/18 12:39:21  igorm

// Fixes for compatibility after the SW reset.

//

// Revision 1.51  2004/11/15 18:23:21  igorm

// When CAN was reset by setting the reset_mode signal in mode register, it

// was possible that CAN was blocked for a short period of time. Problem

// occured very rarly.

//

// Revision 1.50  2004/10/27 18:51:36  igorm

// Fixed synchronization problem in real hardware when 0xf is used for TSEG1.

//

// Revision 1.49  2004/10/25 06:37:51  igorm

// Arbitration bug fixed.

//

// Revision 1.48  2004/05/12 15:58:41  igorm

// Core improved to pass all tests with the Bosch VHDL Reference system.

//

// Revision 1.47  2004/02/08 14:24:10  mohor

// Error counters changed.

//

// Revision 1.46  2003/10/17 05:55:20  markom

// mbist signals updated according to newest convention

//

// Revision 1.45  2003/09/30 21:14:33  mohor

// Error counters changed.

//

// Revision 1.44  2003/09/30 00:55:12  mohor

// Error counters fixed to be compatible with Bosch VHDL reference model.

// Small synchronization changes.

//

// Revision 1.43  2003/09/25 18:55:49  mohor

// Synchronization changed, error counters fixed.

//

// Revision 1.42  2003/08/29 07:01:14  mohor

// When detecting bus-free, signal bus_free_cnt_en was cleared to zero

// although the last sampled bit was zero instead of one.

//

// Revision 1.41  2003/07/18 15:23:31  tadejm

// Tx and rx length are limited to 8 bytes regardless to the DLC value.

//

// Revision 1.40  2003/07/16 15:10:17  mohor

// Fixed according to the linter.

//

// Revision 1.39  2003/07/16 13:12:46  mohor

// Fixed according to the linter.

//

// Revision 1.38  2003/07/10 01:59:04  tadejm

// Synchronization fixed. In some strange cases it didn't work according to

// the VHDL reference model.

//

// Revision 1.37  2003/07/07 11:21:37  mohor

// Little fixes (to fix warnings).

//

// Revision 1.36  2003/07/03 09:32:20  mohor

// Synchronization changed.

//

// Revision 1.35  2003/06/27 20:56:12  simons

// Virtual silicon ram instances added.

//

// Revision 1.34  2003/06/22 09:43:03  mohor

// synthesi full_case parallel_case fixed.

//

// Revision 1.33  2003/06/21 12:16:30  mohor

// paralel_case and full_case compiler directives added to case statements.

//

// Revision 1.32  2003/06/17 14:28:32  mohor

// Form error was detected when stuff bit occured at the end of crc.

//

// Revision 1.31  2003/06/16 14:31:29  tadejm

// Bit stuffing corrected when stuffing comes at the end of the crc.

//

// Revision 1.30  2003/06/16 13:57:58  mohor

// tx_point generated one clk earlier. rx_i registered. Data corrected when

// using extended mode.

//

// Revision 1.29  2003/06/11 14:21:35  mohor

// When switching to tx, sync stage is overjumped.

//

// Revision 1.28  2003/03/01 22:53:33  mohor

// Actel APA ram supported.

//

// Revision 1.27  2003/02/20 00:26:02  mohor

// When a dominant bit was detected at the third bit of the intermission and

// node had a message to transmit, bit_stuff error could occur. Fixed.

//

// Revision 1.26  2003/02/19 23:21:54  mohor

// When bit error occured while active error flag was transmitted, counter was

// not incremented.

//

// Revision 1.25  2003/02/19 14:44:03  mohor

// CAN core finished. Host interface added. Registers finished.

// Synchronization to the wishbone finished.

//

// Revision 1.24  2003/02/18 00:10:15  mohor

// Most of the registers added. Registers "arbitration lost capture", "error code

// capture" + few more still need to be added.

//

// Revision 1.23  2003/02/14 20:17:01  mohor

// Several registers added. Not finished, yet.

//

// Revision 1.22  2003/02/12 14:23:59  mohor

// abort_tx added. Bit destuff fixed.

//

// Revision 1.21  2003/02/11 00:56:06  mohor

// Wishbone interface added.

//

// Revision 1.20  2003/02/10 16:02:11  mohor

// CAN is working according to the specification. WB interface and more

// registers (status, IRQ, ...) needs to be added.

//

// Revision 1.19  2003/02/09 18:40:29  mohor

// Overload fixed. Hard synchronization also enabled at the last bit of

// interframe.

//

// Revision 1.18  2003/02/09 02:24:33  mohor

// Bosch license warning added. Error counters finished. Overload frames

// still need to be fixed.

//

// Revision 1.17  2003/02/04 17:24:41  mohor

// Backup.

//

// Revision 1.16  2003/02/04 14:34:52  mohor

// *** empty log message ***

//

// Revision 1.15  2003/01/31 01:13:37  mohor

// backup.

//

// Revision 1.14  2003/01/16 13:36:19  mohor

// Form error supported. When receiving messages, last bit of the end-of-frame

// does not generate form error. Receiver goes to the idle mode one bit sooner.

// (CAN specification ver 2.0, part B, page 57).

//

// Revision 1.13  2003/01/15 21:59:45  mohor

// Data is stored to fifo at the end of ack stage.

//

// Revision 1.12  2003/01/15 21:05:11  mohor

// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).

//

// Revision 1.11  2003/01/15 14:40:23  mohor

// RX state machine fixed to receive "remote request" frames correctly.

// No data bytes are written to fifo when such frames are received.

//

// Revision 1.10  2003/01/15 13:16:47  mohor

// When a frame with "remote request" is received, no data is stored to

// fifo, just the frame information (identifier, ...). Data length that

// is stored is the received data length and not the actual data length

// that is stored to fifo.

//

// Revision 1.9  2003/01/14 12:19:35  mohor

// rx_fifo is now working.

//

// Revision 1.8  2003/01/10 17:51:33  mohor

// Temporary version (backup).

//

// Revision 1.7  2003/01/09 21:54:45  mohor

// rx fifo added. Not 100 % verified, yet.

//

// Revision 1.6  2003/01/09 14:46:58  mohor

// Temporary files (backup).

//

// Revision 1.5  2003/01/08 13:30:31  mohor

// Temp version.

//

// Revision 1.4  2003/01/08 02:10:53  mohor

// Acceptance filter added.

//

// Revision 1.3  2002/12/28 04:13:23  mohor

// Backup version.

//

// Revision 1.2  2002/12/27 00:12:52  mohor

// Header changed, testbench improved to send a frame (crc still missing).

//

// Revision 1.1.1.1  2002/12/20 16:39:21  mohor

// Initial

//

//

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "can_defines.v"

module can_bsp

(

  clk,

  rst,

  sample_point,

  sampled_bit,

  sampled_bit_q,

  tx_point,

  hard_sync,

  addr,

  data_in,

  data_out,

  fifo_selected,

  /* Mode register */

  reset_mode,

  listen_only_mode,

  acceptance_filter_mode,

  self_test_mode,

  /* Command register */

  release_buffer,

  tx_request,

  abort_tx,

  self_rx_request,

  single_shot_transmission,

  tx_state,

  tx_state_q,

  overload_request,

  overload_frame,

  /* Arbitration Lost Capture Register */

  read_arbitration_lost_capture_reg,

  /* Error Code Capture Register */

  read_error_code_capture_reg,

  error_capture_code,

  /* Error Warning Limit register */

  error_warning_limit,

  /* Rx Error Counter register */

  we_rx_err_cnt,

  /* Tx Error Counter register */

  we_tx_err_cnt,

  /* Clock Divider register */

  extended_mode,

  rx_idle,

  transmitting,

  transmitter,

  go_rx_inter,

  not_first_bit_of_inter,

  rx_inter,

  set_reset_mode,

  node_bus_off,

  error_status,

  rx_err_cnt,

  tx_err_cnt,

  transmit_status,

  receive_status,

  tx_successful,

  need_to_tx,

  overrun,

  info_empty,

  set_bus_error_irq,

  set_arbitration_lost_irq,

  arbitration_lost_capture,

  node_error_passive,

  node_error_active,

  rx_message_counter,

  /* This section is for BASIC and EXTENDED mode */

  /* Acceptance code register */

  acceptance_code_0,

  /* Acceptance mask register */

  acceptance_mask_0,

  /* End: This section is for BASIC and EXTENDED mode */

  /* This section is for EXTENDED mode */

  /* Acceptance code register */

  acceptance_code_1,

  acceptance_code_2,

  acceptance_code_3,

  /* Acceptance mask register */

  acceptance_mask_1,

  acceptance_mask_2,

  acceptance_mask_3,

  /* End: This section is for EXTENDED mode */

  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */

  tx_data_0,

  tx_data_1,

  tx_data_2,

  tx_data_3,

  tx_data_4,

  tx_data_5,

  tx_data_6,

  tx_data_7,

  tx_data_8,

  tx_data_9,

  tx_data_10,

  tx_data_11,

  tx_data_12,

  /* End: Tx data registers */

  /* Tx signal */

  tx,

  tx_next,

  bus_off_on,

  go_overload_frame,

  go_error_frame,

  go_tx,

  send_ack

  /* Bist */

`ifdef CAN_BIST

  ,

  mbist_si_i,

  mbist_so_o,

  mbist_ctrl_i

`endif

);

parameter Tp = 1;

input         clk;

input         rst;

input         sample_point;

input         sampled_bit;

input         sampled_bit_q;

input         tx_point;

input         hard_sync;

input   [7:0] addr;

input   [7:0] data_in;

output  [7:0] data_out;

input         fifo_selected;

input         reset_mode;

input         listen_only_mode;

input         acceptance_filter_mode;

input         extended_mode;

input         self_test_mode;

/* Command register */

input         release_buffer;

input         tx_request;

input         abort_tx;

input         self_rx_request;

input         single_shot_transmission;

output        tx_state;

output        tx_state_q;

input         overload_request;     // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to

output        overload_frame;       // be send in a row. This is not implemented, yet,  because host can not send an overload request.

/* Arbitration Lost Capture Register */

input         read_arbitration_lost_capture_reg;

/* Error Code Capture Register */

input         read_error_code_capture_reg;

output  [7:0] error_capture_code;

/* Error Warning Limit register */

input   [7:0] error_warning_limit;

/* Rx Error Counter register */

input         we_rx_err_cnt;

/* Tx Error Counter register */

input         we_tx_err_cnt;

output        rx_idle;

output        transmitting;

output        transmitter;

output        go_rx_inter;

output        not_first_bit_of_inter;

output        rx_inter;

output        set_reset_mode;

output        node_bus_off;

output        error_status;

output  [8:0] rx_err_cnt;

output  [8:0] tx_err_cnt;

output        transmit_status;

output        receive_status;

output        tx_successful;

output        need_to_tx;

output        overrun;

output        info_empty;

output        set_bus_error_irq;

output        set_arbitration_lost_irq;

output  [4:0] arbitration_lost_capture;

output        node_error_passive;

output        node_error_active;

output  [6:0] rx_message_counter;

/* This section is for BASIC and EXTENDED mode */

/* Acceptance code register */

input   [7:0] acceptance_code_0;

/* Acceptance mask register */

input   [7:0] acceptance_mask_0;

/* End: This section is for BASIC and EXTENDED mode */

/* This section is for EXTENDED mode */

/* Acceptance code register */

input   [7:0] acceptance_code_1;

input   [7:0] acceptance_code_2;

input   [7:0] acceptance_code_3;

/* Acceptance mask register */

input   [7:0] acceptance_mask_1;

input   [7:0] acceptance_mask_2;

input   [7:0] acceptance_mask_3;

/* End: This section is for EXTENDED mode */

/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */

input   [7:0] tx_data_0;

input   [7:0] tx_data_1;

input   [7:0] tx_data_2;

input   [7:0] tx_data_3;

input   [7:0] tx_data_4;

input   [7:0] tx_data_5;

input   [7:0] tx_data_6;

input   [7:0] tx_data_7;

input   [7:0] tx_data_8;

input   [7:0] tx_data_9;

input   [7:0] tx_data_10;

input   [7:0] tx_data_11;

input   [7:0] tx_data_12;

/* End: Tx data registers */

/* Tx signal */

output        tx;

output        tx_next;

output        bus_off_on;

output        go_overload_frame;

output        go_error_frame;

output        go_tx;

output        send_ack;

/* Bist */

`ifdef CAN_BIST

input         mbist_si_i;

output        mbist_so_o;

input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control

`endif

reg           reset_mode_q;

reg     [5:0] bit_cnt;

reg     [3:0] data_len;

reg    [28:0] id;

reg     [2:0] bit_stuff_cnt;

reg     [2:0] bit_stuff_cnt_tx;

reg           tx_point_q;

reg           rx_idle;

reg           rx_id1;

reg           rx_rtr1;

reg           rx_ide;

reg           rx_id2;

reg           rx_rtr2;

reg           rx_r1;

reg           rx_r0;

reg           rx_dlc;

reg           rx_data;

reg           rx_crc;

reg           rx_crc_lim;

reg           rx_ack;

reg           rx_ack_lim;

reg           rx_eof;

reg           rx_inter;

reg           go_early_tx_latched;

reg           rtr1;

reg           ide;

reg           rtr2;

reg    [14:0] crc_in;

reg     [7:0] tmp_data;

reg     [7:0] tmp_fifo [0:7];

reg           write_data_to_tmp_fifo;

reg     [2:0] byte_cnt;

reg           bit_stuff_cnt_en;

reg           crc_enable;

reg     [2:0] eof_cnt;

reg     [2:0] passive_cnt;

reg           transmitting;

reg           error_frame;

reg           enable_error_cnt2;

reg     [2:0] error_cnt1;

reg     [2:0] error_cnt2;

reg     [2:0] delayed_dominant_cnt;

reg           enable_overload_cnt2;

reg           overload_frame;

reg           overload_frame_blocked;

reg     [1:0] overload_request_cnt;

reg     [2:0] overload_cnt1;

reg     [2:0] overload_cnt2;

reg           tx;

reg           crc_err;

reg           arbitration_lost;

reg           arbitration_lost_q;

reg           arbitration_field_d;

reg     [4:0] arbitration_lost_capture;

reg     [4:0] arbitration_cnt;

reg           arbitration_blocked;

reg           tx_q;

reg           need_to_tx;   // When the CAN core has something to transmit and a dominant bit is sampled at the third bit

reg     [3:0] data_cnt;     // Counting the data bytes that are written to FIFO

reg     [2:0] header_cnt;   // Counting header length

reg           wr_fifo;      // Write data and header to 64-byte fifo

reg     [7:0] data_for_fifo;// Multiplexed data that is stored to 64-byte fifo

reg     [5:0] tx_pointer;

reg           tx_bit;

reg           tx_state;

reg           tx_state_q;

reg           transmitter;

reg           finish_msg;

reg     [8:0] rx_err_cnt;

reg     [8:0] tx_err_cnt;

reg     [3:0] bus_free_cnt;

reg           bus_free_cnt_en;

reg           bus_free;

reg           waiting_for_bus_free;

reg           node_error_passive;

reg           node_bus_off;

reg           node_bus_off_q;

reg           ack_err_latched;

reg           bit_err_latched;

reg           stuff_err_latched;

reg           form_err_latched;

reg           rule3_exc1_1;

reg           rule3_exc1_2;

reg           suspend;

reg           susp_cnt_en;

reg     [2:0] susp_cnt;

reg           error_flag_over_latched;

reg     [7:0] error_capture_code;

reg     [7:6] error_capture_code_type;

reg           error_capture_code_blocked;

reg           tx_next;

reg           first_compare_bit;

wire    [4:0] error_capture_code_segment;

wire          error_capture_code_direction;

wire          bit_de_stuff;

wire          bit_de_stuff_tx;

wire          rule5;

/* Rx state machine */

wire          go_rx_idle;

wire          go_rx_id1;

wire          go_rx_rtr1;

wire          go_rx_ide;

wire          go_rx_id2;

wire          go_rx_rtr2;

wire          go_rx_r1;

wire          go_rx_r0;

wire          go_rx_dlc;

wire          go_rx_data;

wire          go_rx_crc;

wire          go_rx_crc_lim;

wire          go_rx_ack;

wire          go_rx_ack_lim;

wire          go_rx_eof;

wire          go_rx_inter;

wire          last_bit_of_inter;

wire          go_crc_enable;

wire          rst_crc_enable;

wire          bit_de_stuff_set;

wire          bit_de_stuff_reset;

wire          go_early_tx;

wire   [14:0] calculated_crc;

wire   [15:0] r_calculated_crc;

wire          remote_rq;

wire    [3:0] limited_data_len;

wire          form_err;

wire          error_frame_ended;

wire          overload_frame_ended;

wire          bit_err;

wire          ack_err;

wire          stuff_err;

wire          id_ok;                // If received ID matches ID set in registers

wire          no_byte0;             // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.

wire          no_byte1;             // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.

wire    [2:0] header_len;

wire          storing_header;

wire    [3:0] limited_data_len_minus1;

wire          reset_wr_fifo;

wire          err;

wire          arbitration_field;

wire   [18:0] basic_chain;

wire   [63:0] basic_chain_data;

wire   [18:0] extended_chain_std;

wire   [38:0] extended_chain_ext;

wire   [63:0] extended_chain_data_std;

wire   [63:0] extended_chain_data_ext;

wire          rst_tx_pointer;

wire    [7:0] r_tx_data_0;

wire    [7:0] r_tx_data_1;

wire    [7:0] r_tx_data_2;

wire    [7:0] r_tx_data_3;

wire    [7:0] r_tx_data_4;

wire    [7:0] r_tx_data_5;

wire    [7:0] r_tx_data_6;

wire    [7:0] r_tx_data_7;

wire    [7:0] r_tx_data_8;

wire    [7:0] r_tx_data_9;

wire    [7:0] r_tx_data_10;

wire    [7:0] r_tx_data_11;

wire    [7:0] r_tx_data_12;

wire          send_ack;

wire          bit_err_exc1;

wire          bit_err_exc2;

wire          bit_err_exc3;

wire          bit_err_exc4;

wire          bit_err_exc5;

wire          bit_err_exc6;

wire          error_flag_over;

wire          overload_flag_over;

wire    [5:0] limited_tx_cnt_ext;

wire    [5:0] limited_tx_cnt_std;

assign go_rx_idle     =                   sample_point &  sampled_bit & last_bit_of_inter | bus_free & (~node_bus_off);

assign go_rx_id1      =                   sample_point &  (~sampled_bit) & (rx_idle | last_bit_of_inter);

assign go_rx_rtr1     = (~bit_de_stuff) & sample_point &  rx_id1  & (bit_cnt[3:0] == 4'd10);

assign go_rx_ide      = (~bit_de_stuff) & sample_point &  rx_rtr1;

assign go_rx_id2      = (~bit_de_stuff) & sample_point &  rx_ide  &   sampled_bit;

assign go_rx_rtr2     = (~bit_de_stuff) & sample_point &  rx_id2  & (bit_cnt[4:0] == 5'd17);