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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.20  2003/06/20 14:51:11  mohor
// Previous change removed. When resynchronization occurs we go to seg1
// stage. sync stage does not cause another start of seg1 stage.
//
// Revision 1.19  2003/06/20 14:28:20  mohor
// When hard_sync or resync occure we need to go to seg1 segment. Going to
// sync segment is in that case blocked.
//
// Revision 1.18  2003/06/17 15:53:33  mohor
// clk_cnt reduced from [8:0] to [6:0].
//
// Revision 1.17  2003/06/17 14:32:17  mohor
// Removed few signals.
//
// Revision 1.16  2003/06/16 13:57:58  mohor
// tx_point generated one clk earlier. rx_i registered. Data corrected when
// using extended mode.
//
// Revision 1.15  2003/06/13 15:02:24  mohor
// Synchronization is also needed when transmitting a message.
//
// Revision 1.14  2003/06/13 14:55:11  mohor
// Counters width changed.
//
// Revision 1.13  2003/06/11 14:21:35  mohor
// When switching to tx, sync stage is overjumped.
//
// Revision 1.12  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.11  2003/02/09 18:40:29  mohor
// Overload fixed. Hard synchronization also enabled at the last bit of
// interframe.
//
// Revision 1.10  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.9  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.8  2003/01/10 17:51:34  mohor
// Temporary version (backup).
//
// Revision 1.7  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.6  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.5  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.4  2002/12/26 01:33:05  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:16  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:17:00  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
 
  /* Mode register */
  reset_mode,
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  sample_point,
  sampled_bit,
  sampled_bit_q,
  tx_point,
  hard_sync,
 
  /* Output from can_bsp module */
  rx_idle,
  last_bit_of_inter,
  transmitting,
  go_rx_inter
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
 
  /* Mode register */
input         reset_mode;
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output from can_bsp module */
input         rx_idle;
input         last_bit_of_inter;
input         transmitting;
input         go_rx_inter;
 
/* Output signals from this module */
output        sample_point;
output        sampled_bit;
output        sampled_bit_q;
output        tx_point;
output        hard_sync;
 
 
 
reg     [6:0] clk_cnt;
reg           clk_en;
reg           clk_en_q;
reg           sync_blocked;
reg           hard_sync_blocked;
reg           sampled_bit;
reg           sampled_bit_q;
reg     [4:0] quant_cnt;
reg     [3:0] delay;
reg           sync;
reg           seg1;
reg           seg2;
reg           resync_latched;
reg           sample_point;
reg     [1:0] sample;
reg           go_sync;
reg           go_seg1;
reg           go_seg2;
reg           tx_point;
 
wire          go_sync_unregistered;
wire          go_seg1_unregistered;
wire          go_seg2_unregistered;
wire [8:0]    preset_cnt;
wire          sync_window;
wire          resync;
wire          quant_cnt_rst;
 
 
 
assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
assign hard_sync  =   (rx_idle | last_bit_of_inter)    & (~rx) & sampled_bit & (~hard_sync_blocked);  // Hard synchronization
assign resync     =  (~rx_idle) & (~last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~(transmitting & seg1));       // Re-synchronization
 
 
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_cnt <= 0;
  else if (clk_cnt >= (preset_cnt-1'b1))
    clk_cnt <=#Tp 0;
  else
    clk_cnt <=#Tp clk_cnt + 1'b1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en  <= 1'b0;
  else if (clk_cnt == (preset_cnt-1'b1))
    clk_en  <=#Tp 1'b1;
  else
    clk_en  <=#Tp 1'b0;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en_q  <= 1'b0;
  else
    clk_en_q  <=#Tp clk_en;
end
 
 
 
/* Changing states */
 assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));
 assign go_seg1_unregistered = clk_en & (((sync | hard_sync) & (~seg1)) | (resync & seg2 & sync_window) | (resync_latched & sync_window));
 assign go_seg2_unregistered = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    go_sync <= 1'b0;
  else
    go_sync <=#Tp go_sync_unregistered;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    go_seg1 <= 1'b0;
  else
    go_seg1 <=#Tp go_seg1_unregistered;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    go_seg2 <= 1'b0;
  else
    go_seg2 <=#Tp go_seg2_unregistered;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    tx_point <= 1'b0;
  else
    tx_point <=#Tp go_sync_unregistered | (go_seg1_unregistered & (~(sync | hard_sync)));
end
 
 
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
   SJW is reached */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_latched <= 1'b0;
  else if (resync & seg2 & (~sync_window))
    resync_latched <=#Tp 1'b1;
  else if (go_seg1)
    resync_latched <= 1'b0;
end
 
 
 
/* Synchronization stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync <= 0;
  else if (go_sync)
    sync <=#Tp 1'b1;
  else if (clk_en_q)
    sync <=#Tp 1'b0;
end
 
 
/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg1 <= 1;
  else if (go_seg1)
    seg1 <=#Tp 1'b1;
  else if (go_seg2)
    seg1 <=#Tp 1'b0;
end
 
 
/* Seg2 stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg2 <= 0;
  else if (go_seg2)
    seg2 <=#Tp 1'b1;
  else if (go_sync | go_seg1)
    seg2 <=#Tp 1'b0;
end
 
 
/* Quant counter */
assign quant_cnt_rst = go_sync | go_seg1 | go_seg2;
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    quant_cnt <= 0;
  else if (quant_cnt_rst)
    quant_cnt <=#Tp 0;
  else if (clk_en_q)
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
 
 
/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    delay <= 0;
  else if (clk_en_q & resync & seg1)
    delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);
  else if (go_sync | go_seg1)
    delay <=#Tp 0;
end
 
 
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
 
 
// Sampling data (memorizing two samples all the time).
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sample <= 2'b11;
  else if (clk_en_q)
    sample <= {sample[0], rx};
end
 
 
// When enabled, tripple sampling is done here.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1;
      sampled_bit_q <= 1;
      sample_point <= 0;
    end
  else if (clk_en_q & (~hard_sync))
    begin
      if (seg1 & (quant_cnt == (time_segment1 + delay)))
        begin
          sample_point <=#Tp 1;
          sampled_bit_q <=#Tp sampled_bit;
          if (triple_sampling)
            sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
          else
            sampled_bit <=#Tp rx;
        end
    end
  else
    sample_point <=#Tp 0;
end
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync_blocked <=#Tp 1'b0;
  else if (clk_en_q)
    begin
      if (resync)
        sync_blocked <=#Tp 1'b1;
      else if (seg2 & (quant_cnt[2:0] == time_segment2))
        sync_blocked <=#Tp 1'b0;
    end
end
 
 
/* Blocking hard synchronization when occurs once or when we are transmitting a msg */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    hard_sync_blocked <=#Tp 1'b0;
  else if (hard_sync | transmitting & tx_point)
    hard_sync_blocked <=#Tp 1'b1;
  else if (go_rx_inter)
    hard_sync_blocked <=#Tp 1'b0;
end
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	2	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	100	mohor	`// Revision 1.20 2003/06/20 14:51:11 mohor`
54			`// Previous change removed. When resynchronization occurs we go to seg1`
55			`// stage. sync stage does not cause another start of seg1 stage.`
56			`//`
57	88	mohor	`// Revision 1.19 2003/06/20 14:28:20 mohor`
58			`// When hard_sync or resync occure we need to go to seg1 segment. Going to`
59			`// sync segment is in that case blocked.`
60			`//`
61	87	mohor	`// Revision 1.18 2003/06/17 15:53:33 mohor`
62			`// clk_cnt reduced from [8:0] to [6:0].`
63			`//`
64	84	mohor	`// Revision 1.17 2003/06/17 14:32:17 mohor`
65			`// Removed few signals.`
66			`//`
67	82	mohor	`// Revision 1.16 2003/06/16 13:57:58 mohor`
68			`// tx_point generated one clk earlier. rx_i registered. Data corrected when`
69			`// using extended mode.`
70			`//`
71	78	mohor	`// Revision 1.15 2003/06/13 15:02:24 mohor`
72			`// Synchronization is also needed when transmitting a message.`
73			`//`
74	77	mohor	`// Revision 1.14 2003/06/13 14:55:11 mohor`
75			`// Counters width changed.`
76			`//`
77	76	mohor	`// Revision 1.13 2003/06/11 14:21:35 mohor`
78			`// When switching to tx, sync stage is overjumped.`
79			`//`
80	75	mohor	`// Revision 1.12 2003/02/14 20:17:01 mohor`
81			`// Several registers added. Not finished, yet.`
82			`//`
83	35	mohor	`// Revision 1.11 2003/02/09 18:40:29 mohor`
84			`// Overload fixed. Hard synchronization also enabled at the last bit of`
85			`// interframe.`
86			`//`
87	29	mohor	`// Revision 1.10 2003/02/09 02:24:33 mohor`
88			`// Bosch license warning added. Error counters finished. Overload frames`
89			`// still need to be fixed.`
90			`//`
91	28	mohor	`// Revision 1.9 2003/01/31 01:13:38 mohor`
92			`// backup.`
93			`//`
94	24	mohor	`// Revision 1.8 2003/01/10 17:51:34 mohor`
95			`// Temporary version (backup).`
96			`//`
97	15	mohor	`// Revision 1.7 2003/01/08 02:10:53 mohor`
98			`// Acceptance filter added.`
99			`//`
100	11	mohor	`// Revision 1.6 2002/12/28 04:13:23 mohor`
101			`// Backup version.`
102			`//`
103	10	mohor	`// Revision 1.5 2002/12/27 00:12:52 mohor`
104			`// Header changed, testbench improved to send a frame (crc still missing).`
105			`//`
106	9	mohor	`// Revision 1.4 2002/12/26 01:33:05 mohor`
107			`// Tripple sampling supported.`
108			`//`
109	7	mohor	`// Revision 1.3 2002/12/25 23:44:16 mohor`
110			`// Commented lines removed.`
111			`//`
112	6	mohor	`// Revision 1.2 2002/12/25 14:17:00 mohor`
113			`// Synchronization working.`
114			`//`
115	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
116			`// Initial`
117	2	mohor	`//`
118			`//`
119	5	mohor	`//`
120	2	mohor
121			`// synopsys translate_off`
122			`include "timescale.v"
123			`// synopsys translate_on`
124			`include "can_defines.v"
125
126			`module can_btl`
127			`(`
128			`clk,`
129			`rst,`
130			`rx,`
131
132			`/* Mode register */`
133	10	mohor	`reset_mode,`
134	2	mohor
135			`/* Bus Timing 0 register */`
136			`baud_r_presc,`
137			`sync_jump_width,`
138
139			`/* Bus Timing 1 register */`
140			`time_segment1,`
141			`time_segment2,`
142			`triple_sampling,`
143
144			`/* Output signals from this module */`
145	10	mohor	`sample_point,`
146			`sampled_bit,`
147			`sampled_bit_q,`
148	24	mohor	`tx_point,`
149	11	mohor	`hard_sync,`
150	2	mohor
151	10	mohor	`/* Output from can_bsp module */`
152	24	mohor	`rx_idle,`
153	100	mohor	`last_bit_of_inter,`
154			`transmitting,`
155			`go_rx_inter`
156	2	mohor
157			`);`
158
159			`parameter Tp = 1;`
160
161			`input clk;`
162			`input rst;`
163			`input rx;`
164
165	10	mohor	`/* Mode register */`
166	2	mohor	`input reset_mode;`
167
168			`/* Bus Timing 0 register */`
169			`input [5:0] baud_r_presc;`
170			`input [1:0] sync_jump_width;`
171
172			`/* Bus Timing 1 register */`
173			`input [3:0] time_segment1;`
174			`input [2:0] time_segment2;`
175			`input triple_sampling;`
176
177	10	mohor	`/* Output from can_bsp module */`
178			`input rx_idle;`
179	29	mohor	`input last_bit_of_inter;`
180	100	mohor	`input transmitting;`
181			`input go_rx_inter;`
182	10	mohor
183	2	mohor	`/* Output signals from this module */`
184	10	mohor	`output sample_point;`
185			`output sampled_bit;`
186			`output sampled_bit_q;`
187	24	mohor	`output tx_point;`
188	11	mohor	`output hard_sync;`
189	2	mohor
190
191
192	84	mohor	`reg [6:0] clk_cnt;`
193	2	mohor	`reg clk_en;`
194	78	mohor	`reg clk_en_q;`
195	5	mohor	`reg sync_blocked;`
196	100	mohor	`reg hard_sync_blocked;`
197	2	mohor	`reg sampled_bit;`
198	10	mohor	`reg sampled_bit_q;`
199	76	mohor	`reg [4:0] quant_cnt;`
200	6	mohor	`reg [3:0] delay;`
201			`reg sync;`
202			`reg seg1;`
203			`reg seg2;`
204			`reg resync_latched;`
205	10	mohor	`reg sample_point;`
206	7	mohor	`reg [1:0] sample;`
207	76	mohor	`reg go_sync;`
208	100	mohor	`reg go_seg1;`
209			`reg go_seg2;`
210			`reg tx_point;`
211	2	mohor
212	76	mohor	`wire go_sync_unregistered;`
213	100	mohor	`wire go_seg1_unregistered;`
214			`wire go_seg2_unregistered;`
215	6	mohor	`wire [8:0] preset_cnt;`
216			`wire sync_window;`
217	75	mohor	`wire resync;`
218	82	mohor	`wire quant_cnt_rst;`
219	2	mohor
220	5	mohor
221	76	mohor
222	6	mohor	`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
223	100	mohor	`assign hard_sync = (rx_idle \| last_bit_of_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization`
224			`assign resync = (~rx_idle) & (~last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~(transmitting & seg1)); // Re-synchronization`
225	5	mohor
226
227	6	mohor	`/* Generating general enable signal that defines baud rate. */`
228	2	mohor	`always @ (posedge clk or posedge rst)`
229			`begin`
230			`if (rst)`
231	10	mohor	`clk_cnt <= 0;`
232	78	mohor	`else if (clk_cnt >= (preset_cnt-1'b1))`
233	10	mohor	`clk_cnt <=#Tp 0;`
234			`else`
235	76	mohor	`clk_cnt <=#Tp clk_cnt + 1'b1;`
236	10	mohor	`end`
237
238
239			`always @ (posedge clk or posedge rst)`
240			`begin`
241			`if (rst)`
242			`clk_en <= 1'b0;`
243	76	mohor	`else if (clk_cnt == (preset_cnt-1'b1))`
244	10	mohor	`clk_en <=#Tp 1'b1;`
245	2	mohor	`else`
246	10	mohor	`clk_en <=#Tp 1'b0;`
247	2	mohor	`end`
248
249
250	5	mohor
251	78	mohor	`always @ (posedge clk or posedge rst)`
252			`begin`
253			`if (rst)`
254			`clk_en_q <= 1'b0;`
255			`else`
256			`clk_en_q <=#Tp clk_en;`
257			`end`
258
259
260
261	6	mohor	`/* Changing states */`
262	76	mohor	`assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));`
263	100	mohor	`assign go_seg1_unregistered = clk_en & (((sync \| hard_sync) & (~seg1)) \| (resync & seg2 & sync_window) \| (resync_latched & sync_window));`
264			`assign go_seg2_unregistered = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));`
265	5	mohor
266
267	76	mohor	`always @ (posedge clk or posedge rst)`
268			`begin`
269			`if (rst)`
270			`go_sync <= 1'b0;`
271			`else`
272	88	mohor	`go_sync <=#Tp go_sync_unregistered;`
273	76	mohor	`end`
274
275
276	100	mohor	`always @ (posedge clk or posedge rst)`
277			`begin`
278			`if (rst)`
279			`go_seg1 <= 1'b0;`
280			`else`
281			`go_seg1 <=#Tp go_seg1_unregistered;`
282			`end`
283
284
285			`always @ (posedge clk or posedge rst)`
286			`begin`
287			`if (rst)`
288			`go_seg2 <= 1'b0;`
289			`else`
290			`go_seg2 <=#Tp go_seg2_unregistered;`
291			`end`
292
293
294			`always @ (posedge clk or posedge rst)`
295			`begin`
296			`if (rst)`
297			`tx_point <= 1'b0;`
298			`else`
299			`tx_point <=#Tp go_sync_unregistered \| (go_seg1_unregistered & (~(sync \| hard_sync)));`
300			`end`
301
302
303	6	mohor	`/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when`
304			`SJW is reached */`
305	2	mohor	`always @ (posedge clk or posedge rst)`
306			`begin`
307			`if (rst)`
308	5	mohor	`resync_latched <= 1'b0;`
309	6	mohor	`else if (resync & seg2 & (~sync_window))`
310	5	mohor	`resync_latched <=#Tp 1'b1;`
311			`else if (go_seg1)`
312			`resync_latched <= 1'b0;`
313			`end`
314
315
316
317	6	mohor	`/* Synchronization stage/segment */`
318	5	mohor	`always @ (posedge clk or posedge rst)`
319			`begin`
320			`if (rst)`
321	10	mohor	`sync <= 0;`
322	5	mohor	`else if (go_sync)`
323			`sync <=#Tp 1'b1;`
324	78	mohor	`else if (clk_en_q)`
325	5	mohor	`sync <=#Tp 1'b0;`
326			`end`
327
328
329	6	mohor	`/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */`
330	5	mohor	`always @ (posedge clk or posedge rst)`
331			`begin`
332			`if (rst)`
333	10	mohor	`seg1 <= 1;`
334	5	mohor	`else if (go_seg1)`
335			`seg1 <=#Tp 1'b1;`
336			`else if (go_seg2)`
337			`seg1 <=#Tp 1'b0;`
338			`end`
339
340
341	6	mohor	`/* Seg2 stage/segment */`
342	5	mohor	`always @ (posedge clk or posedge rst)`
343			`begin`
344			`if (rst)`
345			`seg2 <= 0;`
346			`else if (go_seg2)`
347			`seg2 <=#Tp 1'b1;`
348			`else if (go_sync \| go_seg1)`
349			`seg2 <=#Tp 1'b0;`
350			`end`
351
352
353	6	mohor	`/* Quant counter */`
354	82	mohor	`assign quant_cnt_rst = go_sync \| go_seg1 \| go_seg2;`
355	76	mohor
356	5	mohor	`always @ (posedge clk or posedge rst)`
357			`begin`
358			`if (rst)`
359			`quant_cnt <= 0;`
360	82	mohor	`else if (quant_cnt_rst)`
361	5	mohor	`quant_cnt <=#Tp 0;`
362	78	mohor	`else if (clk_en_q)`
363	5	mohor	`quant_cnt <=#Tp quant_cnt + 1'b1;`
364			`end`
365
366
367	6	mohor	`/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */`
368	5	mohor	`always @ (posedge clk or posedge rst)`
369			`begin`
370			`if (rst)`
371	6	mohor	`delay <= 0;`
372	78	mohor	`else if (clk_en_q & resync & seg1)`
373	76	mohor	`delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);`
374	5	mohor	`else if (go_sync \| go_seg1)`
375	6	mohor	`delay <=#Tp 0;`
376	5	mohor	`end`
377
378
379	6	mohor	`// If early edge appears within this window (in seg2 stage), phase error is fully compensated`
380	76	mohor	`assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));`
381	5	mohor
382
383	7	mohor	`// Sampling data (memorizing two samples all the time).`
384	5	mohor	`always @ (posedge clk or posedge rst)`
385			`begin`
386			`if (rst)`
387	7	mohor	`sample <= 2'b11;`
388	78	mohor	`else if (clk_en_q)`
389	7	mohor	`sample <= {sample[0], rx};`
390			`end`
391
392
393			`// When enabled, tripple sampling is done here.`
394			`always @ (posedge clk or posedge rst)`
395			`begin`
396			`if (rst)`
397	2	mohor	`begin`
398			`sampled_bit <= 1;`
399	10	mohor	`sampled_bit_q <= 1;`
400			`sample_point <= 0;`
401	2	mohor	`end`
402	78	mohor	`else if (clk_en_q & (~hard_sync))`
403	2	mohor	`begin`
404	7	mohor	`if (seg1 & (quant_cnt == (time_segment1 + delay)))`
405			`begin`
406	10	mohor	`sample_point <=#Tp 1;`
407			`sampled_bit_q <=#Tp sampled_bit;`
408	7	mohor	`if (triple_sampling)`
409			`sampled_bit <=#Tp (sample[0] & sample[1]) \| ( sample[0] & rx) \| (sample[1] & rx);`
410			`else`
411			`sampled_bit <=#Tp rx;`
412			`end`
413	2	mohor	`end`
414	5	mohor	`else`
415	10	mohor	`sample_point <=#Tp 0;`
416	2	mohor	`end`
417
418
419
420	5	mohor	`/* Blocking synchronization (can occur only once in a bit time) */`
421	35	mohor
422	5	mohor	`always @ (posedge clk or posedge rst)`
423			`begin`
424			`if (rst)`
425			`sync_blocked <=#Tp 1'b0;`
426	78	mohor	`else if (clk_en_q)`
427	5	mohor	`begin`
428	100	mohor	`if (resync)`
429	5	mohor	`sync_blocked <=#Tp 1'b1;`
430	76	mohor	`else if (seg2 & (quant_cnt[2:0] == time_segment2))`
431	5	mohor	`sync_blocked <=#Tp 1'b0;`
432			`end`
433			`end`
434	2	mohor
435
436	100	mohor	`/* Blocking hard synchronization when occurs once or when we are transmitting a msg */`
437	24	mohor	`always @ (posedge clk or posedge rst)`
438			`begin`
439			`if (rst)`
440	100	mohor	`hard_sync_blocked <=#Tp 1'b0;`
441			`else if (hard_sync \| transmitting & tx_point)`
442			`hard_sync_blocked <=#Tp 1'b1;`
443			`else if (go_rx_inter)`
444			`hard_sync_blocked <=#Tp 1'b0;`
445	24	mohor	`end`
446	2	mohor
447
448	5	mohor
449	24	mohor
450
451	2	mohor	`endmodule`

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