URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Blame information for rev 141

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003, 2004 Authors                       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.28  2004/02/08 14:25:26  mohor
// Header changed.
//
// Revision 1.27  2003/09/30 00:55:13  mohor
// Error counters fixed to be compatible with Bosch VHDL reference model.
// Small synchronization changes.
//
// Revision 1.26  2003/09/25 18:55:49  mohor
// Synchronization changed, error counters fixed.
//
// Revision 1.25  2003/07/16 13:40:35  mohor
// Fixed according to the linter.
//
// Revision 1.24  2003/07/10 15:32:28  mohor
// Unused signal removed.
//
// Revision 1.23  2003/07/10 01:59:04  tadejm
// Synchronization fixed. In some strange cases it didn't work according to
// the VHDL reference model.
//
// Revision 1.22  2003/07/07 11:21:37  mohor
// Little fixes (to fix warnings).
//
// Revision 1.21  2003/07/03 09:32:20  mohor
// Synchronization changed.
//
// Revision 1.20  2003/06/20 14:51:11  mohor
// Previous change removed. When resynchronization occurs we go to seg1
// stage. sync stage does not cause another start of seg1 stage.
//
// Revision 1.19  2003/06/20 14:28:20  mohor
// When hard_sync or resync occure we need to go to seg1 segment. Going to
// sync segment is in that case blocked.
//
// Revision 1.18  2003/06/17 15:53:33  mohor
// clk_cnt reduced from [8:0] to [6:0].
//
// Revision 1.17  2003/06/17 14:32:17  mohor
// Removed few signals.
//
// Revision 1.16  2003/06/16 13:57:58  mohor
// tx_point generated one clk earlier. rx_i registered. Data corrected when
// using extended mode.
//
// Revision 1.15  2003/06/13 15:02:24  mohor
// Synchronization is also needed when transmitting a message.
//
// Revision 1.14  2003/06/13 14:55:11  mohor
// Counters width changed.
//
// Revision 1.13  2003/06/11 14:21:35  mohor
// When switching to tx, sync stage is overjumped.
//
// Revision 1.12  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.11  2003/02/09 18:40:29  mohor
// Overload fixed. Hard synchronization also enabled at the last bit of
// interframe.
//
// Revision 1.10  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.9  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.8  2003/01/10 17:51:34  mohor
// Temporary version (backup).
//
// Revision 1.7  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.6  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.5  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.4  2002/12/26 01:33:05  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:16  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:17:00  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
  tx,
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  sample_point,
  sampled_bit,
  sampled_bit_q,
  tx_point,
  hard_sync,
 
  /* Output from can_bsp module */
  rx_idle,
  rx_inter,
  transmitting,
  transmitter,
  go_rx_inter,
  tx_next,
 
  go_overload_frame,
  go_error_frame,
  go_tx,
  send_ack,
  node_error_passive
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
input         tx;
 
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output from can_bsp module */
input         rx_idle;
input         rx_inter;
input         transmitting;
input         transmitter;
input         go_rx_inter;
input         tx_next;
 
input         go_overload_frame;
input         go_error_frame;
input         go_tx;
input         send_ack;
input         node_error_passive;
 
/* Output signals from this module */
output        sample_point;
output        sampled_bit;
output        sampled_bit_q;
output        tx_point;
output        hard_sync;
 
reg     [6:0] clk_cnt;
reg           clk_en;
reg           clk_en_q;
reg           sync_blocked;
reg           hard_sync_blocked;
reg           sampled_bit;
reg           sampled_bit_q;
reg     [3:0] quant_cnt;
reg     [3:0] delay;
reg           sync;
reg           seg1;
reg           seg2;
reg           resync_latched;
reg           sample_point;
reg     [1:0] sample;
reg           tx_point;
reg           tx_next_sp;
 
wire          go_sync;
wire          go_seg1;
wire          go_seg2;
wire [7:0]    preset_cnt;
wire          sync_window;
wire          resync;
 
 
assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
assign hard_sync  =   (rx_idle | rx_inter)    & (~rx) & sampled_bit & (~hard_sync_blocked);  // Hard synchronization
assign resync     =  (~rx_idle) & (~rx_inter) & (~rx) & sampled_bit & (~sync_blocked);       // Re-synchronization
 
 
 
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_cnt <= 7'h0;
  else if (clk_cnt >= (preset_cnt-1'b1))
    clk_cnt <=#Tp 7'h0;
  else
    clk_cnt <=#Tp clk_cnt + 1'b1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en  <= 1'b0;
  else if ({1'b0, clk_cnt} == (preset_cnt-1'b1))
    clk_en  <=#Tp 1'b1;
  else
    clk_en  <=#Tp 1'b0;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en_q  <= 1'b0;
  else
    clk_en_q  <=#Tp clk_en;
end
 
 
 
/* Changing states */
assign go_sync = clk_en_q & seg2 & (quant_cnt[2:0] == time_segment2) & (~hard_sync) & (~resync);
assign go_seg1 = clk_en_q & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    tx_point <= 1'b0;
  else
    tx_point <=#Tp ~tx_point & seg2 & (  clk_en & (quant_cnt[2:0] == time_segment2)
                                       | (clk_en | clk_en_q) & (resync | hard_sync)
                                      );    // When transmitter we should transmit as soon as possible.
end
 
 
 
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
   SJW is reached */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_latched <= 1'b0;
  else if (resync & seg2 & (~sync_window))
    resync_latched <=#Tp 1'b1;
  else if (go_seg1)
    resync_latched <= 1'b0;
end
 
 
 
/* Synchronization stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync <= 1'b0;
  else if (clk_en_q)
    sync <=#Tp go_sync;
end
 
 
/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg1 <= 1'b1;
  else if (go_seg1)
    seg1 <=#Tp 1'b1;
  else if (go_seg2)
    seg1 <=#Tp 1'b0;
end
 
 
/* Seg2 stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg2 <= 1'b0;
  else if (go_seg2)
    seg2 <=#Tp 1'b1;
  else if (go_sync | go_seg1)
    seg2 <=#Tp 1'b0;
end
 
 
/* Quant counter */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    quant_cnt <= 4'h0;
  else if (go_sync | go_seg1 | go_seg2)
    quant_cnt <=#Tp 4'h0;
  else if (clk_en_q)
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
 
 
/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    delay <= 4'h0;
  else if (resync & seg1 & (~transmitting | transmitting & (tx_next_sp | (tx & (~rx)))))  // when transmitting 0 with positive error delay is set to 0
    delay <=#Tp (quant_cnt > {2'h0, sync_jump_width})? ({2'h0, sync_jump_width} + 1'b1) : (quant_cnt + 1'b1);
  else if (go_sync | go_seg1)
    delay <=#Tp 4'h0;
end
 
 
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
 
 
// Sampling data (memorizing two samples all the time).
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sample <= 2'b11;
  else if (clk_en_q)
    sample <= {sample[0], rx};
end
 
 
// When enabled, tripple sampling is done here.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1'b1;
      sampled_bit_q <= 1'b1;
      sample_point <= 1'b0;
    end
  else if (go_error_frame)
    begin
      sampled_bit_q <=#Tp sampled_bit;
      sample_point <=#Tp 1'b0;
    end
  else if (clk_en_q & (~hard_sync))
    begin
      if (seg1 & (quant_cnt == (time_segment1 + delay)))
        begin
          sample_point <=#Tp 1'b1;
          sampled_bit_q <=#Tp sampled_bit;
          if (triple_sampling)
            sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
          else
            sampled_bit <=#Tp rx;
        end
    end
  else
    sample_point <=#Tp 1'b0;
end
 
 
// tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we
// need to synchronize (even when we are a transmitter)
always @ (posedge clk or posedge rst)
begin
  if (rst)
    tx_next_sp <= 1'b0;
  else if (go_overload_frame | (go_error_frame & (~node_error_passive)) | go_tx | send_ack)
    tx_next_sp <=#Tp 1'b0;
  else if (go_error_frame & node_error_passive)
    tx_next_sp <=#Tp 1'b1;
  else if (sample_point)
    tx_next_sp <=#Tp tx_next;
end
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync_blocked <=#Tp 1'b1;
  else if (clk_en_q)
    begin
      if (resync)
        sync_blocked <=#Tp 1'b1;
      else if (go_seg2)
        sync_blocked <=#Tp 1'b0;
    end
end
 
 
/* Blocking hard synchronization when occurs once or when we are transmitting a msg */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    hard_sync_blocked <=#Tp 1'b0;
  else if (hard_sync & clk_en_q | (transmitting & transmitter | go_tx) & tx_point & (~tx_next))
    hard_sync_blocked <=#Tp 1'b1;
  else if (go_rx_inter | (rx_idle | rx_inter) & sample_point & sampled_bit)  // When a glitch performed synchronization
    hard_sync_blocked <=#Tp 1'b0;
end
 
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	137	mohor	`//// Copyright (C) 2002, 2003, 2004 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	2	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	141	igorm	`// Revision 1.28 2004/02/08 14:25:26 mohor`
54			`// Header changed.`
55			`//`
56	137	mohor	`// Revision 1.27 2003/09/30 00:55:13 mohor`
57			`// Error counters fixed to be compatible with Bosch VHDL reference model.`
58			`// Small synchronization changes.`
59			`//`
60	126	mohor	`// Revision 1.26 2003/09/25 18:55:49 mohor`
61			`// Synchronization changed, error counters fixed.`
62			`//`
63	125	mohor	`// Revision 1.25 2003/07/16 13:40:35 mohor`
64			`// Fixed according to the linter.`
65			`//`
66	108	mohor	`// Revision 1.24 2003/07/10 15:32:28 mohor`
67			`// Unused signal removed.`
68			`//`
69	106	mohor	`// Revision 1.23 2003/07/10 01:59:04 tadejm`
70			`// Synchronization fixed. In some strange cases it didn't work according to`
71			`// the VHDL reference model.`
72			`//`
73	104	tadejm	`// Revision 1.22 2003/07/07 11:21:37 mohor`
74			`// Little fixes (to fix warnings).`
75			`//`
76	102	mohor	`// Revision 1.21 2003/07/03 09:32:20 mohor`
77			`// Synchronization changed.`
78			`//`
79	100	mohor	`// Revision 1.20 2003/06/20 14:51:11 mohor`
80			`// Previous change removed. When resynchronization occurs we go to seg1`
81			`// stage. sync stage does not cause another start of seg1 stage.`
82			`//`
83	88	mohor	`// Revision 1.19 2003/06/20 14:28:20 mohor`
84			`// When hard_sync or resync occure we need to go to seg1 segment. Going to`
85			`// sync segment is in that case blocked.`
86			`//`
87	87	mohor	`// Revision 1.18 2003/06/17 15:53:33 mohor`
88			`// clk_cnt reduced from [8:0] to [6:0].`
89			`//`
90	84	mohor	`// Revision 1.17 2003/06/17 14:32:17 mohor`
91			`// Removed few signals.`
92			`//`
93	82	mohor	`// Revision 1.16 2003/06/16 13:57:58 mohor`
94			`// tx_point generated one clk earlier. rx_i registered. Data corrected when`
95			`// using extended mode.`
96			`//`
97	78	mohor	`// Revision 1.15 2003/06/13 15:02:24 mohor`
98			`// Synchronization is also needed when transmitting a message.`
99			`//`
100	77	mohor	`// Revision 1.14 2003/06/13 14:55:11 mohor`
101			`// Counters width changed.`
102			`//`
103	76	mohor	`// Revision 1.13 2003/06/11 14:21:35 mohor`
104			`// When switching to tx, sync stage is overjumped.`
105			`//`
106	75	mohor	`// Revision 1.12 2003/02/14 20:17:01 mohor`
107			`// Several registers added. Not finished, yet.`
108			`//`
109	35	mohor	`// Revision 1.11 2003/02/09 18:40:29 mohor`
110			`// Overload fixed. Hard synchronization also enabled at the last bit of`
111			`// interframe.`
112			`//`
113	29	mohor	`// Revision 1.10 2003/02/09 02:24:33 mohor`
114			`// Bosch license warning added. Error counters finished. Overload frames`
115			`// still need to be fixed.`
116			`//`
117	28	mohor	`// Revision 1.9 2003/01/31 01:13:38 mohor`
118			`// backup.`
119			`//`
120	24	mohor	`// Revision 1.8 2003/01/10 17:51:34 mohor`
121			`// Temporary version (backup).`
122			`//`
123	15	mohor	`// Revision 1.7 2003/01/08 02:10:53 mohor`
124			`// Acceptance filter added.`
125			`//`
126	11	mohor	`// Revision 1.6 2002/12/28 04:13:23 mohor`
127			`// Backup version.`
128			`//`
129	10	mohor	`// Revision 1.5 2002/12/27 00:12:52 mohor`
130			`// Header changed, testbench improved to send a frame (crc still missing).`
131			`//`
132	9	mohor	`// Revision 1.4 2002/12/26 01:33:05 mohor`
133			`// Tripple sampling supported.`
134			`//`
135	7	mohor	`// Revision 1.3 2002/12/25 23:44:16 mohor`
136			`// Commented lines removed.`
137			`//`
138	6	mohor	`// Revision 1.2 2002/12/25 14:17:00 mohor`
139			`// Synchronization working.`
140			`//`
141	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
142			`// Initial`
143	2	mohor	`//`
144			`//`
145	5	mohor	`//`
146	2	mohor
147			`// synopsys translate_off`
148			`include "timescale.v"
149			`// synopsys translate_on`
150			`include "can_defines.v"
151
152			`module can_btl`
153			`(`
154			`clk,`
155			`rst,`
156			`rx,`
157	125	mohor	`tx,`
158	2	mohor
159			`/* Bus Timing 0 register */`
160			`baud_r_presc,`
161			`sync_jump_width,`
162
163			`/* Bus Timing 1 register */`
164			`time_segment1,`
165			`time_segment2,`
166			`triple_sampling,`
167
168			`/* Output signals from this module */`
169	10	mohor	`sample_point,`
170			`sampled_bit,`
171			`sampled_bit_q,`
172	24	mohor	`tx_point,`
173	11	mohor	`hard_sync,`
174	2	mohor
175	10	mohor	`/* Output from can_bsp module */`
176	24	mohor	`rx_idle,`
177	126	mohor	`rx_inter,`
178	125	mohor	`transmitting,`
179			`transmitter,`
180			`go_rx_inter,`
181			`tx_next,`
182	2	mohor
183	125	mohor	`go_overload_frame,`
184			`go_error_frame,`
185			`go_tx,`
186			`send_ack,`
187			`node_error_passive`
188	2	mohor	`);`
189
190			`parameter Tp = 1;`
191
192			`input clk;`
193			`input rst;`
194			`input rx;`
195	125	mohor	`input tx;`
196	2	mohor
197
198			`/* Bus Timing 0 register */`
199			`input [5:0] baud_r_presc;`
200			`input [1:0] sync_jump_width;`
201
202			`/* Bus Timing 1 register */`
203			`input [3:0] time_segment1;`
204			`input [2:0] time_segment2;`
205			`input triple_sampling;`
206
207	10	mohor	`/* Output from can_bsp module */`
208			`input rx_idle;`
209	126	mohor	`input rx_inter;`
210	100	mohor	`input transmitting;`
211	125	mohor	`input transmitter;`
212			`input go_rx_inter;`
213			`input tx_next;`
214	10	mohor
215	125	mohor	`input go_overload_frame;`
216			`input go_error_frame;`
217			`input go_tx;`
218			`input send_ack;`
219			`input node_error_passive;`
220
221	2	mohor	`/* Output signals from this module */`
222	10	mohor	`output sample_point;`
223			`output sampled_bit;`
224			`output sampled_bit_q;`
225	24	mohor	`output tx_point;`
226	11	mohor	`output hard_sync;`
227	2	mohor
228	84	mohor	`reg [6:0] clk_cnt;`
229	2	mohor	`reg clk_en;`
230	78	mohor	`reg clk_en_q;`
231	5	mohor	`reg sync_blocked;`
232	100	mohor	`reg hard_sync_blocked;`
233	2	mohor	`reg sampled_bit;`
234	10	mohor	`reg sampled_bit_q;`
235	108	mohor	`reg [3:0] quant_cnt;`
236	6	mohor	`reg [3:0] delay;`
237			`reg sync;`
238			`reg seg1;`
239			`reg seg2;`
240			`reg resync_latched;`
241	10	mohor	`reg sample_point;`
242	7	mohor	`reg [1:0] sample;`
243	100	mohor	`reg tx_point;`
244	125	mohor	`reg tx_next_sp;`
245	2	mohor
246	125	mohor	`wire go_sync;`
247			`wire go_seg1;`
248			`wire go_seg2;`
249	108	mohor	`wire [7:0] preset_cnt;`
250	6	mohor	`wire sync_window;`
251	75	mohor	`wire resync;`
252	2	mohor
253	5	mohor
254	6	mohor	`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
255	126	mohor	`assign hard_sync = (rx_idle \| rx_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization`
256			`assign resync = (~rx_idle) & (~rx_inter) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization`
257	5	mohor
258
259	141	igorm
260	6	mohor	`/* Generating general enable signal that defines baud rate. */`
261	2	mohor	`always @ (posedge clk or posedge rst)`
262			`begin`
263			`if (rst)`
264	108	mohor	`clk_cnt <= 7'h0;`
265	78	mohor	`else if (clk_cnt >= (preset_cnt-1'b1))`
266	108	mohor	`clk_cnt <=#Tp 7'h0;`
267	10	mohor	`else`
268	76	mohor	`clk_cnt <=#Tp clk_cnt + 1'b1;`
269	10	mohor	`end`
270
271
272			`always @ (posedge clk or posedge rst)`
273			`begin`
274			`if (rst)`
275			`clk_en <= 1'b0;`
276	108	mohor	`else if ({1'b0, clk_cnt} == (preset_cnt-1'b1))`
277	10	mohor	`clk_en <=#Tp 1'b1;`
278	2	mohor	`else`
279	10	mohor	`clk_en <=#Tp 1'b0;`
280	2	mohor	`end`
281
282
283	5	mohor
284	78	mohor	`always @ (posedge clk or posedge rst)`
285			`begin`
286			`if (rst)`
287			`clk_en_q <= 1'b0;`
288			`else`
289			`clk_en_q <=#Tp clk_en;`
290			`end`
291
292
293
294	6	mohor	`/* Changing states */`
295	125	mohor	`assign go_sync = clk_en_q & seg2 & (quant_cnt[2:0] == time_segment2) & (~hard_sync) & (~resync);`
296			`assign go_seg1 = clk_en_q & (sync \| hard_sync \| (resync & seg2 & sync_window) \| (resync_latched & sync_window));`
297			`assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));`
298	5	mohor
299
300	76	mohor
301	100	mohor	`always @ (posedge clk or posedge rst)`
302			`begin`
303			`if (rst)`
304			`tx_point <= 1'b0;`
305			`else`
306	125	mohor	`tx_point <=#Tp ~tx_point & seg2 & ( clk_en & (quant_cnt[2:0] == time_segment2)`
307	141	igorm	`\| (clk_en \| clk_en_q) & (resync \| hard_sync)`
308	125	mohor	`); // When transmitter we should transmit as soon as possible.`
309	100	mohor	`end`
310
311
312	141	igorm
313	6	mohor	`/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when`
314			`SJW is reached */`
315	2	mohor	`always @ (posedge clk or posedge rst)`
316			`begin`
317			`if (rst)`
318	5	mohor	`resync_latched <= 1'b0;`
319	6	mohor	`else if (resync & seg2 & (~sync_window))`
320	5	mohor	`resync_latched <=#Tp 1'b1;`
321			`else if (go_seg1)`
322			`resync_latched <= 1'b0;`
323			`end`
324
325
326
327	6	mohor	`/* Synchronization stage/segment */`
328	5	mohor	`always @ (posedge clk or posedge rst)`
329			`begin`
330			`if (rst)`
331	108	mohor	`sync <= 1'b0;`
332	125	mohor	`else if (clk_en_q)`
333			`sync <=#Tp go_sync;`
334	5	mohor	`end`
335
336
337	6	mohor	`/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */`
338	5	mohor	`always @ (posedge clk or posedge rst)`
339			`begin`
340			`if (rst)`
341	108	mohor	`seg1 <= 1'b1;`
342	5	mohor	`else if (go_seg1)`
343			`seg1 <=#Tp 1'b1;`
344			`else if (go_seg2)`
345			`seg1 <=#Tp 1'b0;`
346			`end`
347
348
349	6	mohor	`/* Seg2 stage/segment */`
350	5	mohor	`always @ (posedge clk or posedge rst)`
351			`begin`
352			`if (rst)`
353	108	mohor	`seg2 <= 1'b0;`
354	5	mohor	`else if (go_seg2)`
355			`seg2 <=#Tp 1'b1;`
356			`else if (go_sync \| go_seg1)`
357			`seg2 <=#Tp 1'b0;`
358			`end`
359
360
361	6	mohor	`/* Quant counter */`
362	5	mohor	`always @ (posedge clk or posedge rst)`
363			`begin`
364			`if (rst)`
365	108	mohor	`quant_cnt <= 4'h0;`
366			`else if (go_sync \| go_seg1 \| go_seg2)`
367			`quant_cnt <=#Tp 4'h0;`
368	78	mohor	`else if (clk_en_q)`
369	5	mohor	`quant_cnt <=#Tp quant_cnt + 1'b1;`
370			`end`
371
372
373	6	mohor	`/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */`
374	5	mohor	`always @ (posedge clk or posedge rst)`
375			`begin`
376			`if (rst)`
377	108	mohor	`delay <= 4'h0;`
378	125	mohor	`else if (resync & seg1 & (~transmitting \| transmitting & (tx_next_sp \| (tx & (~rx))))) // when transmitting 0 with positive error delay is set to 0`
379	108	mohor	`delay <=#Tp (quant_cnt > {2'h0, sync_jump_width})? ({2'h0, sync_jump_width} + 1'b1) : (quant_cnt + 1'b1);`
380	5	mohor	`else if (go_sync \| go_seg1)`
381	108	mohor	`delay <=#Tp 4'h0;`
382	5	mohor	`end`
383
384
385	6	mohor	`// If early edge appears within this window (in seg2 stage), phase error is fully compensated`
386	76	mohor	`assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));`
387	5	mohor
388
389	7	mohor	`// Sampling data (memorizing two samples all the time).`
390	5	mohor	`always @ (posedge clk or posedge rst)`
391			`begin`
392			`if (rst)`
393	7	mohor	`sample <= 2'b11;`
394	78	mohor	`else if (clk_en_q)`
395	7	mohor	`sample <= {sample[0], rx};`
396			`end`
397
398
399			`// When enabled, tripple sampling is done here.`
400			`always @ (posedge clk or posedge rst)`
401			`begin`
402			`if (rst)`
403	2	mohor	`begin`
404	108	mohor	`sampled_bit <= 1'b1;`
405			`sampled_bit_q <= 1'b1;`
406			`sample_point <= 1'b0;`
407	2	mohor	`end`
408	141	igorm	`else if (go_error_frame)`
409			`begin`
410			`sampled_bit_q <=#Tp sampled_bit;`
411			`sample_point <=#Tp 1'b0;`
412			`end`
413	78	mohor	`else if (clk_en_q & (~hard_sync))`
414	2	mohor	`begin`
415	7	mohor	`if (seg1 & (quant_cnt == (time_segment1 + delay)))`
416			`begin`
417	108	mohor	`sample_point <=#Tp 1'b1;`
418	10	mohor	`sampled_bit_q <=#Tp sampled_bit;`
419	7	mohor	`if (triple_sampling)`
420			`sampled_bit <=#Tp (sample[0] & sample[1]) \| ( sample[0] & rx) \| (sample[1] & rx);`
421			`else`
422			`sampled_bit <=#Tp rx;`
423			`end`
424	2	mohor	`end`
425	5	mohor	`else`
426	108	mohor	`sample_point <=#Tp 1'b0;`
427	2	mohor	`end`
428
429
430	125	mohor	`// tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we`
431			`// need to synchronize (even when we are a transmitter)`
432			`always @ (posedge clk or posedge rst)`
433			`begin`
434			`if (rst)`
435			`tx_next_sp <= 1'b0;`
436			`else if (go_overload_frame \| (go_error_frame & (~node_error_passive)) \| go_tx \| send_ack)`
437			`tx_next_sp <=#Tp 1'b0;`
438			`else if (go_error_frame & node_error_passive)`
439			`tx_next_sp <=#Tp 1'b1;`
440			`else if (sample_point)`
441			`tx_next_sp <=#Tp tx_next;`
442			`end`
443	2	mohor
444	125	mohor
445
446	5	mohor	`/* Blocking synchronization (can occur only once in a bit time) */`
447	35	mohor
448	5	mohor	`always @ (posedge clk or posedge rst)`
449			`begin`
450			`if (rst)`
451	104	tadejm	`sync_blocked <=#Tp 1'b1;`
452	78	mohor	`else if (clk_en_q)`
453	5	mohor	`begin`
454	100	mohor	`if (resync)`
455	5	mohor	`sync_blocked <=#Tp 1'b1;`
456	104	tadejm	`else if (go_seg2)`
457	5	mohor	`sync_blocked <=#Tp 1'b0;`
458			`end`
459			`end`
460	2	mohor
461
462	100	mohor	`/* Blocking hard synchronization when occurs once or when we are transmitting a msg */`
463	24	mohor	`always @ (posedge clk or posedge rst)`
464			`begin`
465			`if (rst)`
466	100	mohor	`hard_sync_blocked <=#Tp 1'b0;`
467	141	igorm	`else if (hard_sync & clk_en_q \| (transmitting & transmitter \| go_tx) & tx_point & (~tx_next))`
468	100	mohor	`hard_sync_blocked <=#Tp 1'b1;`
469	126	mohor	`else if (go_rx_inter \| (rx_idle \| rx_inter) & sample_point & sampled_bit) // When a glitch performed synchronization`
470	100	mohor	`hard_sync_blocked <=#Tp 1'b0;`
471	24	mohor	`end`
472	2	mohor
473
474	5	mohor
475	24	mohor
476
477	2	mohor	`endmodule`
478	141	igorm

Browse

Tools

Subversion Repositories can

[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Blame information for rev 141