URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Blame information for rev 161

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003, 2004 Authors                       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.29  2004/05/12 15:58:41  igorm
// Core improved to pass all tests with the Bosch VHDL Reference system.
//
// Revision 1.28  2004/02/08 14:25:26  mohor
// Header changed.
//
// Revision 1.27  2003/09/30 00:55:13  mohor
// Error counters fixed to be compatible with Bosch VHDL reference model.
// Small synchronization changes.
//
// Revision 1.26  2003/09/25 18:55:49  mohor
// Synchronization changed, error counters fixed.
//
// Revision 1.25  2003/07/16 13:40:35  mohor
// Fixed according to the linter.
//
// Revision 1.24  2003/07/10 15:32:28  mohor
// Unused signal removed.
//
// Revision 1.23  2003/07/10 01:59:04  tadejm
// Synchronization fixed. In some strange cases it didn't work according to
// the VHDL reference model.
//
// Revision 1.22  2003/07/07 11:21:37  mohor
// Little fixes (to fix warnings).
//
// Revision 1.21  2003/07/03 09:32:20  mohor
// Synchronization changed.
//
// Revision 1.20  2003/06/20 14:51:11  mohor
// Previous change removed. When resynchronization occurs we go to seg1
// stage. sync stage does not cause another start of seg1 stage.
//
// Revision 1.19  2003/06/20 14:28:20  mohor
// When hard_sync or resync occure we need to go to seg1 segment. Going to
// sync segment is in that case blocked.
//
// Revision 1.18  2003/06/17 15:53:33  mohor
// clk_cnt reduced from [8:0] to [6:0].
//
// Revision 1.17  2003/06/17 14:32:17  mohor
// Removed few signals.
//
// Revision 1.16  2003/06/16 13:57:58  mohor
// tx_point generated one clk earlier. rx_i registered. Data corrected when
// using extended mode.
//
// Revision 1.15  2003/06/13 15:02:24  mohor
// Synchronization is also needed when transmitting a message.
//
// Revision 1.14  2003/06/13 14:55:11  mohor
// Counters width changed.
//
// Revision 1.13  2003/06/11 14:21:35  mohor
// When switching to tx, sync stage is overjumped.
//
// Revision 1.12  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.11  2003/02/09 18:40:29  mohor
// Overload fixed. Hard synchronization also enabled at the last bit of
// interframe.
//
// Revision 1.10  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.9  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.8  2003/01/10 17:51:34  mohor
// Temporary version (backup).
//
// Revision 1.7  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.6  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.5  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.4  2002/12/26 01:33:05  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:16  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:17:00  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
  tx,
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  sample_point,
  sampled_bit,
  sampled_bit_q,
  tx_point,
  hard_sync,
 
  /* Output from can_bsp module */
  rx_idle,
  rx_inter,
  transmitting,
  transmitter,
  go_rx_inter,
  tx_next,
 
  go_overload_frame,
  go_error_frame,
  go_tx,
  send_ack,
  node_error_passive
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
input         tx;
 
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output from can_bsp module */
input         rx_idle;
input         rx_inter;
input         transmitting;
input         transmitter;
input         go_rx_inter;
input         tx_next;
 
input         go_overload_frame;
input         go_error_frame;
input         go_tx;
input         send_ack;
input         node_error_passive;
 
/* Output signals from this module */
output        sample_point;
output        sampled_bit;
output        sampled_bit_q;
output        tx_point;
output        hard_sync;
 
reg     [6:0] clk_cnt;
reg           clk_en;
reg           clk_en_q;
reg           sync_blocked;
reg           hard_sync_blocked;
reg           sampled_bit;
reg           sampled_bit_q;
reg     [4:0] quant_cnt;
reg     [3:0] delay;
reg           sync;
reg           seg1;
reg           seg2;
reg           resync_latched;
reg           sample_point;
reg     [1:0] sample;
reg           tx_point;
reg           tx_next_sp;
 
wire          go_sync;
wire          go_seg1;
wire          go_seg2;
wire [7:0]    preset_cnt;
wire          sync_window;
wire          resync;
 
 
assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
assign hard_sync  =   (rx_idle | rx_inter)    & (~rx) & sampled_bit & (~hard_sync_blocked);  // Hard synchronization
assign resync     =  (~rx_idle) & (~rx_inter) & (~rx) & sampled_bit & (~sync_blocked);       // Re-synchronization
 
 
 
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_cnt <= 7'h0;
  else if (clk_cnt >= (preset_cnt-1'b1))
    clk_cnt <=#Tp 7'h0;
  else
    clk_cnt <=#Tp clk_cnt + 1'b1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en  <= 1'b0;
  else if ({1'b0, clk_cnt} == (preset_cnt-1'b1))
    clk_en  <=#Tp 1'b1;
  else
    clk_en  <=#Tp 1'b0;
end
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en_q  <= 1'b0;
  else
    clk_en_q  <=#Tp clk_en;
end
 
 
 
/* Changing states */
assign go_sync = clk_en_q & seg2 & (quant_cnt[2:0] == time_segment2) & (~hard_sync) & (~resync);
assign go_seg1 = clk_en_q & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
 
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    tx_point <= 1'b0;
  else
    tx_point <=#Tp ~tx_point & seg2 & (  clk_en & (quant_cnt[2:0] == time_segment2)
                                       | (clk_en | clk_en_q) & (resync | hard_sync)
                                      );    // When transmitter we should transmit as soon as possible.
end
 
 
 
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
   SJW is reached */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_latched <= 1'b0;
  else if (resync & seg2 & (~sync_window))
    resync_latched <=#Tp 1'b1;
  else if (go_seg1)
    resync_latched <= 1'b0;
end
 
 
 
/* Synchronization stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync <= 1'b0;
  else if (clk_en_q)
    sync <=#Tp go_sync;
end
 
 
/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg1 <= 1'b1;
  else if (go_seg1)
    seg1 <=#Tp 1'b1;
  else if (go_seg2)
    seg1 <=#Tp 1'b0;
end
 
 
/* Seg2 stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg2 <= 1'b0;
  else if (go_seg2)
    seg2 <=#Tp 1'b1;
  else if (go_sync | go_seg1)
    seg2 <=#Tp 1'b0;
end
 
 
/* Quant counter */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    quant_cnt <= 5'h0;
  else if (go_sync | go_seg1 | go_seg2)
    quant_cnt <=#Tp 5'h0;
  else if (clk_en_q)
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
 
 
/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    delay <= 4'h0;
  else if (resync & seg1 & (~transmitting | transmitting & (tx_next_sp | (tx & (~rx)))))  // when transmitting 0 with positive error delay is set to 0
    delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? ({2'h0, sync_jump_width} + 1'b1) : (quant_cnt + 1'b1);
  else if (go_sync | go_seg1)
    delay <=#Tp 4'h0;
end
 
 
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
 
 
// Sampling data (memorizing two samples all the time).
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sample <= 2'b11;
  else if (clk_en_q)
    sample <= {sample[0], rx};
end
 
 
// When enabled, tripple sampling is done here.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1'b1;
      sampled_bit_q <= 1'b1;
      sample_point <= 1'b0;
    end
  else if (go_error_frame)
    begin
      sampled_bit_q <=#Tp sampled_bit;
      sample_point <=#Tp 1'b0;
    end
  else if (clk_en_q & (~hard_sync))
    begin
      if (seg1 & (quant_cnt == (time_segment1 + delay)))
        begin
          sample_point <=#Tp 1'b1;
          sampled_bit_q <=#Tp sampled_bit;
          if (triple_sampling)
            sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
          else
            sampled_bit <=#Tp rx;
        end
    end
  else
    sample_point <=#Tp 1'b0;
end
 
 
// tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we
// need to synchronize (even when we are a transmitter)
always @ (posedge clk or posedge rst)
begin
  if (rst)
    tx_next_sp <= 1'b0;
  else if (go_overload_frame | (go_error_frame & (~node_error_passive)) | go_tx | send_ack)
    tx_next_sp <=#Tp 1'b0;
  else if (go_error_frame & node_error_passive)
    tx_next_sp <=#Tp 1'b1;
  else if (sample_point)
    tx_next_sp <=#Tp tx_next;
end
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync_blocked <=#Tp 1'b1;
  else if (clk_en_q)
    begin
      if (resync)
        sync_blocked <=#Tp 1'b1;
      else if (go_seg2)
        sync_blocked <=#Tp 1'b0;
    end
end
 
 
/* Blocking hard synchronization when occurs once or when we are transmitting a msg */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    hard_sync_blocked <=#Tp 1'b0;
  else if (hard_sync & clk_en_q | (transmitting & transmitter | go_tx) & tx_point & (~tx_next))
    hard_sync_blocked <=#Tp 1'b1;
  else if (go_rx_inter | (rx_idle | rx_inter) & sample_point & sampled_bit)  // When a glitch performed synchronization
    hard_sync_blocked <=#Tp 1'b0;
end
 
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	137	mohor	`//// Copyright (C) 2002, 2003, 2004 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	2	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	149	igorm	`// Revision 1.29 2004/05/12 15:58:41 igorm`
54			`// Core improved to pass all tests with the Bosch VHDL Reference system.`
55			`//`
56	141	igorm	`// Revision 1.28 2004/02/08 14:25:26 mohor`
57			`// Header changed.`
58			`//`
59	137	mohor	`// Revision 1.27 2003/09/30 00:55:13 mohor`
60			`// Error counters fixed to be compatible with Bosch VHDL reference model.`
61			`// Small synchronization changes.`
62			`//`
63	126	mohor	`// Revision 1.26 2003/09/25 18:55:49 mohor`
64			`// Synchronization changed, error counters fixed.`
65			`//`
66	125	mohor	`// Revision 1.25 2003/07/16 13:40:35 mohor`
67			`// Fixed according to the linter.`
68			`//`
69	108	mohor	`// Revision 1.24 2003/07/10 15:32:28 mohor`
70			`// Unused signal removed.`
71			`//`
72	106	mohor	`// Revision 1.23 2003/07/10 01:59:04 tadejm`
73			`// Synchronization fixed. In some strange cases it didn't work according to`
74			`// the VHDL reference model.`
75			`//`
76	104	tadejm	`// Revision 1.22 2003/07/07 11:21:37 mohor`
77			`// Little fixes (to fix warnings).`
78			`//`
79	102	mohor	`// Revision 1.21 2003/07/03 09:32:20 mohor`
80			`// Synchronization changed.`
81			`//`
82	100	mohor	`// Revision 1.20 2003/06/20 14:51:11 mohor`
83			`// Previous change removed. When resynchronization occurs we go to seg1`
84			`// stage. sync stage does not cause another start of seg1 stage.`
85			`//`
86	88	mohor	`// Revision 1.19 2003/06/20 14:28:20 mohor`
87			`// When hard_sync or resync occure we need to go to seg1 segment. Going to`
88			`// sync segment is in that case blocked.`
89			`//`
90	87	mohor	`// Revision 1.18 2003/06/17 15:53:33 mohor`
91			`// clk_cnt reduced from [8:0] to [6:0].`
92			`//`
93	84	mohor	`// Revision 1.17 2003/06/17 14:32:17 mohor`
94			`// Removed few signals.`
95			`//`
96	82	mohor	`// Revision 1.16 2003/06/16 13:57:58 mohor`
97			`// tx_point generated one clk earlier. rx_i registered. Data corrected when`
98			`// using extended mode.`
99			`//`
100	78	mohor	`// Revision 1.15 2003/06/13 15:02:24 mohor`
101			`// Synchronization is also needed when transmitting a message.`
102			`//`
103	77	mohor	`// Revision 1.14 2003/06/13 14:55:11 mohor`
104			`// Counters width changed.`
105			`//`
106	76	mohor	`// Revision 1.13 2003/06/11 14:21:35 mohor`
107			`// When switching to tx, sync stage is overjumped.`
108			`//`
109	75	mohor	`// Revision 1.12 2003/02/14 20:17:01 mohor`
110			`// Several registers added. Not finished, yet.`
111			`//`
112	35	mohor	`// Revision 1.11 2003/02/09 18:40:29 mohor`
113			`// Overload fixed. Hard synchronization also enabled at the last bit of`
114			`// interframe.`
115			`//`
116	29	mohor	`// Revision 1.10 2003/02/09 02:24:33 mohor`
117			`// Bosch license warning added. Error counters finished. Overload frames`
118			`// still need to be fixed.`
119			`//`
120	28	mohor	`// Revision 1.9 2003/01/31 01:13:38 mohor`
121			`// backup.`
122			`//`
123	24	mohor	`// Revision 1.8 2003/01/10 17:51:34 mohor`
124			`// Temporary version (backup).`
125			`//`
126	15	mohor	`// Revision 1.7 2003/01/08 02:10:53 mohor`
127			`// Acceptance filter added.`
128			`//`
129	11	mohor	`// Revision 1.6 2002/12/28 04:13:23 mohor`
130			`// Backup version.`
131			`//`
132	10	mohor	`// Revision 1.5 2002/12/27 00:12:52 mohor`
133			`// Header changed, testbench improved to send a frame (crc still missing).`
134			`//`
135	9	mohor	`// Revision 1.4 2002/12/26 01:33:05 mohor`
136			`// Tripple sampling supported.`
137			`//`
138	7	mohor	`// Revision 1.3 2002/12/25 23:44:16 mohor`
139			`// Commented lines removed.`
140			`//`
141	6	mohor	`// Revision 1.2 2002/12/25 14:17:00 mohor`
142			`// Synchronization working.`
143			`//`
144	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
145			`// Initial`
146	2	mohor	`//`
147			`//`
148	5	mohor	`//`
149	2	mohor
150			`// synopsys translate_off`
151			`include "timescale.v"
152			`// synopsys translate_on`
153			`include "can_defines.v"
154
155			`module can_btl`
156			`(`
157			`clk,`
158			`rst,`
159			`rx,`
160	125	mohor	`tx,`
161	2	mohor
162			`/* Bus Timing 0 register */`
163			`baud_r_presc,`
164			`sync_jump_width,`
165
166			`/* Bus Timing 1 register */`
167			`time_segment1,`
168			`time_segment2,`
169			`triple_sampling,`
170
171			`/* Output signals from this module */`
172	10	mohor	`sample_point,`
173			`sampled_bit,`
174			`sampled_bit_q,`
175	24	mohor	`tx_point,`
176	11	mohor	`hard_sync,`
177	2	mohor
178	10	mohor	`/* Output from can_bsp module */`
179	24	mohor	`rx_idle,`
180	126	mohor	`rx_inter,`
181	125	mohor	`transmitting,`
182			`transmitter,`
183			`go_rx_inter,`
184			`tx_next,`
185	2	mohor
186	125	mohor	`go_overload_frame,`
187			`go_error_frame,`
188			`go_tx,`
189			`send_ack,`
190			`node_error_passive`
191	2	mohor	`);`
192
193			`parameter Tp = 1;`
194
195			`input clk;`
196			`input rst;`
197			`input rx;`
198	125	mohor	`input tx;`
199	2	mohor
200
201			`/* Bus Timing 0 register */`
202			`input [5:0] baud_r_presc;`
203			`input [1:0] sync_jump_width;`
204
205			`/* Bus Timing 1 register */`
206			`input [3:0] time_segment1;`
207			`input [2:0] time_segment2;`
208			`input triple_sampling;`
209
210	10	mohor	`/* Output from can_bsp module */`
211			`input rx_idle;`
212	126	mohor	`input rx_inter;`
213	100	mohor	`input transmitting;`
214	125	mohor	`input transmitter;`
215			`input go_rx_inter;`
216			`input tx_next;`
217	10	mohor
218	125	mohor	`input go_overload_frame;`
219			`input go_error_frame;`
220			`input go_tx;`
221			`input send_ack;`
222			`input node_error_passive;`
223
224	2	mohor	`/* Output signals from this module */`
225	10	mohor	`output sample_point;`
226			`output sampled_bit;`
227			`output sampled_bit_q;`
228	24	mohor	`output tx_point;`
229	11	mohor	`output hard_sync;`
230	2	mohor
231	84	mohor	`reg [6:0] clk_cnt;`
232	2	mohor	`reg clk_en;`
233	78	mohor	`reg clk_en_q;`
234	5	mohor	`reg sync_blocked;`
235	100	mohor	`reg hard_sync_blocked;`
236	2	mohor	`reg sampled_bit;`
237	10	mohor	`reg sampled_bit_q;`
238	149	igorm	`reg [4:0] quant_cnt;`
239	6	mohor	`reg [3:0] delay;`
240			`reg sync;`
241			`reg seg1;`
242			`reg seg2;`
243			`reg resync_latched;`
244	10	mohor	`reg sample_point;`
245	7	mohor	`reg [1:0] sample;`
246	100	mohor	`reg tx_point;`
247	125	mohor	`reg tx_next_sp;`
248	2	mohor
249	125	mohor	`wire go_sync;`
250			`wire go_seg1;`
251			`wire go_seg2;`
252	108	mohor	`wire [7:0] preset_cnt;`
253	6	mohor	`wire sync_window;`
254	75	mohor	`wire resync;`
255	2	mohor
256	5	mohor
257	6	mohor	`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
258	126	mohor	`assign hard_sync = (rx_idle \| rx_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization`
259			`assign resync = (~rx_idle) & (~rx_inter) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization`
260	5	mohor
261
262	141	igorm
263	6	mohor	`/* Generating general enable signal that defines baud rate. */`
264	2	mohor	`always @ (posedge clk or posedge rst)`
265			`begin`
266			`if (rst)`
267	108	mohor	`clk_cnt <= 7'h0;`
268	78	mohor	`else if (clk_cnt >= (preset_cnt-1'b1))`
269	108	mohor	`clk_cnt <=#Tp 7'h0;`
270	10	mohor	`else`
271	76	mohor	`clk_cnt <=#Tp clk_cnt + 1'b1;`
272	10	mohor	`end`
273
274
275			`always @ (posedge clk or posedge rst)`
276			`begin`
277			`if (rst)`
278			`clk_en <= 1'b0;`
279	108	mohor	`else if ({1'b0, clk_cnt} == (preset_cnt-1'b1))`
280	10	mohor	`clk_en <=#Tp 1'b1;`
281	2	mohor	`else`
282	10	mohor	`clk_en <=#Tp 1'b0;`
283	2	mohor	`end`
284
285
286	5	mohor
287	78	mohor	`always @ (posedge clk or posedge rst)`
288			`begin`
289			`if (rst)`
290			`clk_en_q <= 1'b0;`
291			`else`
292			`clk_en_q <=#Tp clk_en;`
293			`end`
294
295
296
297	6	mohor	`/* Changing states */`
298	125	mohor	`assign go_sync = clk_en_q & seg2 & (quant_cnt[2:0] == time_segment2) & (~hard_sync) & (~resync);`
299			`assign go_seg1 = clk_en_q & (sync \| hard_sync \| (resync & seg2 & sync_window) \| (resync_latched & sync_window));`
300			`assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));`
301	5	mohor
302
303	76	mohor
304	100	mohor	`always @ (posedge clk or posedge rst)`
305			`begin`
306			`if (rst)`
307			`tx_point <= 1'b0;`
308			`else`
309	125	mohor	`tx_point <=#Tp ~tx_point & seg2 & ( clk_en & (quant_cnt[2:0] == time_segment2)`
310	141	igorm	`\| (clk_en \| clk_en_q) & (resync \| hard_sync)`
311	125	mohor	`); // When transmitter we should transmit as soon as possible.`
312	100	mohor	`end`
313
314
315	141	igorm
316	6	mohor	`/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when`
317			`SJW is reached */`
318	2	mohor	`always @ (posedge clk or posedge rst)`
319			`begin`
320			`if (rst)`
321	5	mohor	`resync_latched <= 1'b0;`
322	6	mohor	`else if (resync & seg2 & (~sync_window))`
323	5	mohor	`resync_latched <=#Tp 1'b1;`
324			`else if (go_seg1)`
325			`resync_latched <= 1'b0;`
326			`end`
327
328
329
330	6	mohor	`/* Synchronization stage/segment */`
331	5	mohor	`always @ (posedge clk or posedge rst)`
332			`begin`
333			`if (rst)`
334	108	mohor	`sync <= 1'b0;`
335	125	mohor	`else if (clk_en_q)`
336			`sync <=#Tp go_sync;`
337	5	mohor	`end`
338
339
340	6	mohor	`/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */`
341	5	mohor	`always @ (posedge clk or posedge rst)`
342			`begin`
343			`if (rst)`
344	108	mohor	`seg1 <= 1'b1;`
345	5	mohor	`else if (go_seg1)`
346			`seg1 <=#Tp 1'b1;`
347			`else if (go_seg2)`
348			`seg1 <=#Tp 1'b0;`
349			`end`
350
351
352	6	mohor	`/* Seg2 stage/segment */`
353	5	mohor	`always @ (posedge clk or posedge rst)`
354			`begin`
355			`if (rst)`
356	108	mohor	`seg2 <= 1'b0;`
357	5	mohor	`else if (go_seg2)`
358			`seg2 <=#Tp 1'b1;`
359			`else if (go_sync \| go_seg1)`
360			`seg2 <=#Tp 1'b0;`
361			`end`
362
363
364	6	mohor	`/* Quant counter */`
365	5	mohor	`always @ (posedge clk or posedge rst)`
366			`begin`
367			`if (rst)`
368	149	igorm	`quant_cnt <= 5'h0;`
369	108	mohor	`else if (go_sync \| go_seg1 \| go_seg2)`
370	149	igorm	`quant_cnt <=#Tp 5'h0;`
371	78	mohor	`else if (clk_en_q)`
372	5	mohor	`quant_cnt <=#Tp quant_cnt + 1'b1;`
373			`end`
374
375
376	6	mohor	`/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */`
377	5	mohor	`always @ (posedge clk or posedge rst)`
378			`begin`
379			`if (rst)`
380	108	mohor	`delay <= 4'h0;`
381	125	mohor	`else if (resync & seg1 & (~transmitting \| transmitting & (tx_next_sp \| (tx & (~rx))))) // when transmitting 0 with positive error delay is set to 0`
382	149	igorm	`delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? ({2'h0, sync_jump_width} + 1'b1) : (quant_cnt + 1'b1);`
383	5	mohor	`else if (go_sync \| go_seg1)`
384	108	mohor	`delay <=#Tp 4'h0;`
385	5	mohor	`end`
386
387
388	6	mohor	`// If early edge appears within this window (in seg2 stage), phase error is fully compensated`
389	76	mohor	`assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));`
390	5	mohor
391
392	7	mohor	`// Sampling data (memorizing two samples all the time).`
393	5	mohor	`always @ (posedge clk or posedge rst)`
394			`begin`
395			`if (rst)`
396	7	mohor	`sample <= 2'b11;`
397	78	mohor	`else if (clk_en_q)`
398	7	mohor	`sample <= {sample[0], rx};`
399			`end`
400
401
402			`// When enabled, tripple sampling is done here.`
403			`always @ (posedge clk or posedge rst)`
404			`begin`
405			`if (rst)`
406	2	mohor	`begin`
407	108	mohor	`sampled_bit <= 1'b1;`
408			`sampled_bit_q <= 1'b1;`
409			`sample_point <= 1'b0;`
410	2	mohor	`end`
411	141	igorm	`else if (go_error_frame)`
412			`begin`
413			`sampled_bit_q <=#Tp sampled_bit;`
414			`sample_point <=#Tp 1'b0;`
415			`end`
416	78	mohor	`else if (clk_en_q & (~hard_sync))`
417	2	mohor	`begin`
418	7	mohor	`if (seg1 & (quant_cnt == (time_segment1 + delay)))`
419			`begin`
420	108	mohor	`sample_point <=#Tp 1'b1;`
421	10	mohor	`sampled_bit_q <=#Tp sampled_bit;`
422	7	mohor	`if (triple_sampling)`
423			`sampled_bit <=#Tp (sample[0] & sample[1]) \| ( sample[0] & rx) \| (sample[1] & rx);`
424			`else`
425			`sampled_bit <=#Tp rx;`
426			`end`
427	2	mohor	`end`
428	5	mohor	`else`
429	108	mohor	`sample_point <=#Tp 1'b0;`
430	2	mohor	`end`
431
432
433	125	mohor	`// tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we`
434			`// need to synchronize (even when we are a transmitter)`
435			`always @ (posedge clk or posedge rst)`
436			`begin`
437			`if (rst)`
438			`tx_next_sp <= 1'b0;`
439			`else if (go_overload_frame \| (go_error_frame & (~node_error_passive)) \| go_tx \| send_ack)`
440			`tx_next_sp <=#Tp 1'b0;`
441			`else if (go_error_frame & node_error_passive)`
442			`tx_next_sp <=#Tp 1'b1;`
443			`else if (sample_point)`
444			`tx_next_sp <=#Tp tx_next;`
445			`end`
446	2	mohor
447	125	mohor
448
449	5	mohor	`/* Blocking synchronization (can occur only once in a bit time) */`
450	35	mohor
451	5	mohor	`always @ (posedge clk or posedge rst)`
452			`begin`
453			`if (rst)`
454	104	tadejm	`sync_blocked <=#Tp 1'b1;`
455	78	mohor	`else if (clk_en_q)`
456	5	mohor	`begin`
457	100	mohor	`if (resync)`
458	5	mohor	`sync_blocked <=#Tp 1'b1;`
459	104	tadejm	`else if (go_seg2)`
460	5	mohor	`sync_blocked <=#Tp 1'b0;`
461			`end`
462			`end`
463	2	mohor
464
465	100	mohor	`/* Blocking hard synchronization when occurs once or when we are transmitting a msg */`
466	24	mohor	`always @ (posedge clk or posedge rst)`
467			`begin`
468			`if (rst)`
469	100	mohor	`hard_sync_blocked <=#Tp 1'b0;`
470	141	igorm	`else if (hard_sync & clk_en_q \| (transmitting & transmitter \| go_tx) & tx_point & (~tx_next))`
471	100	mohor	`hard_sync_blocked <=#Tp 1'b1;`
472	126	mohor	`else if (go_rx_inter \| (rx_idle \| rx_inter) & sample_point & sampled_bit) // When a glitch performed synchronization`
473	100	mohor	`hard_sync_blocked <=#Tp 1'b0;`
474	24	mohor	`end`
475	2	mohor
476
477	5	mohor
478	24	mohor
479
480	2	mohor	`endmodule`
481	141	igorm

Browse

Tools

Subversion Repositories can

[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Blame information for rev 161