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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_btl.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11  2003/02/09 18:40:29  mohor
// Overload fixed. Hard synchronization also enabled at the last bit of
// interframe.
//
// Revision 1.10  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.9  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.8  2003/01/10 17:51:34  mohor
// Temporary version (backup).
//
// Revision 1.7  2003/01/08 02:10:53  mohor
// Acceptance filter added.
//
// Revision 1.6  2002/12/28 04:13:23  mohor
// Backup version.
//
// Revision 1.5  2002/12/27 00:12:52  mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.4  2002/12/26 01:33:05  mohor
// Tripple sampling supported.
//
// Revision 1.3  2002/12/25 23:44:16  mohor
// Commented lines removed.
//
// Revision 1.2  2002/12/25 14:17:00  mohor
// Synchronization working.
//
// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
// Initial
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_btl
(
  clk,
  rst,
  rx,
 
  /* Mode register */
  reset_mode,
 
  /* Bus Timing 0 register */
  baud_r_presc,
  sync_jump_width,
 
  /* Bus Timing 1 register */
  time_segment1,
  time_segment2,
  triple_sampling,
 
  /* Output signals from this module */
  clk_en,
  sample_point,
  sampled_bit,
  sampled_bit_q,
  tx_point,
  hard_sync,
  resync,
 
  /* Output from can_bsp module */
  rx_idle,
  transmitting,
  last_bit_of_inter
 
 
 
 
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         rx;
 
  /* Mode register */
input         reset_mode;
 
/* Bus Timing 0 register */
input   [5:0] baud_r_presc;
input   [1:0] sync_jump_width;
 
/* Bus Timing 1 register */
input   [3:0] time_segment1;
input   [2:0] time_segment2;
input         triple_sampling;
 
/* Output from can_bsp module */
input         rx_idle;
input         transmitting;
input         last_bit_of_inter;
 
/* Output signals from this module */
output        clk_en;
output        sample_point;
output        sampled_bit;
output        sampled_bit_q;
output        tx_point;
output        hard_sync;
output        resync;
 
 
 
reg     [8:0] clk_cnt;
reg           clk_en;
reg           sync_blocked;
reg           resync_blocked;
reg           sampled_bit;
reg           sampled_bit_q;
reg     [7:0] quant_cnt;
reg     [3:0] delay;
reg           sync;
reg           seg1;
reg           seg2;
reg           resync_latched;
reg           sample_point;
reg     [1:0] sample;
 
wire          go_sync;
wire          go_seg1;
wire          go_seg2;
wire [8:0]    preset_cnt;
wire          sync_window;
 
 
 
assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
assign hard_sync  =   (rx_idle | last_bit_of_inter)  & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting);  // Hard synchronization
assign resync     =  (~rx_idle)                      & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting);  // Re-synchronization
 
 
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_cnt <= 0;
  else if (clk_cnt == (preset_cnt-1))
    clk_cnt <=#Tp 0;
  else
    clk_cnt <=#Tp clk_cnt + 1;
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    clk_en  <= 1'b0;
  else if (clk_cnt == (preset_cnt-1))
    clk_en  <=#Tp 1'b1;
  else
    clk_en  <=#Tp 1'b0;
end
 
 
 
/* Changing states */
 assign go_sync = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt == time_segment2)));
 assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
 assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
 
 
 
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
   SJW is reached */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_latched <= 1'b0;
  else if (resync & seg2 & (~sync_window))
    resync_latched <=#Tp 1'b1;
  else if (go_seg1)
    resync_latched <= 1'b0;
end
 
 
 
/* Synchronization stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync <= 0;
  else if (go_sync)
    sync <=#Tp 1'b1;
  else if (go_seg1)
    sync <=#Tp 1'b0;
end
 
 
assign tx_point = go_sync;
 
/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg1 <= 1;
  else if (go_seg1)
    seg1 <=#Tp 1'b1;
  else if (go_seg2)
    seg1 <=#Tp 1'b0;
end
 
 
/* Seg2 stage/segment */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    seg2 <= 0;
  else if (go_seg2)
    seg2 <=#Tp 1'b1;
  else if (go_sync | go_seg1)
    seg2 <=#Tp 1'b0;
end
 
 
/* Quant counter */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    quant_cnt <= 0;
  else if (go_sync | go_seg1 | go_seg2)
    quant_cnt <=#Tp 0;
  else if (clk_en)
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
 
 
/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    delay <= 0;
  else if (clk_en & resync & seg1)
    delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);
  else if (go_sync | go_seg1)
    delay <=#Tp 0;
end
 
 
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));
 
 
// Sampling data (memorizing two samples all the time).
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sample <= 2'b11;
  else if (clk_en)
    sample <= {sample[0], rx};
end
 
 
// When enabled, tripple sampling is done here.
always @ (posedge clk or posedge rst)
begin
  if (rst)
    begin
      sampled_bit <= 1;
      sampled_bit_q <= 1;
      sample_point <= 0;
    end
  else if (clk_en & (~hard_sync))
    begin
      if (seg1 & (quant_cnt == (time_segment1 + delay)))
        begin
          sample_point <=#Tp 1;
          sampled_bit_q <=#Tp sampled_bit;
          if (triple_sampling)
            sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
          else
            sampled_bit <=#Tp rx;
        end
    end
  else
    sample_point <=#Tp 0;
end
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    sync_blocked <=#Tp 1'b0;
  else if (clk_en)
    begin
      if (hard_sync | resync)
        sync_blocked <=#Tp 1'b1;
      else if (seg2 & quant_cnt == time_segment2)
        sync_blocked <=#Tp 1'b0;
    end
end
 
 
/* Blocking resynchronization until reception starts (needed because after reset mode exits we are waiting for
   end-of-frame and interframe. No resynchronization is needed meanwhile). */
always @ (posedge clk or posedge rst)
begin
  if (rst)
    resync_blocked <=#Tp 1'b1;
  else if (reset_mode)
    resync_blocked <=#Tp 1'b1;
  else if (hard_sync)
    resync_blocked <=#Tp 1'b0;
end
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_btl.v ////`
4			`//// ////`
5			`//// ////`
6	9	mohor	`//// This file is part of the CAN Protocol Controller ////`
7	2	mohor	`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15	9	mohor	`//// All additional information is available in the README.txt ////`
16	2	mohor	`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	9	mohor	`//// Copyright (C) 2002, 2003 Authors ////`
21	2	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	2	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	35	mohor	`// Revision 1.11 2003/02/09 18:40:29 mohor`
54			`// Overload fixed. Hard synchronization also enabled at the last bit of`
55			`// interframe.`
56			`//`
57	29	mohor	`// Revision 1.10 2003/02/09 02:24:33 mohor`
58			`// Bosch license warning added. Error counters finished. Overload frames`
59			`// still need to be fixed.`
60			`//`
61	28	mohor	`// Revision 1.9 2003/01/31 01:13:38 mohor`
62			`// backup.`
63			`//`
64	24	mohor	`// Revision 1.8 2003/01/10 17:51:34 mohor`
65			`// Temporary version (backup).`
66			`//`
67	15	mohor	`// Revision 1.7 2003/01/08 02:10:53 mohor`
68			`// Acceptance filter added.`
69			`//`
70	11	mohor	`// Revision 1.6 2002/12/28 04:13:23 mohor`
71			`// Backup version.`
72			`//`
73	10	mohor	`// Revision 1.5 2002/12/27 00:12:52 mohor`
74			`// Header changed, testbench improved to send a frame (crc still missing).`
75			`//`
76	9	mohor	`// Revision 1.4 2002/12/26 01:33:05 mohor`
77			`// Tripple sampling supported.`
78			`//`
79	7	mohor	`// Revision 1.3 2002/12/25 23:44:16 mohor`
80			`// Commented lines removed.`
81			`//`
82	6	mohor	`// Revision 1.2 2002/12/25 14:17:00 mohor`
83			`// Synchronization working.`
84			`//`
85	5	mohor	`// Revision 1.1.1.1 2002/12/20 16:39:21 mohor`
86			`// Initial`
87	2	mohor	`//`
88			`//`
89	5	mohor	`//`
90	2	mohor
91			`// synopsys translate_off`
92			`include "timescale.v"
93			`// synopsys translate_on`
94			`include "can_defines.v"
95
96			`module can_btl`
97			`(`
98			`clk,`
99			`rst,`
100			`rx,`
101
102			`/* Mode register */`
103	10	mohor	`reset_mode,`
104	2	mohor
105			`/* Bus Timing 0 register */`
106			`baud_r_presc,`
107			`sync_jump_width,`
108
109			`/* Bus Timing 1 register */`
110			`time_segment1,`
111			`time_segment2,`
112			`triple_sampling,`
113
114			`/* Output signals from this module */`
115			`clk_en,`
116	10	mohor	`sample_point,`
117			`sampled_bit,`
118			`sampled_bit_q,`
119	24	mohor	`tx_point,`
120	11	mohor	`hard_sync,`
121			`resync,`
122	2	mohor
123	10	mohor	`/* Output from can_bsp module */`
124	24	mohor	`rx_idle,`
125	29	mohor	`transmitting,`
126			`last_bit_of_inter`
127	2	mohor
128	10	mohor
129	11	mohor
130	2	mohor
131
132			`);`
133
134			`parameter Tp = 1;`
135
136			`input clk;`
137			`input rst;`
138			`input rx;`
139
140	10	mohor	`/* Mode register */`
141	2	mohor	`input reset_mode;`
142
143			`/* Bus Timing 0 register */`
144			`input [5:0] baud_r_presc;`
145			`input [1:0] sync_jump_width;`
146
147			`/* Bus Timing 1 register */`
148			`input [3:0] time_segment1;`
149			`input [2:0] time_segment2;`
150			`input triple_sampling;`
151
152	10	mohor	`/* Output from can_bsp module */`
153			`input rx_idle;`
154	24	mohor	`input transmitting;`
155	29	mohor	`input last_bit_of_inter;`
156	10	mohor
157	2	mohor	`/* Output signals from this module */`
158			`output clk_en;`
159	10	mohor	`output sample_point;`
160			`output sampled_bit;`
161			`output sampled_bit_q;`
162	24	mohor	`output tx_point;`
163	11	mohor	`output hard_sync;`
164			`output resync;`
165	2	mohor
166
167
168			`reg [8:0] clk_cnt;`
169			`reg clk_en;`
170	5	mohor	`reg sync_blocked;`
171	24	mohor	`reg resync_blocked;`
172	2	mohor	`reg sampled_bit;`
173	10	mohor	`reg sampled_bit_q;`
174	2	mohor	`reg [7:0] quant_cnt;`
175	6	mohor	`reg [3:0] delay;`
176			`reg sync;`
177			`reg seg1;`
178			`reg seg2;`
179			`reg resync_latched;`
180	10	mohor	`reg sample_point;`
181	7	mohor	`reg [1:0] sample;`
182	2	mohor
183	6	mohor	`wire go_sync;`
184			`wire go_seg1;`
185			`wire go_seg2;`
186			`wire [8:0] preset_cnt;`
187			`wire sync_window;`
188	2	mohor
189	5	mohor
190
191	6	mohor	`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`
192	29	mohor	`assign hard_sync = (rx_idle \| last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked) & (~transmitting); // Hard synchronization`
193			`assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked) & (~transmitting); // Re-synchronization`
194	5	mohor
195
196	6	mohor	`/* Generating general enable signal that defines baud rate. */`
197	2	mohor	`always @ (posedge clk or posedge rst)`
198			`begin`
199			`if (rst)`
200	10	mohor	`clk_cnt <= 0;`
201	35	mohor	`else if (clk_cnt == (preset_cnt-1))`
202	10	mohor	`clk_cnt <=#Tp 0;`
203			`else`
204			`clk_cnt <=#Tp clk_cnt + 1;`
205			`end`
206
207
208			`always @ (posedge clk or posedge rst)`
209			`begin`
210			`if (rst)`
211			`clk_en <= 1'b0;`
212	2	mohor	`else if (clk_cnt == (preset_cnt-1))`
213	10	mohor	`clk_en <=#Tp 1'b1;`
214	2	mohor	`else`
215	10	mohor	`clk_en <=#Tp 1'b0;`
216	2	mohor	`end`
217
218
219	5	mohor
220	6	mohor	`/* Changing states */`
221	10	mohor	`assign go_sync = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt == time_segment2)));`
222			`assign go_seg1 = clk_en & (sync \| hard_sync \| (resync & seg2 & sync_window) \| (resync_latched & sync_window));`
223			`assign go_seg2 = clk_en & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));`
224	5	mohor
225
226	10	mohor
227	6	mohor	`/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when`
228			`SJW is reached */`
229	2	mohor	`always @ (posedge clk or posedge rst)`
230			`begin`
231			`if (rst)`
232	5	mohor	`resync_latched <= 1'b0;`
233	6	mohor	`else if (resync & seg2 & (~sync_window))`
234	5	mohor	`resync_latched <=#Tp 1'b1;`
235			`else if (go_seg1)`
236			`resync_latched <= 1'b0;`
237			`end`
238
239
240
241	6	mohor	`/* Synchronization stage/segment */`
242	5	mohor	`always @ (posedge clk or posedge rst)`
243			`begin`
244			`if (rst)`
245	10	mohor	`sync <= 0;`
246	5	mohor	`else if (go_sync)`
247			`sync <=#Tp 1'b1;`
248			`else if (go_seg1)`
249			`sync <=#Tp 1'b0;`
250			`end`
251
252
253	24	mohor	`assign tx_point = go_sync;`
254
255	6	mohor	`/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */`
256	5	mohor	`always @ (posedge clk or posedge rst)`
257			`begin`
258			`if (rst)`
259	10	mohor	`seg1 <= 1;`
260	5	mohor	`else if (go_seg1)`
261			`seg1 <=#Tp 1'b1;`
262			`else if (go_seg2)`
263			`seg1 <=#Tp 1'b0;`
264			`end`
265
266
267	6	mohor	`/* Seg2 stage/segment */`
268	5	mohor	`always @ (posedge clk or posedge rst)`
269			`begin`
270			`if (rst)`
271			`seg2 <= 0;`
272			`else if (go_seg2)`
273			`seg2 <=#Tp 1'b1;`
274			`else if (go_sync \| go_seg1)`
275			`seg2 <=#Tp 1'b0;`
276			`end`
277
278
279	6	mohor	`/* Quant counter */`
280	5	mohor	`always @ (posedge clk or posedge rst)`
281			`begin`
282			`if (rst)`
283			`quant_cnt <= 0;`
284	35	mohor	`else if (go_sync \| go_seg1 \| go_seg2)`
285	5	mohor	`quant_cnt <=#Tp 0;`
286			`else if (clk_en)`
287			`quant_cnt <=#Tp quant_cnt + 1'b1;`
288			`end`
289
290
291	6	mohor	`/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */`
292	5	mohor	`always @ (posedge clk or posedge rst)`
293			`begin`
294			`if (rst)`
295	6	mohor	`delay <= 0;`
296	5	mohor	`else if (clk_en & resync & seg1)`
297	6	mohor	`delay <=#Tp (quant_cnt > sync_jump_width)? (sync_jump_width + 1) : (quant_cnt + 1);`
298	5	mohor	`else if (go_sync \| go_seg1)`
299	6	mohor	`delay <=#Tp 0;`
300	5	mohor	`end`
301
302
303	6	mohor	`// If early edge appears within this window (in seg2 stage), phase error is fully compensated`
304			`assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));`
305	5	mohor
306
307	7	mohor	`// Sampling data (memorizing two samples all the time).`
308	5	mohor	`always @ (posedge clk or posedge rst)`
309			`begin`
310			`if (rst)`
311	7	mohor	`sample <= 2'b11;`
312			`else if (clk_en)`
313			`sample <= {sample[0], rx};`
314			`end`
315
316
317			`// When enabled, tripple sampling is done here.`
318			`always @ (posedge clk or posedge rst)`
319			`begin`
320			`if (rst)`
321	2	mohor	`begin`
322			`sampled_bit <= 1;`
323	10	mohor	`sampled_bit_q <= 1;`
324			`sample_point <= 0;`
325	2	mohor	`end`
326	15	mohor	`else if (clk_en & (~hard_sync))`
327	2	mohor	`begin`
328	7	mohor	`if (seg1 & (quant_cnt == (time_segment1 + delay)))`
329			`begin`
330	10	mohor	`sample_point <=#Tp 1;`
331			`sampled_bit_q <=#Tp sampled_bit;`
332	7	mohor	`if (triple_sampling)`
333			`sampled_bit <=#Tp (sample[0] & sample[1]) \| ( sample[0] & rx) \| (sample[1] & rx);`
334			`else`
335			`sampled_bit <=#Tp rx;`
336			`end`
337	2	mohor	`end`
338	5	mohor	`else`
339	10	mohor	`sample_point <=#Tp 0;`
340	2	mohor	`end`
341
342
343
344	5	mohor	`/* Blocking synchronization (can occur only once in a bit time) */`
345	35	mohor
346	5	mohor	`always @ (posedge clk or posedge rst)`
347			`begin`
348			`if (rst)`
349			`sync_blocked <=#Tp 1'b0;`
350			`else if (clk_en)`
351			`begin`
352	35	mohor	`if (hard_sync \| resync)`
353	5	mohor	`sync_blocked <=#Tp 1'b1;`
354			`else if (seg2 & quant_cnt == time_segment2)`
355			`sync_blocked <=#Tp 1'b0;`
356			`end`
357			`end`
358	2	mohor
359
360	24	mohor	`/* Blocking resynchronization until reception starts (needed because after reset mode exits we are waiting for`
361			`end-of-frame and interframe. No resynchronization is needed meanwhile). */`
362			`always @ (posedge clk or posedge rst)`
363			`begin`
364			`if (rst)`
365			`resync_blocked <=#Tp 1'b1;`
366			`else if (reset_mode)`
367			`resync_blocked <=#Tp 1'b1;`
368			`else if (hard_sync)`
369			`resync_blocked <=#Tp 1'b0;`
370			`end`
371	2	mohor
372
373	5	mohor
374	24	mohor
375
376	2	mohor	`endmodule`

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