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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_crc.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003, 2004 Authors                       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2003/07/16 13:16:51  mohor
// Fixed according to the linter.
//
// Revision 1.3  2003/02/10 16:02:11  mohor
// CAN is working according to the specification. WB interface and more
// registers (status, IRQ, ...) needs to be added.
//
// Revision 1.2  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.1  2003/01/08 02:10:54  mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module can_crc (clk, data, enable, initialize, crc);
 
 
parameter Tp = 1;
 
input         clk;
input         data;
input         enable;
input         initialize;
 
output [14:0] crc;
 
reg    [14:0] crc;
 
wire          crc_next;
wire   [14:0] crc_tmp;
 
 
assign crc_next = data ^ crc[14];
assign crc_tmp = {crc[13:0], 1'b0};
 
always @ (posedge clk)
begin
  if(initialize)
    crc <= #Tp 15'h0;
  else if (enable)
    begin
      if (crc_next)
        crc <= #Tp crc_tmp ^ 15'h4599;
      else
        crc <= #Tp crc_tmp;
    end
end
 
 
endmodule

Line No.	Rev	Author	Line
1	11	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_crc.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	137	mohor	`//// Copyright (C) 2002, 2003, 2004 Authors ////`
21	11	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	11	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	137	mohor	`// Revision 1.4 2003/07/16 13:16:51 mohor`
54			`// Fixed according to the linter.`
55			`//`
56	107	mohor	`// Revision 1.3 2003/02/10 16:02:11 mohor`
57			`// CAN is working according to the specification. WB interface and more`
58			`// registers (status, IRQ, ...) needs to be added.`
59			`//`
60	30	mohor	`// Revision 1.2 2003/02/09 02:24:33 mohor`
61			`// Bosch license warning added. Error counters finished. Overload frames`
62			`// still need to be fixed.`
63			`//`
64	28	mohor	`// Revision 1.1 2003/01/08 02:10:54 mohor`
65			`// Acceptance filter added.`
66	11	mohor	`//`
67			`//`
68			`//`
69	28	mohor	`//`
70	11	mohor
71			`// synopsys translate_off`
72			`include "timescale.v"
73			`// synopsys translate_on`
74
75			`module can_crc (clk, data, enable, initialize, crc);`
76
77
78			`parameter Tp = 1;`
79
80			`input clk;`
81			`input data;`
82	30	mohor	`input enable;`
83	11	mohor	`input initialize;`
84
85			`output [14:0] crc;`
86
87			`reg [14:0] crc;`
88
89			`wire crc_next;`
90			`wire [14:0] crc_tmp;`
91
92
93			`assign crc_next = data ^ crc[14];`
94			`assign crc_tmp = {crc[13:0], 1'b0};`
95
96			`always @ (posedge clk)`
97			`begin`
98			`if(initialize)`
99	107	mohor	`crc <= #Tp 15'h0;`
100	11	mohor	`else if (enable)`
101			`begin`
102			`if (crc_next)`
103			`crc <= #Tp crc_tmp ^ 15'h4599;`
104			`else`
105			`crc <= #Tp crc_tmp;`
106			`end`
107			`end`
108
109
110			`endmodule`

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