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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_fifo.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.20  2003/07/16 14:00:45  mohor
// Fixed according to the linter.
//
// Revision 1.19  2003/07/03 09:30:44  mohor
// PCI_BIST replaced with CAN_BIST.
//
// Revision 1.18  2003/06/27 22:14:23  simons
// Overrun fifo implemented with FFs, because it is not possible to create such a memory.
//
// Revision 1.17  2003/06/27 20:56:15  simons
// Virtual silicon ram instances added.
//
// Revision 1.16  2003/06/18 23:03:44  mohor
// Typo fixed.
//
// Revision 1.15  2003/06/11 09:37:05  mohor
// overrun and length_info fifos are initialized at the end of reset.
//
// Revision 1.14  2003/03/05 15:02:30  mohor
// Xilinx RAM added.
//
// Revision 1.13  2003/03/01 22:53:33  mohor
// Actel APA ram supported.
//
// Revision 1.12  2003/02/19 14:44:03  mohor
// CAN core finished. Host interface added. Registers finished.
// Synchronization to the wishbone finished.
//
// Revision 1.11  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.10  2003/02/11 00:56:06  mohor
// Wishbone interface added.
//
// Revision 1.9  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.8  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.7  2003/01/17 17:44:31  mohor
// Fifo corrected to be synthesizable.
//
// Revision 1.6  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored
// to fifo, just the frame information (identifier, ...). Data length
// that is stored is the received data length and not the actual data
// length that is stored to fifo.
//
// Revision 1.5  2003/01/14 17:25:09  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.4  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.3  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.2  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.1  2003/01/08 02:10:55  mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_fifo
(
  clk,
  rst,
 
  wr,
 
  data_in,
  addr,
  data_out,
  fifo_selected,
 
  reset_mode,
  release_buffer,
  extended_mode,
  overrun,
  info_empty,
  info_cnt
 
`ifdef CAN_BIST
  ,
  scanb_rst,
  scanb_clk,
  scanb_si,
  scanb_so,
  scanb_en
`endif
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         wr;
input   [7:0] data_in;
input   [5:0] addr;
input         reset_mode;
input         release_buffer;
input         extended_mode;
input         fifo_selected;
 
output  [7:0] data_out;
output        overrun;
output        info_empty;
output  [6:0] info_cnt;
 
`ifdef CAN_BIST
input         scanb_rst;
input         scanb_clk;
input         scanb_si;
output        scanb_so;
input         scanb_en;
wire          scanb_s_0;
`endif
 
`ifdef ACTEL_APA_RAM
`else
`ifdef XILINX_RAM
`else
`ifdef ARTISAN_RAM
  reg           overrun_info[0:63];
`else
`ifdef VIRTUALSILICON_RAM
  reg           overrun_info[0:63];
`else
  reg     [7:0] fifo [0:63];
  reg     [3:0] length_fifo[0:63];
  reg           overrun_info[0:63];
`endif
`endif
`endif
`endif
 
reg     [5:0] rd_pointer;
reg     [5:0] wr_pointer;
reg     [5:0] read_address;
reg     [5:0] wr_info_pointer;
reg     [5:0] rd_info_pointer;
reg           wr_q;
reg     [3:0] len_cnt;
reg     [6:0] fifo_cnt;
reg     [6:0] info_cnt;
reg           latch_overrun;
reg           initialize_memories;
 
wire    [3:0] length_info;
wire          write_length_info;
wire          fifo_empty;
wire          fifo_full;
wire          info_full;
 
assign write_length_info = (~wr) & wr_q;
 
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_q <=#Tp 1'b0;
  else if (reset_mode)
    wr_q <=#Tp 1'b0;
  else
    wr_q <=#Tp wr;
end
 
 
// length counter
always @ (posedge clk or posedge rst)
begin
  if (rst)
    len_cnt <= 4'h0;
  else if (reset_mode | write_length_info)
    len_cnt <=#Tp 4'h0;
  else if (wr & (~fifo_full))
    len_cnt <=#Tp len_cnt + 1'b1;
end
 
 
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_info_pointer <= 6'h0;
  else if (write_length_info & (~info_full) | initialize_memories)
    wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
  else if (reset_mode)
    wr_info_pointer <=#Tp 6'h0;
end
 
 
 
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_info_pointer <= 6'h0;
  else if (reset_mode)
    rd_info_pointer <=#Tp 6'h0;
  else if (release_buffer & (~fifo_empty))
    rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
 
 
// rd_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_pointer <= 5'h0;
  else if (release_buffer & (~fifo_empty))
    rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
  else if (reset_mode)
    rd_pointer <=#Tp 5'h0;
end
 
 
// wr_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_pointer <= 5'h0;
  else if (wr & (~fifo_full))
    wr_pointer <=#Tp wr_pointer + 1'b1;
  else if (reset_mode)
    wr_pointer <=#Tp 5'h0;
end
 
 
// latch_overrun
always @ (posedge clk or posedge rst)
begin
  if (rst)
    latch_overrun <= 1'b0;
  else if (reset_mode | write_length_info)
    latch_overrun <=#Tp 1'b0;
  else if (wr & fifo_full)
    latch_overrun <=#Tp 1'b1;
end
 
 
// Counting data in fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    fifo_cnt <= 7'h0;
  else if (wr & (~release_buffer) & (~fifo_full))
    fifo_cnt <=#Tp fifo_cnt + 1'b1;
  else if ((~wr) & release_buffer & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
  else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
  else if (reset_mode)
    fifo_cnt <=#Tp 7'h0;
end
 
assign fifo_full = fifo_cnt == 7'd64;
assign fifo_empty = fifo_cnt == 7'd0;
 
 
// Counting data in length_fifo and overrun_info fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    info_cnt <=#Tp 7'h0;
  else if (reset_mode)
    info_cnt <=#Tp 7'h0;
  else if (write_length_info ^ release_buffer)
    begin
      if (release_buffer & (~info_empty))
        info_cnt <=#Tp info_cnt - 1'b1;
      else if (write_length_info & (~info_full))
        info_cnt <=#Tp info_cnt + 1'b1;
    end
end
 
assign info_full = info_cnt == 7'd64;
assign info_empty = info_cnt == 7'd0;
 
 
// Selecting which address will be used for reading data from rx fifo
always @ (extended_mode or rd_pointer or addr)
begin
  if (extended_mode)      // extended mode
    read_address = rd_pointer + (addr - 6'd16);
  else                    // normal mode
    read_address = rd_pointer + (addr - 6'd20);
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    initialize_memories <= 1'b1;
  else if (&wr_info_pointer)
    initialize_memories <=#Tp 1'b0;
end
 
 
`ifdef ACTEL_APA_RAM
  actel_ram_64x8_sync fifo
  (
    .DO      (data_out),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (data_in),
    .PO      (),                       // parity not used
    .WRB     (~(wr & (~fifo_full))),
    .RDB     (~fifo_selected),
    .WADDR   (wr_pointer),
    .RADDR   (read_address)
  );
 
 
  actel_ram_64x4_sync info_fifo
  (
    .DO      (length_info),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (len_cnt & {4{~initialize_memories}}),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
 
 
  actel_ram_64x1_sync overrun_fifo
  (
    .DO      (overrun),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
`else
`ifdef XILINX_RAM
 
/*
  ram_64x8_sync fifo
  (
    .addra(wr_pointer),
    .addrb(read_address),
    .clka(clk),
    .clkb(clk),
    .dina(data_in),
    .doutb(data_out),
    .wea(wr & (~fifo_full))
  );
*/
 
  RAMB4_S8_S8 fifo
  (
    .DOA(),
    .DOB(data_out),
    .ADDRA({3'h0, wr_pointer}),
    .CLKA(clk),
    .DIA(data_in),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(wr & (~fifo_full)),
    .ADDRB({3'h0, read_address}),
    .CLKB(clk),
    .DIB(8'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
 
/*
  ram_64x4_sync info_fifo
  (
    .addra(wr_info_pointer),
    .addrb(rd_info_pointer),
    .clka(clk),
    .clkb(clk),
    .dina(len_cnt),
    .doutb(length_info),
    .wea(write_length_info & (~info_full))
  );
*/
  RAMB4_S4_S4 info_fifo
  (
    .DOA(),
    .DOB(length_info),
    .ADDRA({4'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA(len_cnt & {4{~initialize_memories}}),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({4'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(4'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
/*
  ram_64x1_sync overrun_fifo
  (
    .addra(wr_info_pointer),
    .addrb(rd_info_pointer),
    .clka(clk),
    .clkb(clk),
    .dina(latch_overrun | (wr & fifo_full)),
    .doutb(overrun),
    .wea(write_length_info & (~info_full))
  );
*/
 
 
  RAMB4_S1_S1 overrun_fifo
  (
    .DOA(),
    .DOB(overrun),
    .ADDRA({6'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({6'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(1'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
`else
`ifdef VIRTUALSILICON_RAM
 
`ifdef CAN_BIST
    vs_hdtp_64x8_bist fifo
`else
    vs_hdtp_64x8 fifo
`endif
    (
        .RCK        (clk),
        .WCK        (clk),
        .RADR       (read_address),
        .WADR       (wr_pointer),
        .DI         (data_in),
        .DOUT       (data_out),
        .REN        (~fifo_selected),
        .WEN        (~(wr & (~fifo_full)))
    `ifdef CAN_BIST
        ,
        // debug chain signals
        .scanb_rst  (scanb_rst),
        .scanb_clk  (scanb_clk),
        .scanb_si   (scanb_si),
        .scanb_so   (scanb_s_0),
        .scanb_en   (scanb_en)
    `endif
    );
 
`ifdef CAN_BIST
    vs_hdtp_64x4_bist info_fifo
`else
    vs_hdtp_64x4 info_fifo
`endif
    (
        .RCK        (clk),
        .WCK        (clk),
        .RADR       (rd_info_pointer),
        .WADR       (wr_info_pointer),
        .DI         (len_cnt & {4{~initialize_memories}}),
        .DOUT       (length_info),
        .REN        (1'b0),
        .WEN        (~(write_length_info & (~info_full) | initialize_memories))
    `ifdef CAN_BIST
        ,
        // debug chain signals
        .scanb_rst  (scanb_rst),
        .scanb_clk  (scanb_clk),
        .scanb_si   (scanb_s_0),
        .scanb_so   (scanb_so),
        .scanb_en   (scanb_en)
    `endif
    );
 
    // overrun_info
    always @ (posedge clk)
    begin
      if (write_length_info & (~info_full) | initialize_memories)
        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
    end
 
 
    // reading overrun
    assign overrun = overrun_info[rd_info_pointer];
 
`else
`ifdef ARTISAN_RAM
 
`ifdef CAN_BIST
    art_hstp_64x8_bist fifo
    (
        .CLKR       (clk),
        .CLKW       (clk),
        .AR         (read_address),
        .AW         (wr_pointer),
        .D          (data_in),
        .Q          (data_out),
        .REN        (~fifo_selected),
        .WEN        (~(wr & (~fifo_full))),
        .scanb_rst  (scanb_rst),
        .scanb_clk  (scanb_clk),
        .scanb_si   (scanb_si),
        .scanb_so   (scanb_s_0),
        .scanb_en   (scanb_en)
    );
    art_hstp_64x4_bist info_fifo
    (
        .CLKR       (clk),
        .CLKW       (clk),
        .AR         (rd_info_pointer),
        .AW         (wr_info_pointer),
        .D          (len_cnt & {4{~initialize_memories}}),
        .Q          (length_info),
        .REN        (1'b0),
        .WEN        (~(write_length_info & (~info_full) | initialize_memories)),
        .scanb_rst  (scanb_rst),
        .scanb_clk  (scanb_clk),
        .scanb_si   (scanb_s_0),
        .scanb_so   (scanb_so),
        .scanb_en   (scanb_en)
    );
`else
    art_hsdp_64x8 fifo
    (
        .CENA       (1'b0),
        .CENB       (1'b0),
        .CLKA       (clk),
        .CLKB       (clk),
        .AA         (read_address),
        .AB         (wr_pointer),
        .DA         (8'h00),
        .DB         (data_in),
        .QA         (data_out),
        .QB         (),
        .RENA       (~fifo_selected),
        .RENB       (1'b1),
        .WENA       (1'b1),
        .WENB       (~(wr & (~fifo_full))),
    );
    art_hsdp_64x4 info_fifo
    (
        .CENA       (1'b0),
        .CENB       (1'b0),
        .CLKA       (clk),
        .CLKB       (clk),
        .AA         (rd_info_pointer),
        .AB         (wr_info_pointer),
        .DA         (4'h0),
        .DB         (len_cnt & {4{~initialize_memories}}),
        .QA         (length_info),
        .QB         (),
        .RENA       (1'b0),
        .RENB       (1'b1),
        .WENB       (),
        .WENB       (~(write_length_info & (~info_full) | initialize_memories))
    );
`endif
 
    // overrun_info
    always @ (posedge clk)
    begin
      if (write_length_info & (~info_full) | initialize_memories)
        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
    end
 
 
    // reading overrun
    assign overrun = overrun_info[rd_info_pointer];
 
`else
  // writing data to fifo
  always @ (posedge clk)
  begin
    if (wr & (~fifo_full))
      fifo[wr_pointer] <=#Tp data_in;
  end
 
  // reading from fifo
  assign data_out = fifo[read_address];
 
 
  // writing length_fifo
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
  end
 
 
  // reading length_fifo
  assign length_info = length_fifo[rd_info_pointer];
 
  // overrun_info
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
  end
 
 
  // reading overrun
  assign overrun = overrun_info[rd_info_pointer];
 
 
`endif
`endif
`endif
`endif
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	11	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_fifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002, 2003 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	11	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	115	simons	`// Revision 1.20 2003/07/16 14:00:45 mohor`
54			`// Fixed according to the linter.`
55			`//`
56	109	mohor	`// Revision 1.19 2003/07/03 09:30:44 mohor`
57			`// PCI_BIST replaced with CAN_BIST.`
58			`//`
59	99	mohor	`// Revision 1.18 2003/06/27 22:14:23 simons`
60			`// Overrun fifo implemented with FFs, because it is not possible to create such a memory.`
61			`//`
62	97	simons	`// Revision 1.17 2003/06/27 20:56:15 simons`
63			`// Virtual silicon ram instances added.`
64			`//`
65	95	simons	`// Revision 1.16 2003/06/18 23:03:44 mohor`
66			`// Typo fixed.`
67			`//`
68	85	mohor	`// Revision 1.15 2003/06/11 09:37:05 mohor`
69			`// overrun and length_info fifos are initialized at the end of reset.`
70			`//`
71	73	mohor	`// Revision 1.14 2003/03/05 15:02:30 mohor`
72			`// Xilinx RAM added.`
73			`//`
74	51	mohor	`// Revision 1.13 2003/03/01 22:53:33 mohor`
75			`// Actel APA ram supported.`
76			`//`
77	48	mohor	`// Revision 1.12 2003/02/19 14:44:03 mohor`
78			`// CAN core finished. Host interface added. Registers finished.`
79			`// Synchronization to the wishbone finished.`
80			`//`
81	39	mohor	`// Revision 1.11 2003/02/14 20:17:01 mohor`
82			`// Several registers added. Not finished, yet.`
83			`//`
84	35	mohor	`// Revision 1.10 2003/02/11 00:56:06 mohor`
85			`// Wishbone interface added.`
86			`//`
87	31	mohor	`// Revision 1.9 2003/02/09 02:24:33 mohor`
88			`// Bosch license warning added. Error counters finished. Overload frames`
89			`// still need to be fixed.`
90			`//`
91	28	mohor	`// Revision 1.8 2003/01/31 01:13:38 mohor`
92			`// backup.`
93			`//`
94	24	mohor	`// Revision 1.7 2003/01/17 17:44:31 mohor`
95			`// Fifo corrected to be synthesizable.`
96			`//`
97	23	mohor	`// Revision 1.6 2003/01/15 13:16:47 mohor`
98	31	mohor	`// When a frame with "remote request" is received, no data is stored`
99			`// to fifo, just the frame information (identifier, ...). Data length`
100			`// that is stored is the received data length and not the actual data`
101			`// length that is stored to fifo.`
102	23	mohor	`//`
103	18	mohor	`// Revision 1.5 2003/01/14 17:25:09 mohor`
104			`// Addresses corrected to decimal values (previously hex).`
105			`//`
106	17	mohor	`// Revision 1.4 2003/01/14 12:19:35 mohor`
107			`// rx_fifo is now working.`
108			`//`
109	16	mohor	`// Revision 1.3 2003/01/09 21:54:45 mohor`
110			`// rx fifo added. Not 100 % verified, yet.`
111			`//`
112	14	mohor	`// Revision 1.2 2003/01/09 14:46:58 mohor`
113			`// Temporary files (backup).`
114			`//`
115	13	mohor	`// Revision 1.1 2003/01/08 02:10:55 mohor`
116			`// Acceptance filter added.`
117	11	mohor	`//`
118			`//`
119			`//`
120	13	mohor	`//`
121	11	mohor
122			`// synopsys translate_off`
123			`include "timescale.v"
124			`// synopsys translate_on`
125			`include "can_defines.v"
126
127			`module can_fifo`
128			`(`
129			`clk,`
130			`rst,`
131
132			`wr,`
133
134			`data_in,`
135	14	mohor	`addr,`
136	11	mohor	`data_out,`
137	48	mohor	`fifo_selected,`
138	11	mohor
139			`reset_mode,`
140	14	mohor	`release_buffer,`
141	35	mohor	`extended_mode,`
142			`overrun,`
143	39	mohor	`info_empty,`
144			`info_cnt`
145	13	mohor
146	95	simons	`ifdef CAN_BIST
147			`,`
148			`scanb_rst,`
149			`scanb_clk,`
150			`scanb_si,`
151			`scanb_so,`
152			`scanb_en`
153			`endif
154	11	mohor	`);`
155
156			`parameter Tp = 1;`
157
158			`input clk;`
159			`input rst;`
160			`input wr;`
161			`input [7:0] data_in;`
162	109	mohor	`input [5:0] addr;`
163	11	mohor	`input reset_mode;`
164			`input release_buffer;`
165	14	mohor	`input extended_mode;`
166	48	mohor	`input fifo_selected;`
167	11	mohor
168	13	mohor	`output [7:0] data_out;`
169	35	mohor	`output overrun;`
170			`output info_empty;`
171	39	mohor	`output [6:0] info_cnt;`
172	11	mohor
173	95	simons	`ifdef CAN_BIST
174			`input scanb_rst;`
175			`input scanb_clk;`
176			`input scanb_si;`
177			`output scanb_so;`
178			`input scanb_en;`
179			`wire scanb_s_0;`
180			`endif
181
182	48	mohor	`ifdef ACTEL_APA_RAM
183			`else
184	51	mohor	`ifdef XILINX_RAM
185			`else
186	115	simons	`ifdef ARTISAN_RAM
187			`reg overrun_info[0:63];`
188			`else
189	95	simons	`ifdef VIRTUALSILICON_RAM
190	97	simons	`reg overrun_info[0:63];`
191	95	simons	`else
192	48	mohor	`reg [7:0] fifo [0:63];`
193			`reg [3:0] length_fifo[0:63];`
194			`reg overrun_info[0:63];`
195			`endif
196	51	mohor	`endif
197	95	simons	`endif
198	115	simons	`endif
199	11	mohor
200			`reg [5:0] rd_pointer;`
201			`reg [5:0] wr_pointer;`
202	14	mohor	`reg [5:0] read_address;`
203	16	mohor	`reg [5:0] wr_info_pointer;`
204			`reg [5:0] rd_info_pointer;`
205	13	mohor	`reg wr_q;`
206			`reg [3:0] len_cnt;`
207	16	mohor	`reg [6:0] fifo_cnt;`
208	24	mohor	`reg [6:0] info_cnt;`
209	16	mohor	`reg latch_overrun;`
210	73	mohor	`reg initialize_memories;`
211	11	mohor
212	48	mohor	`wire [3:0] length_info;`
213	13	mohor	`wire write_length_info;`
214	16	mohor	`wire fifo_empty;`
215			`wire fifo_full;`
216	24	mohor	`wire info_full;`
217	11	mohor
218	13	mohor	`assign write_length_info = (~wr) & wr_q;`
219
220			`// Delayed write signal`
221			`always @ (posedge clk or posedge rst)`
222			`begin`
223			`if (rst)`
224	109	mohor	`wr_q <=#Tp 1'b0;`
225	13	mohor	`else if (reset_mode)`
226	109	mohor	`wr_q <=#Tp 1'b0;`
227	13	mohor	`else`
228			`wr_q <=#Tp wr;`
229			`end`
230
231
232			`// length counter`
233			`always @ (posedge clk or posedge rst)`
234			`begin`
235			`if (rst)`
236	109	mohor	`len_cnt <= 4'h0;`
237	13	mohor	`else if (reset_mode \| write_length_info)`
238	109	mohor	`len_cnt <=#Tp 4'h0;`
239	16	mohor	`else if (wr & (~fifo_full))`
240	13	mohor	`len_cnt <=#Tp len_cnt + 1'b1;`
241			`end`
242
243
244			`// wr_info_pointer`
245			`always @ (posedge clk or posedge rst)`
246			`begin`
247			`if (rst)`
248	109	mohor	`wr_info_pointer <= 6'h0;`
249	73	mohor	`else if (write_length_info & (~info_full) \| initialize_memories)`
250			`wr_info_pointer <=#Tp wr_info_pointer + 1'b1;`
251	13	mohor	`else if (reset_mode)`
252	109	mohor	`wr_info_pointer <=#Tp 6'h0;`
253	13	mohor	`end`
254
255
256
257			`// rd_info_pointer`
258	11	mohor	`always @ (posedge clk or posedge rst)`
259			`begin`
260			`if (rst)`
261	109	mohor	`rd_info_pointer <= 6'h0;`
262	11	mohor	`else if (reset_mode)`
263	109	mohor	`rd_info_pointer <=#Tp 6'h0;`
264	16	mohor	`else if (release_buffer & (~fifo_empty))`
265	13	mohor	`rd_info_pointer <=#Tp rd_info_pointer + 1'b1;`
266	11	mohor	`end`
267
268
269			`// rd_pointer`
270			`always @ (posedge clk or posedge rst)`
271			`begin`
272			`if (rst)`
273	109	mohor	`rd_pointer <= 5'h0;`
274	16	mohor	`else if (release_buffer & (~fifo_empty))`
275	109	mohor	`rd_pointer <=#Tp rd_pointer + {2'h0, length_info};`
276	11	mohor	`else if (reset_mode)`
277	109	mohor	`rd_pointer <=#Tp 5'h0;`
278	11	mohor	`end`
279
280
281			`// wr_pointer`
282			`always @ (posedge clk or posedge rst)`
283			`begin`
284			`if (rst)`
285	109	mohor	`wr_pointer <= 5'h0;`
286	16	mohor	`else if (wr & (~fifo_full))`
287	13	mohor	`wr_pointer <=#Tp wr_pointer + 1'b1;`
288	11	mohor	`else if (reset_mode)`
289	109	mohor	`wr_pointer <=#Tp 5'h0;`
290	11	mohor	`end`
291
292
293	16	mohor	`// latch_overrun`
294			`always @ (posedge clk or posedge rst)`
295			`begin`
296			`if (rst)`
297	109	mohor	`latch_overrun <= 1'b0;`
298	16	mohor	`else if (reset_mode \| write_length_info)`
299	109	mohor	`latch_overrun <=#Tp 1'b0;`
300	16	mohor	`else if (wr & fifo_full)`
301			`latch_overrun <=#Tp 1'b1;`
302			`end`
303
304
305			`// Counting data in fifo`
306			`always @ (posedge clk or posedge rst)`
307			`begin`
308			`if (rst)`
309	109	mohor	`fifo_cnt <= 7'h0;`
310	16	mohor	`else if (wr & (~release_buffer) & (~fifo_full))`
311			`fifo_cnt <=#Tp fifo_cnt + 1'b1;`
312			`else if ((~wr) & release_buffer & (~fifo_empty))`
313	109	mohor	`fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};`
314	16	mohor	`else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))`
315	109	mohor	`fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;`
316	16	mohor	`else if (reset_mode)`
317	109	mohor	`fifo_cnt <=#Tp 7'h0;`
318	16	mohor	`end`
319
320	109	mohor	`assign fifo_full = fifo_cnt == 7'd64;`
321			`assign fifo_empty = fifo_cnt == 7'd0;`
322	16	mohor
323
324	48	mohor	`// Counting data in length_fifo and overrun_info fifo`
325	24	mohor	`always @ (posedge clk or posedge rst)`
326			`begin`
327			`if (rst)`
328	109	mohor	`info_cnt <=#Tp 7'h0;`
329			`else if (reset_mode)`
330			`info_cnt <=#Tp 7'h0;`
331	24	mohor	`else if (write_length_info ^ release_buffer)`
332			`begin`
333			`if (release_buffer & (~info_empty))`
334			`info_cnt <=#Tp info_cnt - 1'b1;`
335			`else if (write_length_info & (~info_full))`
336			`info_cnt <=#Tp info_cnt + 1'b1;`
337			`end`
338			`end`
339
340	109	mohor	`assign info_full = info_cnt == 7'd64;`
341			`assign info_empty = info_cnt == 7'd0;`
342	16	mohor
343	24	mohor
344	14	mohor	`// Selecting which address will be used for reading data from rx fifo`
345			`always @ (extended_mode or rd_pointer or addr)`
346			`begin`
347			`if (extended_mode) // extended mode`
348	109	mohor	`read_address = rd_pointer + (addr - 6'd16);`
349	14	mohor	`else // normal mode`
350	109	mohor	`read_address = rd_pointer + (addr - 6'd20);`
351	14	mohor	`end`
352	11	mohor
353
354	73	mohor	`always @ (posedge clk or posedge rst)`
355			`begin`
356			`if (rst)`
357	109	mohor	`initialize_memories <= 1'b1;`
358	73	mohor	`else if (&wr_info_pointer)`
359			`initialize_memories <=#Tp 1'b0;`
360			`end`
361	14	mohor
362	73	mohor
363	48	mohor	`ifdef ACTEL_APA_RAM
364			`actel_ram_64x8_sync fifo`
365			`(`
366			`.DO (data_out),`
367			`.RCLOCK (clk),`
368			`.WCLOCK (clk),`
369			`.DI (data_in),`
370			`.PO (), // parity not used`
371			`.WRB (~(wr & (~fifo_full))),`
372			`.RDB (~fifo_selected),`
373			`.WADDR (wr_pointer),`
374			`.RADDR (read_address)`
375			`);`
376	14	mohor
377
378	48	mohor	`actel_ram_64x4_sync info_fifo`
379			`(`
380			`.DO (length_info),`
381			`.RCLOCK (clk),`
382			`.WCLOCK (clk),`
383	73	mohor	`.DI (len_cnt & {4{~initialize_memories}}),`
384	48	mohor	`.PO (), // parity not used`
385	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
386	48	mohor	`.RDB (1'b0), // always enabled`
387			`.WADDR (wr_info_pointer),`
388			`.RADDR (rd_info_pointer)`
389			`);`
390	14	mohor
391
392	48	mohor	`actel_ram_64x1_sync overrun_fifo`
393			`(`
394			`.DO (overrun),`
395			`.RCLOCK (clk),`
396			`.WCLOCK (clk),`
397	73	mohor	`.DI ((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
398	48	mohor	`.PO (), // parity not used`
399	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
400	48	mohor	`.RDB (1'b0), // always enabled`
401			`.WADDR (wr_info_pointer),`
402			`.RADDR (rd_info_pointer)`
403			`);`
404			`else
405	51	mohor	`ifdef XILINX_RAM
406
407			`/*`
408			`ram_64x8_sync fifo`
409			`(`
410			`.addra(wr_pointer),`
411			`.addrb(read_address),`
412			`.clka(clk),`
413			`.clkb(clk),`
414			`.dina(data_in),`
415			`.doutb(data_out),`
416			`.wea(wr & (~fifo_full))`
417			`);`
418			`*/`
419
420			`RAMB4_S8_S8 fifo`
421			`(`
422			`.DOA(),`
423			`.DOB(data_out),`
424			`.ADDRA({3'h0, wr_pointer}),`
425			`.CLKA(clk),`
426			`.DIA(data_in),`
427			`.ENA(1'b1),`
428			`.RSTA(1'b0),`
429			`.WEA(wr & (~fifo_full)),`
430			`.ADDRB({3'h0, read_address}),`
431			`.CLKB(clk),`
432			`.DIB(8'h0),`
433			`.ENB(1'b1),`
434			`.RSTB(1'b0),`
435			`.WEB(1'b0)`
436			`);`
437
438
439
440			`/*`
441			`ram_64x4_sync info_fifo`
442			`(`
443			`.addra(wr_info_pointer),`
444			`.addrb(rd_info_pointer),`
445			`.clka(clk),`
446			`.clkb(clk),`
447			`.dina(len_cnt),`
448			`.doutb(length_info),`
449			`.wea(write_length_info & (~info_full))`
450			`);`
451			`*/`
452			`RAMB4_S4_S4 info_fifo`
453			`(`
454			`.DOA(),`
455			`.DOB(length_info),`
456			`.ADDRA({4'h0, wr_info_pointer}),`
457			`.CLKA(clk),`
458	73	mohor	`.DIA(len_cnt & {4{~initialize_memories}}),`
459	51	mohor	`.ENA(1'b1),`
460			`.RSTA(1'b0),`
461	73	mohor	`.WEA(write_length_info & (~info_full) \| initialize_memories),`
462	51	mohor	`.ADDRB({4'h0, rd_info_pointer}),`
463			`.CLKB(clk),`
464			`.DIB(4'h0),`
465			`.ENB(1'b1),`
466			`.RSTB(1'b0),`
467			`.WEB(1'b0)`
468			`);`
469
470			`/*`
471			`ram_64x1_sync overrun_fifo`
472			`(`
473			`.addra(wr_info_pointer),`
474			`.addrb(rd_info_pointer),`
475			`.clka(clk),`
476			`.clkb(clk),`
477			`.dina(latch_overrun \| (wr & fifo_full)),`
478			`.doutb(overrun),`
479			`.wea(write_length_info & (~info_full))`
480			`);`
481			`*/`
482
483
484			`RAMB4_S1_S1 overrun_fifo`
485			`(`
486			`.DOA(),`
487			`.DOB(overrun),`
488			`.ADDRA({6'h0, wr_info_pointer}),`
489			`.CLKA(clk),`
490	73	mohor	`.DIA((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
491	51	mohor	`.ENA(1'b1),`
492			`.RSTA(1'b0),`
493	73	mohor	`.WEA(write_length_info & (~info_full) \| initialize_memories),`
494	51	mohor	`.ADDRB({6'h0, rd_info_pointer}),`
495			`.CLKB(clk),`
496			`.DIB(1'h0),`
497			`.ENB(1'b1),`
498			`.RSTB(1'b0),`
499			`.WEB(1'b0)`
500			`);`

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