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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_fifo.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.22  2003/08/20 09:59:16  mohor
// Artisan RAM fixed (when not using BIST).
//
// Revision 1.21  2003/08/14 16:04:52  simons
// Artisan ram instances added.
//
// Revision 1.20  2003/07/16 14:00:45  mohor
// Fixed according to the linter.
//
// Revision 1.19  2003/07/03 09:30:44  mohor
// PCI_BIST replaced with CAN_BIST.
//
// Revision 1.18  2003/06/27 22:14:23  simons
// Overrun fifo implemented with FFs, because it is not possible to create such a memory.
//
// Revision 1.17  2003/06/27 20:56:15  simons
// Virtual silicon ram instances added.
//
// Revision 1.16  2003/06/18 23:03:44  mohor
// Typo fixed.
//
// Revision 1.15  2003/06/11 09:37:05  mohor
// overrun and length_info fifos are initialized at the end of reset.
//
// Revision 1.14  2003/03/05 15:02:30  mohor
// Xilinx RAM added.
//
// Revision 1.13  2003/03/01 22:53:33  mohor
// Actel APA ram supported.
//
// Revision 1.12  2003/02/19 14:44:03  mohor
// CAN core finished. Host interface added. Registers finished.
// Synchronization to the wishbone finished.
//
// Revision 1.11  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.10  2003/02/11 00:56:06  mohor
// Wishbone interface added.
//
// Revision 1.9  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.8  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.7  2003/01/17 17:44:31  mohor
// Fifo corrected to be synthesizable.
//
// Revision 1.6  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored
// to fifo, just the frame information (identifier, ...). Data length
// that is stored is the received data length and not the actual data
// length that is stored to fifo.
//
// Revision 1.5  2003/01/14 17:25:09  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.4  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.3  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.2  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.1  2003/01/08 02:10:55  mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_fifo
(
  clk,
  rst,
 
  wr,
 
  data_in,
  addr,
  data_out,
  fifo_selected,
 
  reset_mode,
  release_buffer,
  extended_mode,
  overrun,
  info_empty,
  info_cnt
 
`ifdef CAN_BIST
  ,
  scanb_rst,
  scanb_clk,
  scanb_si,
  scanb_so,
  scanb_en
`endif
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         wr;
input   [7:0] data_in;
input   [5:0] addr;
input         reset_mode;
input         release_buffer;
input         extended_mode;
input         fifo_selected;
 
output  [7:0] data_out;
output        overrun;
output        info_empty;
output  [6:0] info_cnt;
 
`ifdef CAN_BIST
input         scanb_rst;
input         scanb_clk;
input         scanb_si;
output        scanb_so;
input         scanb_en;
wire          scanb_s_0;
`endif
 
`ifdef ALTERA_RAM
`else
`ifdef ACTEL_APA_RAM
`else
`ifdef XILINX_RAM
`else
`ifdef ARTISAN_RAM
  reg           overrun_info[0:63];
`else
`ifdef VIRTUALSILICON_RAM
  reg           overrun_info[0:63];
`else
  reg     [7:0] fifo [0:63];
  reg     [3:0] length_fifo[0:63];
  reg           overrun_info[0:63];
`endif
`endif
`endif
`endif
`endif
 
reg     [5:0] rd_pointer;
reg     [5:0] wr_pointer;
reg     [5:0] read_address;
reg     [5:0] wr_info_pointer;
reg     [5:0] rd_info_pointer;
reg           wr_q;
reg     [3:0] len_cnt;
reg     [6:0] fifo_cnt;
reg     [6:0] info_cnt;
reg           latch_overrun;
reg           initialize_memories;
 
wire    [3:0] length_info;
wire          write_length_info;
wire          fifo_empty;
wire          fifo_full;
wire          info_full;
 
assign write_length_info = (~wr) & wr_q;
 
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_q <=#Tp 1'b0;
  else if (reset_mode)
    wr_q <=#Tp 1'b0;
  else
    wr_q <=#Tp wr;
end
 
 
// length counter
always @ (posedge clk or posedge rst)
begin
  if (rst)
    len_cnt <= 4'h0;
  else if (reset_mode | write_length_info)
    len_cnt <=#Tp 4'h0;
  else if (wr & (~fifo_full))
    len_cnt <=#Tp len_cnt + 1'b1;
end
 
 
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_info_pointer <= 6'h0;
  else if (write_length_info & (~info_full) | initialize_memories)
    wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
  else if (reset_mode)
    wr_info_pointer <=#Tp 6'h0;
end
 
 
 
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_info_pointer <= 6'h0;
  else if (reset_mode)
    rd_info_pointer <=#Tp 6'h0;
  else if (release_buffer & (~fifo_empty))
    rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
 
 
// rd_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_pointer <= 5'h0;
  else if (release_buffer & (~fifo_empty))
    rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
  else if (reset_mode)
    rd_pointer <=#Tp 5'h0;
end
 
 
// wr_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_pointer <= 5'h0;
  else if (wr & (~fifo_full))
    wr_pointer <=#Tp wr_pointer + 1'b1;
  else if (reset_mode)
    wr_pointer <=#Tp 5'h0;
end
 
 
// latch_overrun
always @ (posedge clk or posedge rst)
begin
  if (rst)
    latch_overrun <= 1'b0;
  else if (reset_mode | write_length_info)
    latch_overrun <=#Tp 1'b0;
  else if (wr & fifo_full)
    latch_overrun <=#Tp 1'b1;
end
 
 
// Counting data in fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    fifo_cnt <= 7'h0;
  else if (wr & (~release_buffer) & (~fifo_full))
    fifo_cnt <=#Tp fifo_cnt + 1'b1;
  else if ((~wr) & release_buffer & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
  else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
  else if (reset_mode)
    fifo_cnt <=#Tp 7'h0;
end
 
assign fifo_full = fifo_cnt == 7'd64;
assign fifo_empty = fifo_cnt == 7'd0;
 
 
// Counting data in length_fifo and overrun_info fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    info_cnt <=#Tp 7'h0;
  else if (reset_mode)
    info_cnt <=#Tp 7'h0;
  else if (write_length_info ^ release_buffer)
    begin
      if (release_buffer & (~info_empty))
        info_cnt <=#Tp info_cnt - 1'b1;
      else if (write_length_info & (~info_full))
        info_cnt <=#Tp info_cnt + 1'b1;
    end
end
 
assign info_full = info_cnt == 7'd64;
assign info_empty = info_cnt == 7'd0;
 
 
// Selecting which address will be used for reading data from rx fifo
always @ (extended_mode or rd_pointer or addr)
begin
  if (extended_mode)      // extended mode
    read_address = rd_pointer + (addr - 6'd16);
  else                    // normal mode
    read_address = rd_pointer + (addr - 6'd20);
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    initialize_memories <= 1'b1;
  else if (&wr_info_pointer)
    initialize_memories <=#Tp 1'b0;
end
 
 
`ifdef ALTERA_RAM
//  altera_ram_64x8_sync fifo
  lpm_ram_dp fifo
  (
    .q         (data_out),
    .rdclock   (clk),
    .wrclock   (clk),
    .data      (data_in),
    .wren      (~(wr & (~fifo_full))),
    .rden      (~fifo_selected),
    .wraddress (wr_pointer),
    .rdaddress (read_address)
  );
  defparam fifo.lpm_width = 8;
  defparam fifo.lpm_widthad = 6;
 
 
//  altera_ram_64x4_sync info_fifo
  lpm_ram_dp info_fifo
  (
    .q         (length_info),
    .rdclock   (clk),
    .wrclock   (clk),
    .data      (len_cnt & {4{~initialize_memories}}),
    .wren      (~(write_length_info & (~info_full) | initialize_memories)),
    .rden      (1'b0),                   // always enabled
    .wraddress (wr_info_pointer),
    .rdaddress (rd_info_pointer)
  );
  defparam info_fifo.lpm_width = 4;
  defparam info_fifo.lpm_widthad = 6;
 
 
//  altera_ram_64x1_sync overrun_fifo
  lpm_ram_dp overrun_fifo
  (
    .q         (overrun),
    .rdclock   (clk),
    .wrclock   (clk),
    .data      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .wren      (~(write_length_info & (~info_full) | initialize_memories)),
    .rden      (1'b0),                   // always enabled
    .wraddress (wr_info_pointer),
    .rdaddress (rd_info_pointer)
  );
  defparam overrun_fifo.lpm_width = 1;
  defparam overrun_fifo.lpm_widthad = 6;
 
`else
`ifdef ACTEL_APA_RAM
  actel_ram_64x8_sync fifo
  (
    .DO      (data_out),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (data_in),
    .PO      (),                       // parity not used
    .WRB     (~(wr & (~fifo_full))),
    .RDB     (~fifo_selected),
    .WADDR   (wr_pointer),
    .RADDR   (read_address)
  );
 
 
  actel_ram_64x4_sync info_fifo
  (
    .DO      (length_info),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (len_cnt & {4{~initialize_memories}}),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
 
 
  actel_ram_64x1_sync overrun_fifo
  (
    .DO      (overrun),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
`else
`ifdef XILINX_RAM
 
/*
  ram_64x8_sync fifo
  (
    .addra(wr_pointer),
    .addrb(read_address),
    .clka(clk),
    .clkb(clk),
    .dina(data_in),
    .doutb(data_out),
    .wea(wr & (~fifo_full))
  );
*/
 
  RAMB4_S8_S8 fifo
  (
    .DOA(),
    .DOB(data_out),
    .ADDRA({3'h0, wr_pointer}),
    .CLKA(clk),
    .DIA(data_in),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(wr & (~fifo_full)),
    .ADDRB({3'h0, read_address}),
    .CLKB(clk),
    .DIB(8'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
 
/*
  ram_64x4_sync info_fifo
  (
    .addra(wr_info_pointer),
    .addrb(rd_info_pointer),
    .clka(clk),
    .clkb(clk),
    .dina(len_cnt),
    .doutb(length_info),
    .wea(write_length_info & (~info_full))
  );
*/
  RAMB4_S4_S4 info_fifo
  (
    .DOA(),
    .DOB(length_info),
    .ADDRA({4'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA(len_cnt & {4{~initialize_memories}}),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({4'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(4'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
/*
  ram_64x1_sync overrun_fifo
  (
    .addra(wr_info_pointer),
    .addrb(rd_info_pointer),
    .clka(clk),
    .clkb(clk),
    .dina(latch_overrun | (wr & fifo_full)),
    .doutb(overrun),
    .wea(write_length_info & (~info_full))
  );
*/
 
 
  RAMB4_S1_S1 overrun_fifo
  (
    .DOA(),
    .DOB(overrun),
    .ADDRA({6'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({6'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(1'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
`else
`ifdef VIRTUALSILICON_RAM
 
`ifdef CAN_BIST
    vs_hdtp_64x8_bist fifo
`else
    vs_hdtp_64x8 fifo
`endif
    (
        .RCK        (clk),
        .WCK        (clk),
        .RADR       (read_address),
        .WADR       (wr_pointer),
        .DI         (data_in),
        .DOUT       (data_out),
        .REN        (~fifo_selected),
        .WEN        (~(wr & (~fifo_full)))
    `ifdef CAN_BIST
        ,
        // debug chain signals
        .scanb_rst  (scanb_rst),
        .scanb_clk  (scanb_clk),
        .scanb_si   (scanb_si),
        .scanb_so   (scanb_s_0),
        .scanb_en   (scanb_en)
    `endif
    );
 
`ifdef CAN_BIST
    vs_hdtp_64x4_bist info_fifo
`else
    vs_hdtp_64x4 info_fifo
`endif
    (
        .RCK        (clk),
        .WCK        (clk),
        .RADR       (rd_info_pointer),
        .WADR       (wr_info_pointer),
        .DI         (len_cnt & {4{~initialize_memories}}),
        .DOUT       (length_info),
        .REN        (1'b0),
        .WEN        (~(write_length_info & (~info_full) | initialize_memories))
    `ifdef CAN_BIST
        ,
        // debug chain signals
        .scanb_rst  (scanb_rst),
        .scanb_clk  (scanb_clk),
        .scanb_si   (scanb_s_0),
        .scanb_so   (scanb_so),
        .scanb_en   (scanb_en)
    `endif
    );
 
    // overrun_info
    always @ (posedge clk)
    begin
      if (write_length_info & (~info_full) | initialize_memories)
        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
    end
 
 
    // reading overrun
    assign overrun = overrun_info[rd_info_pointer];
 
`else
`ifdef ARTISAN_RAM
 
`ifdef CAN_BIST
    art_hstp_64x8_bist fifo
    (
        .CLKR       (clk),
        .CLKW       (clk),
        .AR         (read_address),
        .AW         (wr_pointer),
        .D          (data_in),
        .Q          (data_out),
        .REN        (~fifo_selected),
        .WEN        (~(wr & (~fifo_full))),
        .scanb_rst  (scanb_rst),
        .scanb_clk  (scanb_clk),
        .scanb_si   (scanb_si),
        .scanb_so   (scanb_s_0),
        .scanb_en   (scanb_en)
    );
    art_hstp_64x4_bist info_fifo
    (
        .CLKR       (clk),
        .CLKW       (clk),
        .AR         (rd_info_pointer),
        .AW         (wr_info_pointer),
        .D          (len_cnt & {4{~initialize_memories}}),
        .Q          (length_info),
        .REN        (1'b0),
        .WEN        (~(write_length_info & (~info_full) | initialize_memories)),
        .scanb_rst  (scanb_rst),
        .scanb_clk  (scanb_clk),
        .scanb_si   (scanb_s_0),
        .scanb_so   (scanb_so),
        .scanb_en   (scanb_en)
    );
`else
    art_hsdp_64x8 fifo
    (
        .CENA       (1'b0),
        .CENB       (1'b0),
        .CLKA       (clk),
        .CLKB       (clk),
        .AA         (read_address),
        .AB         (wr_pointer),
        .DA         (8'h00),
        .DB         (data_in),
        .QA         (data_out),
        .QB         (),
        .OENA       (~fifo_selected),
        .OENB       (1'b1),
        .WENA       (1'b1),
        .WENB       (~(wr & (~fifo_full)))
    );
    art_hsdp_64x4 info_fifo
    (
        .CENA       (1'b0),
        .CENB       (1'b0),
        .CLKA       (clk),
        .CLKB       (clk),
        .AA         (rd_info_pointer),
        .AB         (wr_info_pointer),
        .DA         (4'h0),
        .DB         (len_cnt & {4{~initialize_memories}}),
        .QA         (length_info),
        .QB         (),
        .OENA       (1'b0),
        .OENB       (1'b1),
        .WENA       (1'b1),
        .WENB       (~(write_length_info & (~info_full) | initialize_memories))
    );
`endif
 
    // overrun_info
    always @ (posedge clk)
    begin
      if (write_length_info & (~info_full) | initialize_memories)
        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
    end
 
 
    // reading overrun
    assign overrun = overrun_info[rd_info_pointer];
 
`else
  // writing data to fifo
  always @ (posedge clk)
  begin
    if (wr & (~fifo_full))
      fifo[wr_pointer] <=#Tp data_in;
  end
 
  // reading from fifo
  assign data_out = fifo[read_address];
 
 
  // writing length_fifo
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
  end
 
 
  // reading length_fifo
  assign length_info = length_fifo[rd_info_pointer];
 
  // overrun_info
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
  end
 
 
  // reading overrun
  assign overrun = overrun_info[rd_info_pointer];
 
 
`endif
`endif
`endif
`endif
`endif
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	11	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_fifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002, 2003 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	11	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	124	mohor	`// Revision 1.22 2003/08/20 09:59:16 mohor`
54			`// Artisan RAM fixed (when not using BIST).`
55			`//`
56	118	mohor	`// Revision 1.21 2003/08/14 16:04:52 simons`
57			`// Artisan ram instances added.`
58			`//`
59	115	simons	`// Revision 1.20 2003/07/16 14:00:45 mohor`
60			`// Fixed according to the linter.`
61			`//`
62	109	mohor	`// Revision 1.19 2003/07/03 09:30:44 mohor`
63			`// PCI_BIST replaced with CAN_BIST.`
64			`//`
65	99	mohor	`// Revision 1.18 2003/06/27 22:14:23 simons`
66			`// Overrun fifo implemented with FFs, because it is not possible to create such a memory.`
67			`//`
68	97	simons	`// Revision 1.17 2003/06/27 20:56:15 simons`
69			`// Virtual silicon ram instances added.`
70			`//`
71	95	simons	`// Revision 1.16 2003/06/18 23:03:44 mohor`
72			`// Typo fixed.`
73			`//`
74	85	mohor	`// Revision 1.15 2003/06/11 09:37:05 mohor`
75			`// overrun and length_info fifos are initialized at the end of reset.`
76			`//`
77	73	mohor	`// Revision 1.14 2003/03/05 15:02:30 mohor`
78			`// Xilinx RAM added.`
79			`//`
80	51	mohor	`// Revision 1.13 2003/03/01 22:53:33 mohor`
81			`// Actel APA ram supported.`
82			`//`
83	48	mohor	`// Revision 1.12 2003/02/19 14:44:03 mohor`
84			`// CAN core finished. Host interface added. Registers finished.`
85			`// Synchronization to the wishbone finished.`
86			`//`
87	39	mohor	`// Revision 1.11 2003/02/14 20:17:01 mohor`
88			`// Several registers added. Not finished, yet.`
89			`//`
90	35	mohor	`// Revision 1.10 2003/02/11 00:56:06 mohor`
91			`// Wishbone interface added.`
92			`//`
93	31	mohor	`// Revision 1.9 2003/02/09 02:24:33 mohor`
94			`// Bosch license warning added. Error counters finished. Overload frames`
95			`// still need to be fixed.`
96			`//`
97	28	mohor	`// Revision 1.8 2003/01/31 01:13:38 mohor`
98			`// backup.`
99			`//`
100	24	mohor	`// Revision 1.7 2003/01/17 17:44:31 mohor`
101			`// Fifo corrected to be synthesizable.`
102			`//`
103	23	mohor	`// Revision 1.6 2003/01/15 13:16:47 mohor`
104	31	mohor	`// When a frame with "remote request" is received, no data is stored`
105			`// to fifo, just the frame information (identifier, ...). Data length`
106			`// that is stored is the received data length and not the actual data`
107			`// length that is stored to fifo.`
108	23	mohor	`//`
109	18	mohor	`// Revision 1.5 2003/01/14 17:25:09 mohor`
110			`// Addresses corrected to decimal values (previously hex).`
111			`//`
112	17	mohor	`// Revision 1.4 2003/01/14 12:19:35 mohor`
113			`// rx_fifo is now working.`
114			`//`
115	16	mohor	`// Revision 1.3 2003/01/09 21:54:45 mohor`
116			`// rx fifo added. Not 100 % verified, yet.`
117			`//`
118	14	mohor	`// Revision 1.2 2003/01/09 14:46:58 mohor`
119			`// Temporary files (backup).`
120			`//`
121	13	mohor	`// Revision 1.1 2003/01/08 02:10:55 mohor`
122			`// Acceptance filter added.`
123	11	mohor	`//`
124			`//`
125			`//`
126	13	mohor	`//`
127	11	mohor
128			`// synopsys translate_off`
129			`include "timescale.v"
130			`// synopsys translate_on`
131			`include "can_defines.v"
132
133			`module can_fifo`
134			`(`
135			`clk,`
136			`rst,`
137
138			`wr,`
139
140			`data_in,`
141	14	mohor	`addr,`
142	11	mohor	`data_out,`
143	48	mohor	`fifo_selected,`
144	11	mohor
145			`reset_mode,`
146	14	mohor	`release_buffer,`
147	35	mohor	`extended_mode,`
148			`overrun,`
149	39	mohor	`info_empty,`
150			`info_cnt`
151	13	mohor
152	95	simons	`ifdef CAN_BIST
153			`,`
154			`scanb_rst,`
155			`scanb_clk,`
156			`scanb_si,`
157			`scanb_so,`
158			`scanb_en`
159			`endif
160	11	mohor	`);`
161
162			`parameter Tp = 1;`
163
164			`input clk;`
165			`input rst;`
166			`input wr;`
167			`input [7:0] data_in;`
168	109	mohor	`input [5:0] addr;`
169	11	mohor	`input reset_mode;`
170			`input release_buffer;`
171	14	mohor	`input extended_mode;`
172	48	mohor	`input fifo_selected;`
173	11	mohor
174	13	mohor	`output [7:0] data_out;`
175	35	mohor	`output overrun;`
176			`output info_empty;`
177	39	mohor	`output [6:0] info_cnt;`
178	11	mohor
179	95	simons	`ifdef CAN_BIST
180			`input scanb_rst;`
181			`input scanb_clk;`
182			`input scanb_si;`
183			`output scanb_so;`
184			`input scanb_en;`
185			`wire scanb_s_0;`
186			`endif
187
188	124	mohor	`ifdef ALTERA_RAM
189			`else
190	48	mohor	`ifdef ACTEL_APA_RAM
191			`else
192	51	mohor	`ifdef XILINX_RAM
193			`else
194	115	simons	`ifdef ARTISAN_RAM
195			`reg overrun_info[0:63];`
196			`else
197	95	simons	`ifdef VIRTUALSILICON_RAM
198	97	simons	`reg overrun_info[0:63];`
199	95	simons	`else
200	48	mohor	`reg [7:0] fifo [0:63];`
201			`reg [3:0] length_fifo[0:63];`
202			`reg overrun_info[0:63];`
203			`endif
204	51	mohor	`endif
205	95	simons	`endif
206	115	simons	`endif
207	124	mohor	`endif
208	11	mohor
209			`reg [5:0] rd_pointer;`
210			`reg [5:0] wr_pointer;`
211	14	mohor	`reg [5:0] read_address;`
212	16	mohor	`reg [5:0] wr_info_pointer;`
213			`reg [5:0] rd_info_pointer;`
214	13	mohor	`reg wr_q;`
215			`reg [3:0] len_cnt;`
216	16	mohor	`reg [6:0] fifo_cnt;`
217	24	mohor	`reg [6:0] info_cnt;`
218	16	mohor	`reg latch_overrun;`
219	73	mohor	`reg initialize_memories;`
220	11	mohor
221	48	mohor	`wire [3:0] length_info;`
222	13	mohor	`wire write_length_info;`
223	16	mohor	`wire fifo_empty;`
224			`wire fifo_full;`
225	24	mohor	`wire info_full;`
226	11	mohor
227	13	mohor	`assign write_length_info = (~wr) & wr_q;`
228
229			`// Delayed write signal`
230			`always @ (posedge clk or posedge rst)`
231			`begin`
232			`if (rst)`
233	109	mohor	`wr_q <=#Tp 1'b0;`
234	13	mohor	`else if (reset_mode)`
235	109	mohor	`wr_q <=#Tp 1'b0;`
236	13	mohor	`else`
237			`wr_q <=#Tp wr;`
238			`end`
239
240
241			`// length counter`
242			`always @ (posedge clk or posedge rst)`
243			`begin`
244			`if (rst)`
245	109	mohor	`len_cnt <= 4'h0;`
246	13	mohor	`else if (reset_mode \| write_length_info)`
247	109	mohor	`len_cnt <=#Tp 4'h0;`
248	16	mohor	`else if (wr & (~fifo_full))`
249	13	mohor	`len_cnt <=#Tp len_cnt + 1'b1;`
250			`end`
251
252
253			`// wr_info_pointer`
254			`always @ (posedge clk or posedge rst)`
255			`begin`
256			`if (rst)`
257	109	mohor	`wr_info_pointer <= 6'h0;`
258	73	mohor	`else if (write_length_info & (~info_full) \| initialize_memories)`
259			`wr_info_pointer <=#Tp wr_info_pointer + 1'b1;`
260	13	mohor	`else if (reset_mode)`
261	109	mohor	`wr_info_pointer <=#Tp 6'h0;`
262	13	mohor	`end`
263
264
265
266			`// rd_info_pointer`
267	11	mohor	`always @ (posedge clk or posedge rst)`
268			`begin`
269			`if (rst)`
270	109	mohor	`rd_info_pointer <= 6'h0;`
271	11	mohor	`else if (reset_mode)`
272	109	mohor	`rd_info_pointer <=#Tp 6'h0;`
273	16	mohor	`else if (release_buffer & (~fifo_empty))`
274	13	mohor	`rd_info_pointer <=#Tp rd_info_pointer + 1'b1;`
275	11	mohor	`end`
276
277
278			`// rd_pointer`
279			`always @ (posedge clk or posedge rst)`
280			`begin`
281			`if (rst)`
282	109	mohor	`rd_pointer <= 5'h0;`
283	16	mohor	`else if (release_buffer & (~fifo_empty))`
284	109	mohor	`rd_pointer <=#Tp rd_pointer + {2'h0, length_info};`
285	11	mohor	`else if (reset_mode)`
286	109	mohor	`rd_pointer <=#Tp 5'h0;`
287	11	mohor	`end`
288
289
290			`// wr_pointer`
291			`always @ (posedge clk or posedge rst)`
292			`begin`
293			`if (rst)`
294	109	mohor	`wr_pointer <= 5'h0;`
295	16	mohor	`else if (wr & (~fifo_full))`
296	13	mohor	`wr_pointer <=#Tp wr_pointer + 1'b1;`
297	11	mohor	`else if (reset_mode)`
298	109	mohor	`wr_pointer <=#Tp 5'h0;`
299	11	mohor	`end`
300
301
302	16	mohor	`// latch_overrun`
303			`always @ (posedge clk or posedge rst)`
304			`begin`
305			`if (rst)`
306	109	mohor	`latch_overrun <= 1'b0;`
307	16	mohor	`else if (reset_mode \| write_length_info)`
308	109	mohor	`latch_overrun <=#Tp 1'b0;`
309	16	mohor	`else if (wr & fifo_full)`
310			`latch_overrun <=#Tp 1'b1;`
311			`end`
312
313
314			`// Counting data in fifo`
315			`always @ (posedge clk or posedge rst)`
316			`begin`
317			`if (rst)`
318	109	mohor	`fifo_cnt <= 7'h0;`
319	16	mohor	`else if (wr & (~release_buffer) & (~fifo_full))`
320			`fifo_cnt <=#Tp fifo_cnt + 1'b1;`
321			`else if ((~wr) & release_buffer & (~fifo_empty))`
322	109	mohor	`fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};`
323	16	mohor	`else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))`
324	109	mohor	`fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;`
325	16	mohor	`else if (reset_mode)`
326	109	mohor	`fifo_cnt <=#Tp 7'h0;`
327	16	mohor	`end`
328
329	109	mohor	`assign fifo_full = fifo_cnt == 7'd64;`
330			`assign fifo_empty = fifo_cnt == 7'd0;`
331	16	mohor
332
333	48	mohor	`// Counting data in length_fifo and overrun_info fifo`
334	24	mohor	`always @ (posedge clk or posedge rst)`
335			`begin`
336			`if (rst)`
337	109	mohor	`info_cnt <=#Tp 7'h0;`
338			`else if (reset_mode)`
339			`info_cnt <=#Tp 7'h0;`
340	24	mohor	`else if (write_length_info ^ release_buffer)`
341			`begin`
342			`if (release_buffer & (~info_empty))`
343			`info_cnt <=#Tp info_cnt - 1'b1;`
344			`else if (write_length_info & (~info_full))`
345			`info_cnt <=#Tp info_cnt + 1'b1;`
346			`end`
347			`end`
348
349	109	mohor	`assign info_full = info_cnt == 7'd64;`
350			`assign info_empty = info_cnt == 7'd0;`
351	16	mohor
352	24	mohor
353	14	mohor	`// Selecting which address will be used for reading data from rx fifo`
354			`always @ (extended_mode or rd_pointer or addr)`
355			`begin`
356			`if (extended_mode) // extended mode`
357	109	mohor	`read_address = rd_pointer + (addr - 6'd16);`
358	14	mohor	`else // normal mode`
359	109	mohor	`read_address = rd_pointer + (addr - 6'd20);`
360	14	mohor	`end`
361	11	mohor
362
363	73	mohor	`always @ (posedge clk or posedge rst)`
364			`begin`
365			`if (rst)`
366	109	mohor	`initialize_memories <= 1'b1;`
367	73	mohor	`else if (&wr_info_pointer)`
368			`initialize_memories <=#Tp 1'b0;`
369			`end`
370	14	mohor
371	73	mohor
372	124	mohor	`ifdef ALTERA_RAM
373			`// altera_ram_64x8_sync fifo`
374			`lpm_ram_dp fifo`
375			`(`
376			`.q (data_out),`
377			`.rdclock (clk),`
378			`.wrclock (clk),`
379			`.data (data_in),`
380			`.wren (~(wr & (~fifo_full))),`
381			`.rden (~fifo_selected),`
382			`.wraddress (wr_pointer),`
383			`.rdaddress (read_address)`
384			`);`
385			`defparam fifo.lpm_width = 8;`
386			`defparam fifo.lpm_widthad = 6;`
387
388
389			`// altera_ram_64x4_sync info_fifo`
390			`lpm_ram_dp info_fifo`
391			`(`
392			`.q (length_info),`
393			`.rdclock (clk),`
394			`.wrclock (clk),`
395			`.data (len_cnt & {4{~initialize_memories}}),`
396			`.wren (~(write_length_info & (~info_full) \| initialize_memories)),`
397			`.rden (1'b0), // always enabled`
398			`.wraddress (wr_info_pointer),`
399			`.rdaddress (rd_info_pointer)`
400			`);`
401			`defparam info_fifo.lpm_width = 4;`
402			`defparam info_fifo.lpm_widthad = 6;`
403
404
405			`// altera_ram_64x1_sync overrun_fifo`
406			`lpm_ram_dp overrun_fifo`
407			`(`
408			`.q (overrun),`
409			`.rdclock (clk),`
410			`.wrclock (clk),`
411			`.data ((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
412			`.wren (~(write_length_info & (~info_full) \| initialize_memories)),`
413			`.rden (1'b0), // always enabled`
414			`.wraddress (wr_info_pointer),`
415			`.rdaddress (rd_info_pointer)`
416			`);`
417			`defparam overrun_fifo.lpm_width = 1;`
418			`defparam overrun_fifo.lpm_widthad = 6;`
419
420			`else
421	48	mohor	`ifdef ACTEL_APA_RAM
422			`actel_ram_64x8_sync fifo`
423			`(`
424			`.DO (data_out),`
425			`.RCLOCK (clk),`
426			`.WCLOCK (clk),`
427			`.DI (data_in),`
428			`.PO (), // parity not used`
429			`.WRB (~(wr & (~fifo_full))),`
430			`.RDB (~fifo_selected),`
431			`.WADDR (wr_pointer),`
432			`.RADDR (read_address)`
433			`);`
434	14	mohor
435
436	48	mohor	`actel_ram_64x4_sync info_fifo`
437			`(`
438			`.DO (length_info),`
439			`.RCLOCK (clk),`
440			`.WCLOCK (clk),`
441	73	mohor	`.DI (len_cnt & {4{~initialize_memories}}),`
442	48	mohor	`.PO (), // parity not used`
443	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
444	48	mohor	`.RDB (1'b0), // always enabled`
445			`.WADDR (wr_info_pointer),`
446			`.RADDR (rd_info_pointer)`
447			`);`
448	14	mohor
449
450	48	mohor	`actel_ram_64x1_sync overrun_fifo`
451			`(`
452			`.DO (overrun),`
453			`.RCLOCK (clk),`
454			`.WCLOCK (clk),`
455	73	mohor	`.DI ((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
456	48	mohor	`.PO (), // parity not used`
457	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
458	48	mohor	`.RDB (1'b0), // always enabled`
459			`.WADDR (wr_info_pointer),`
460			`.RADDR (rd_info_pointer)`
461			`);`
462			`else
463	51	mohor	`ifdef XILINX_RAM
464
465			`/*`
466			`ram_64x8_sync fifo`
467			`(`
468			`.addra(wr_pointer),`
469			`.addrb(read_address),`
470			`.clka(clk),`
471			`.clkb(clk),`
472			`.dina(data_in),`
473			`.doutb(data_out),`
474			`.wea(wr & (~fifo_full))`
475			`);`
476			`*/`
477
478			`RAMB4_S8_S8 fifo`
479			`(`
480			`.DOA(),`
481			`.DOB(data_out),`
482			`.ADDRA({3'h0, wr_pointer}),`
483			`.CLKA(clk),`
484			`.DIA(data_in),`
485			`.ENA(1'b1),`
486			`.RSTA(1'b0),`
487			`.WEA(wr & (~fifo_full)),`
488			`.ADDRB({3'h0, read_address}),`
489			`.CLKB(clk),`
490			`.DIB(8'h0),`
491			`.ENB(1'b1),`
492			`.RSTB(1'b0),`
493			`.WEB(1'b0)`
494			`);`
495
496
497
498			`/*`
499			`ram_64x4_sync info_fifo`
500			`(`

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