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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_fifo.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003, 2004 Authors                       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.25  2003/10/23 16:52:17  mohor
// Active high/low problem when Altera devices are used. Bug fixed by
// Rojhalat Ibrahim.
//
// Revision 1.24  2003/10/17 05:55:20  markom
// mbist signals updated according to newest convention
//
// Revision 1.23  2003/09/05 12:46:41  mohor
// ALTERA_RAM supported.
//
// Revision 1.22  2003/08/20 09:59:16  mohor
// Artisan RAM fixed (when not using BIST).
//
// Revision 1.21  2003/08/14 16:04:52  simons
// Artisan ram instances added.
//
// Revision 1.20  2003/07/16 14:00:45  mohor
// Fixed according to the linter.
//
// Revision 1.19  2003/07/03 09:30:44  mohor
// PCI_BIST replaced with CAN_BIST.
//
// Revision 1.18  2003/06/27 22:14:23  simons
// Overrun fifo implemented with FFs, because it is not possible to create such a memory.
//
// Revision 1.17  2003/06/27 20:56:15  simons
// Virtual silicon ram instances added.
//
// Revision 1.16  2003/06/18 23:03:44  mohor
// Typo fixed.
//
// Revision 1.15  2003/06/11 09:37:05  mohor
// overrun and length_info fifos are initialized at the end of reset.
//
// Revision 1.14  2003/03/05 15:02:30  mohor
// Xilinx RAM added.
//
// Revision 1.13  2003/03/01 22:53:33  mohor
// Actel APA ram supported.
//
// Revision 1.12  2003/02/19 14:44:03  mohor
// CAN core finished. Host interface added. Registers finished.
// Synchronization to the wishbone finished.
//
// Revision 1.11  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.10  2003/02/11 00:56:06  mohor
// Wishbone interface added.
//
// Revision 1.9  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.8  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.7  2003/01/17 17:44:31  mohor
// Fifo corrected to be synthesizable.
//
// Revision 1.6  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored
// to fifo, just the frame information (identifier, ...). Data length
// that is stored is the received data length and not the actual data
// length that is stored to fifo.
//
// Revision 1.5  2003/01/14 17:25:09  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.4  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.3  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.2  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.1  2003/01/08 02:10:55  mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_fifo
(
  clk,
  rst,
 
  wr,
 
  data_in,
  addr,
  data_out,
  fifo_selected,
 
  reset_mode,
  release_buffer,
  extended_mode,
  overrun,
  info_empty,
  info_cnt
 
`ifdef CAN_BIST
  ,
  mbist_si_i,
  mbist_so_o,
  mbist_ctrl_i
`endif
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         wr;
input   [7:0] data_in;
input   [5:0] addr;
input         reset_mode;
input         release_buffer;
input         extended_mode;
input         fifo_selected;
 
output  [7:0] data_out;
output        overrun;
output        info_empty;
output  [6:0] info_cnt;
 
`ifdef CAN_BIST
input         mbist_si_i;
output        mbist_so_o;
input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
wire          mbist_s_0;
`endif
 
`ifdef ALTERA_RAM
`else
`ifdef ACTEL_APA_RAM
`else
`ifdef XILINX_RAM
`else
`ifdef ARTISAN_RAM
  reg           overrun_info[0:63];
`else
`ifdef VIRTUALSILICON_RAM
  reg           overrun_info[0:63];
`else
  reg     [7:0] fifo [0:63];
  reg     [3:0] length_fifo[0:63];
  reg           overrun_info[0:63];
`endif
`endif
`endif
`endif
`endif
 
reg     [5:0] rd_pointer;
reg     [5:0] wr_pointer;
reg     [5:0] read_address;
reg     [5:0] wr_info_pointer;
reg     [5:0] rd_info_pointer;
reg           wr_q;
reg     [3:0] len_cnt;
reg     [6:0] fifo_cnt;
reg     [6:0] info_cnt;
reg           latch_overrun;
reg           initialize_memories;
 
wire    [3:0] length_info;
wire          write_length_info;
wire          fifo_empty;
wire          fifo_full;
wire          info_full;
 
assign write_length_info = (~wr) & wr_q;
 
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_q <=#Tp 1'b0;
  else if (reset_mode)
    wr_q <=#Tp 1'b0;
  else
    wr_q <=#Tp wr;
end
 
 
// length counter
always @ (posedge clk or posedge rst)
begin
  if (rst)
    len_cnt <= 4'h0;
  else if (reset_mode | write_length_info)
    len_cnt <=#Tp 4'h0;
  else if (wr & (~fifo_full))
    len_cnt <=#Tp len_cnt + 1'b1;
end
 
 
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_info_pointer <= 6'h0;
  else if (write_length_info & (~info_full) | initialize_memories)
    wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
  else if (reset_mode)
    wr_info_pointer <=#Tp 6'h0;
end
 
 
 
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_info_pointer <= 6'h0;
  else if (reset_mode)
    rd_info_pointer <=#Tp 6'h0;
  else if (release_buffer & (~fifo_empty))
    rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
 
 
// rd_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_pointer <= 5'h0;
  else if (release_buffer & (~fifo_empty))
    rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
  else if (reset_mode)
    rd_pointer <=#Tp 5'h0;
end
 
 
// wr_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_pointer <= 5'h0;
  else if (wr & (~fifo_full))
    wr_pointer <=#Tp wr_pointer + 1'b1;
  else if (reset_mode)
    wr_pointer <=#Tp 5'h0;
end
 
 
// latch_overrun
always @ (posedge clk or posedge rst)
begin
  if (rst)
    latch_overrun <= 1'b0;
  else if (reset_mode | write_length_info)
    latch_overrun <=#Tp 1'b0;
  else if (wr & fifo_full)
    latch_overrun <=#Tp 1'b1;
end
 
 
// Counting data in fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    fifo_cnt <= 7'h0;
  else if (wr & (~release_buffer) & (~fifo_full))
    fifo_cnt <=#Tp fifo_cnt + 1'b1;
  else if ((~wr) & release_buffer & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
  else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
  else if (reset_mode)
    fifo_cnt <=#Tp 7'h0;
end
 
assign fifo_full = fifo_cnt == 7'd64;
assign fifo_empty = fifo_cnt == 7'd0;
 
 
// Counting data in length_fifo and overrun_info fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    info_cnt <=#Tp 7'h0;
  else if (reset_mode)
    info_cnt <=#Tp 7'h0;
  else if (write_length_info ^ release_buffer)
    begin
      if (release_buffer & (~info_empty))
        info_cnt <=#Tp info_cnt - 1'b1;
      else if (write_length_info & (~info_full))
        info_cnt <=#Tp info_cnt + 1'b1;
    end
end
 
assign info_full = info_cnt == 7'd64;
assign info_empty = info_cnt == 7'd0;
 
 
// Selecting which address will be used for reading data from rx fifo
always @ (extended_mode or rd_pointer or addr)
begin
  if (extended_mode)      // extended mode
    read_address = rd_pointer + (addr - 6'd16);
  else                    // normal mode
    read_address = rd_pointer + (addr - 6'd20);
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    initialize_memories <= 1'b1;
  else if (&wr_info_pointer)
    initialize_memories <=#Tp 1'b0;
end
 
 
`ifdef ALTERA_RAM
//  altera_ram_64x8_sync fifo
  lpm_ram_dp fifo
  (
    .q         (data_out),
    .rdclock   (clk),
    .wrclock   (clk),
    .data      (data_in),
    .wren      (wr & (~fifo_full)),
    .rden      (fifo_selected),
    .wraddress (wr_pointer),
    .rdaddress (read_address)
  );
  defparam fifo.lpm_width = 8;
  defparam fifo.lpm_widthad = 6;
  defparam fifo.lpm_numwords = 64;
 
 
//  altera_ram_64x4_sync info_fifo
  lpm_ram_dp info_fifo
  (
    .q         (length_info),
    .rdclock   (clk),
    .wrclock   (clk),
    .data      (len_cnt & {4{~initialize_memories}}),
    .wren      (write_length_info & (~info_full) | initialize_memories),
    .wraddress (wr_info_pointer),
    .rdaddress (rd_info_pointer)
  );
  defparam info_fifo.lpm_width = 4;
  defparam info_fifo.lpm_widthad = 6;
  defparam info_fifo.lpm_numwords = 64;
 
 
//  altera_ram_64x1_sync overrun_fifo
  lpm_ram_dp overrun_fifo
  (
    .q         (overrun),
    .rdclock   (clk),
    .wrclock   (clk),
    .data      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .wren      (write_length_info & (~info_full) | initialize_memories),
    .wraddress (wr_info_pointer),
    .rdaddress (rd_info_pointer)
  );
  defparam overrun_fifo.lpm_width = 1;
  defparam overrun_fifo.lpm_widthad = 6;
  defparam overrun_fifo.lpm_numwords = 64;
 
`else
`ifdef ACTEL_APA_RAM
  actel_ram_64x8_sync fifo
  (
    .DO      (data_out),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (data_in),
    .PO      (),                       // parity not used
    .WRB     (~(wr & (~fifo_full))),
    .RDB     (~fifo_selected),
    .WADDR   (wr_pointer),
    .RADDR   (read_address)
  );
 
 
  actel_ram_64x4_sync info_fifo
  (
    .DO      (length_info),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (len_cnt & {4{~initialize_memories}}),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
 
 
  actel_ram_64x1_sync overrun_fifo
  (
    .DO      (overrun),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
`else
`ifdef XILINX_RAM
 
  RAMB4_S8_S8 fifo
  (
    .DOA(),
    .DOB(data_out),
    .ADDRA({3'h0, wr_pointer}),
    .CLKA(clk),
    .DIA(data_in),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(wr & (~fifo_full)),
    .ADDRB({3'h0, read_address}),
    .CLKB(clk),
    .DIB(8'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
  RAMB4_S4_S4 info_fifo
  (
    .DOA(),
    .DOB(length_info),
    .ADDRA({4'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA(len_cnt & {4{~initialize_memories}}),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({4'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(4'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
  RAMB4_S1_S1 overrun_fifo
  (
    .DOA(),
    .DOB(overrun),
    .ADDRA({6'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({6'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(1'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
`else
`ifdef VIRTUALSILICON_RAM
 
`ifdef CAN_BIST
    vs_hdtp_64x8_bist fifo
`else
    vs_hdtp_64x8 fifo
`endif
    (
        .RCK        (clk),
        .WCK        (clk),
        .RADR       (read_address),
        .WADR       (wr_pointer),
        .DI         (data_in),
        .DOUT       (data_out),
        .REN        (~fifo_selected),
        .WEN        (~(wr & (~fifo_full)))
    `ifdef CAN_BIST
        ,
        // debug chain signals
        .mbist_si_i   (mbist_si_i),
        .mbist_so_o   (mbist_s_0),
        .mbist_ctrl_i   (mbist_ctrl_i)
    `endif
    );
 
`ifdef CAN_BIST
    vs_hdtp_64x4_bist info_fifo
`else
    vs_hdtp_64x4 info_fifo
`endif
    (
        .RCK        (clk),
        .WCK        (clk),
        .RADR       (rd_info_pointer),
        .WADR       (wr_info_pointer),
        .DI         (len_cnt & {4{~initialize_memories}}),
        .DOUT       (length_info),
        .REN        (1'b0),
        .WEN        (~(write_length_info & (~info_full) | initialize_memories))
    `ifdef CAN_BIST
        ,
        // debug chain signals
        .mbist_si_i   (mbist_s_0),
        .mbist_so_o   (mbist_so_o),
        .mbist_ctrl_i   (mbist_ctrl_i)
    `endif
    );
 
    // overrun_info
    always @ (posedge clk)
    begin
      if (write_length_info & (~info_full) | initialize_memories)
        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
    end
 
 
    // reading overrun
    assign overrun = overrun_info[rd_info_pointer];
 
`else
`ifdef ARTISAN_RAM
 
`ifdef CAN_BIST
    art_hstp_64x8_bist fifo
    (
        .CLKR       (clk),
        .CLKW       (clk),
        .AR         (read_address),
        .AW         (wr_pointer),
        .D          (data_in),
        .Q          (data_out),
        .REN        (~fifo_selected),
        .WEN        (~(wr & (~fifo_full))),
        .mbist_si_i   (mbist_si_i),
        .mbist_so_o   (mbist_s_0),
        .mbist_ctrl_i   (mbist_ctrl_i)
    );
    art_hstp_64x4_bist info_fifo
    (
        .CLKR       (clk),
        .CLKW       (clk),
        .AR         (rd_info_pointer),
        .AW         (wr_info_pointer),
        .D          (len_cnt & {4{~initialize_memories}}),
        .Q          (length_info),
        .REN        (1'b0),
        .WEN        (~(write_length_info & (~info_full) | initialize_memories)),
        .mbist_si_i   (mbist_s_0),
        .mbist_so_o   (mbist_so_o),
        .mbist_ctrl_i   (mbist_ctrl_i)
    );
`else
    art_hsdp_64x8 fifo
    (
        .CENA       (1'b0),
        .CENB       (1'b0),
        .CLKA       (clk),
        .CLKB       (clk),
        .AA         (read_address),
        .AB         (wr_pointer),
        .DA         (8'h00),
        .DB         (data_in),
        .QA         (data_out),
        .QB         (),
        .OENA       (~fifo_selected),
        .OENB       (1'b1),
        .WENA       (1'b1),
        .WENB       (~(wr & (~fifo_full)))
    );
    art_hsdp_64x4 info_fifo
    (
        .CENA       (1'b0),
        .CENB       (1'b0),
        .CLKA       (clk),
        .CLKB       (clk),
        .AA         (rd_info_pointer),
        .AB         (wr_info_pointer),
        .DA         (4'h0),
        .DB         (len_cnt & {4{~initialize_memories}}),
        .QA         (length_info),
        .QB         (),
        .OENA       (1'b0),
        .OENB       (1'b1),
        .WENA       (1'b1),
        .WENB       (~(write_length_info & (~info_full) | initialize_memories))
    );
`endif
 
    // overrun_info
    always @ (posedge clk)
    begin
      if (write_length_info & (~info_full) | initialize_memories)
        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
    end
 
 
    // reading overrun
    assign overrun = overrun_info[rd_info_pointer];
 
`else
  // writing data to fifo
  always @ (posedge clk)
  begin
    if (wr & (~fifo_full))
      fifo[wr_pointer] <=#Tp data_in;
  end
 
  // reading from fifo
  assign data_out = fifo[read_address];
 
 
  // writing length_fifo
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
  end
 
 
  // reading length_fifo
  assign length_info = length_fifo[rd_info_pointer];
 
  // overrun_info
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
  end
 
 
  // reading overrun
  assign overrun = overrun_info[rd_info_pointer];
 
 
`endif
`endif
`endif
`endif
`endif
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	11	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_fifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	137	mohor	`//// Copyright (C) 2002, 2003, 2004 Authors ////`
21	11	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	11	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	137	mohor	`// Revision 1.25 2003/10/23 16:52:17 mohor`
54			`// Active high/low problem when Altera devices are used. Bug fixed by`
55			`// Rojhalat Ibrahim.`
56			`//`
57	134	mohor	`// Revision 1.24 2003/10/17 05:55:20 markom`
58			`// mbist signals updated according to newest convention`
59			`//`
60	130	markom	`// Revision 1.23 2003/09/05 12:46:41 mohor`
61			`// ALTERA_RAM supported.`
62			`//`
63	124	mohor	`// Revision 1.22 2003/08/20 09:59:16 mohor`
64			`// Artisan RAM fixed (when not using BIST).`
65			`//`
66	118	mohor	`// Revision 1.21 2003/08/14 16:04:52 simons`
67			`// Artisan ram instances added.`
68			`//`
69	115	simons	`// Revision 1.20 2003/07/16 14:00:45 mohor`
70			`// Fixed according to the linter.`
71			`//`
72	109	mohor	`// Revision 1.19 2003/07/03 09:30:44 mohor`
73			`// PCI_BIST replaced with CAN_BIST.`
74			`//`
75	99	mohor	`// Revision 1.18 2003/06/27 22:14:23 simons`
76			`// Overrun fifo implemented with FFs, because it is not possible to create such a memory.`
77			`//`
78	97	simons	`// Revision 1.17 2003/06/27 20:56:15 simons`
79			`// Virtual silicon ram instances added.`
80			`//`
81	95	simons	`// Revision 1.16 2003/06/18 23:03:44 mohor`
82			`// Typo fixed.`
83			`//`
84	85	mohor	`// Revision 1.15 2003/06/11 09:37:05 mohor`
85			`// overrun and length_info fifos are initialized at the end of reset.`
86			`//`
87	73	mohor	`// Revision 1.14 2003/03/05 15:02:30 mohor`
88			`// Xilinx RAM added.`
89			`//`
90	51	mohor	`// Revision 1.13 2003/03/01 22:53:33 mohor`
91			`// Actel APA ram supported.`
92			`//`
93	48	mohor	`// Revision 1.12 2003/02/19 14:44:03 mohor`
94			`// CAN core finished. Host interface added. Registers finished.`
95			`// Synchronization to the wishbone finished.`
96			`//`
97	39	mohor	`// Revision 1.11 2003/02/14 20:17:01 mohor`
98			`// Several registers added. Not finished, yet.`
99			`//`
100	35	mohor	`// Revision 1.10 2003/02/11 00:56:06 mohor`
101			`// Wishbone interface added.`
102			`//`
103	31	mohor	`// Revision 1.9 2003/02/09 02:24:33 mohor`
104			`// Bosch license warning added. Error counters finished. Overload frames`
105			`// still need to be fixed.`
106			`//`
107	28	mohor	`// Revision 1.8 2003/01/31 01:13:38 mohor`
108			`// backup.`
109			`//`
110	24	mohor	`// Revision 1.7 2003/01/17 17:44:31 mohor`
111			`// Fifo corrected to be synthesizable.`
112			`//`
113	23	mohor	`// Revision 1.6 2003/01/15 13:16:47 mohor`
114	31	mohor	`// When a frame with "remote request" is received, no data is stored`
115			`// to fifo, just the frame information (identifier, ...). Data length`
116			`// that is stored is the received data length and not the actual data`
117			`// length that is stored to fifo.`
118	23	mohor	`//`
119	18	mohor	`// Revision 1.5 2003/01/14 17:25:09 mohor`
120			`// Addresses corrected to decimal values (previously hex).`
121			`//`
122	17	mohor	`// Revision 1.4 2003/01/14 12:19:35 mohor`
123			`// rx_fifo is now working.`
124			`//`
125	16	mohor	`// Revision 1.3 2003/01/09 21:54:45 mohor`
126			`// rx fifo added. Not 100 % verified, yet.`
127			`//`
128	14	mohor	`// Revision 1.2 2003/01/09 14:46:58 mohor`
129			`// Temporary files (backup).`
130			`//`
131	13	mohor	`// Revision 1.1 2003/01/08 02:10:55 mohor`
132			`// Acceptance filter added.`
133	11	mohor	`//`
134			`//`
135			`//`
136	13	mohor	`//`
137	11	mohor
138			`// synopsys translate_off`
139			`include "timescale.v"
140			`// synopsys translate_on`
141			`include "can_defines.v"
142
143			`module can_fifo`
144			`(`
145			`clk,`
146			`rst,`
147
148			`wr,`
149
150			`data_in,`
151	14	mohor	`addr,`
152	11	mohor	`data_out,`
153	48	mohor	`fifo_selected,`
154	11	mohor
155			`reset_mode,`
156	14	mohor	`release_buffer,`
157	35	mohor	`extended_mode,`
158			`overrun,`
159	39	mohor	`info_empty,`
160			`info_cnt`
161	13	mohor
162	95	simons	`ifdef CAN_BIST
163			`,`
164	130	markom	`mbist_si_i,`
165			`mbist_so_o,`
166			`mbist_ctrl_i`
167	95	simons	`endif
168	11	mohor	`);`
169
170			`parameter Tp = 1;`
171
172			`input clk;`
173			`input rst;`
174			`input wr;`
175			`input [7:0] data_in;`
176	109	mohor	`input [5:0] addr;`
177	11	mohor	`input reset_mode;`
178			`input release_buffer;`
179	14	mohor	`input extended_mode;`
180	48	mohor	`input fifo_selected;`
181	11	mohor
182	13	mohor	`output [7:0] data_out;`
183	35	mohor	`output overrun;`
184			`output info_empty;`
185	39	mohor	`output [6:0] info_cnt;`
186	11	mohor
187	95	simons	`ifdef CAN_BIST
188	130	markom	`input mbist_si_i;`
189			`output mbist_so_o;`
190			input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
191			`wire mbist_s_0;`
192	95	simons	`endif
193
194	124	mohor	`ifdef ALTERA_RAM
195			`else
196	48	mohor	`ifdef ACTEL_APA_RAM
197			`else
198	51	mohor	`ifdef XILINX_RAM
199			`else
200	115	simons	`ifdef ARTISAN_RAM
201			`reg overrun_info[0:63];`
202			`else
203	95	simons	`ifdef VIRTUALSILICON_RAM
204	97	simons	`reg overrun_info[0:63];`
205	95	simons	`else
206	48	mohor	`reg [7:0] fifo [0:63];`
207			`reg [3:0] length_fifo[0:63];`
208			`reg overrun_info[0:63];`
209			`endif
210	51	mohor	`endif
211	95	simons	`endif
212	115	simons	`endif
213	124	mohor	`endif
214	11	mohor
215			`reg [5:0] rd_pointer;`
216			`reg [5:0] wr_pointer;`
217	14	mohor	`reg [5:0] read_address;`
218	16	mohor	`reg [5:0] wr_info_pointer;`
219			`reg [5:0] rd_info_pointer;`
220	13	mohor	`reg wr_q;`
221			`reg [3:0] len_cnt;`
222	16	mohor	`reg [6:0] fifo_cnt;`
223	24	mohor	`reg [6:0] info_cnt;`
224	16	mohor	`reg latch_overrun;`
225	73	mohor	`reg initialize_memories;`
226	11	mohor
227	48	mohor	`wire [3:0] length_info;`
228	13	mohor	`wire write_length_info;`
229	16	mohor	`wire fifo_empty;`
230			`wire fifo_full;`
231	24	mohor	`wire info_full;`
232	11	mohor
233	13	mohor	`assign write_length_info = (~wr) & wr_q;`
234
235			`// Delayed write signal`
236			`always @ (posedge clk or posedge rst)`
237			`begin`
238			`if (rst)`
239	109	mohor	`wr_q <=#Tp 1'b0;`
240	13	mohor	`else if (reset_mode)`
241	109	mohor	`wr_q <=#Tp 1'b0;`
242	13	mohor	`else`
243			`wr_q <=#Tp wr;`
244			`end`
245
246
247			`// length counter`
248			`always @ (posedge clk or posedge rst)`
249			`begin`
250			`if (rst)`
251	109	mohor	`len_cnt <= 4'h0;`
252	13	mohor	`else if (reset_mode \| write_length_info)`
253	109	mohor	`len_cnt <=#Tp 4'h0;`
254	16	mohor	`else if (wr & (~fifo_full))`
255	13	mohor	`len_cnt <=#Tp len_cnt + 1'b1;`
256			`end`
257
258
259			`// wr_info_pointer`
260			`always @ (posedge clk or posedge rst)`
261			`begin`
262			`if (rst)`
263	109	mohor	`wr_info_pointer <= 6'h0;`
264	73	mohor	`else if (write_length_info & (~info_full) \| initialize_memories)`
265			`wr_info_pointer <=#Tp wr_info_pointer + 1'b1;`
266	13	mohor	`else if (reset_mode)`
267	109	mohor	`wr_info_pointer <=#Tp 6'h0;`
268	13	mohor	`end`
269
270
271
272			`// rd_info_pointer`
273	11	mohor	`always @ (posedge clk or posedge rst)`
274			`begin`
275			`if (rst)`
276	109	mohor	`rd_info_pointer <= 6'h0;`
277	11	mohor	`else if (reset_mode)`
278	109	mohor	`rd_info_pointer <=#Tp 6'h0;`
279	16	mohor	`else if (release_buffer & (~fifo_empty))`
280	13	mohor	`rd_info_pointer <=#Tp rd_info_pointer + 1'b1;`
281	11	mohor	`end`
282
283
284			`// rd_pointer`
285			`always @ (posedge clk or posedge rst)`
286			`begin`
287			`if (rst)`
288	109	mohor	`rd_pointer <= 5'h0;`
289	16	mohor	`else if (release_buffer & (~fifo_empty))`
290	109	mohor	`rd_pointer <=#Tp rd_pointer + {2'h0, length_info};`
291	11	mohor	`else if (reset_mode)`
292	109	mohor	`rd_pointer <=#Tp 5'h0;`
293	11	mohor	`end`
294
295
296			`// wr_pointer`
297			`always @ (posedge clk or posedge rst)`
298			`begin`
299			`if (rst)`
300	109	mohor	`wr_pointer <= 5'h0;`
301	16	mohor	`else if (wr & (~fifo_full))`
302	13	mohor	`wr_pointer <=#Tp wr_pointer + 1'b1;`
303	11	mohor	`else if (reset_mode)`
304	109	mohor	`wr_pointer <=#Tp 5'h0;`
305	11	mohor	`end`
306
307
308	16	mohor	`// latch_overrun`
309			`always @ (posedge clk or posedge rst)`
310			`begin`
311			`if (rst)`
312	109	mohor	`latch_overrun <= 1'b0;`
313	16	mohor	`else if (reset_mode \| write_length_info)`
314	109	mohor	`latch_overrun <=#Tp 1'b0;`
315	16	mohor	`else if (wr & fifo_full)`
316			`latch_overrun <=#Tp 1'b1;`
317			`end`
318
319
320			`// Counting data in fifo`
321			`always @ (posedge clk or posedge rst)`
322			`begin`
323			`if (rst)`
324	109	mohor	`fifo_cnt <= 7'h0;`
325	16	mohor	`else if (wr & (~release_buffer) & (~fifo_full))`
326			`fifo_cnt <=#Tp fifo_cnt + 1'b1;`
327			`else if ((~wr) & release_buffer & (~fifo_empty))`
328	109	mohor	`fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};`
329	16	mohor	`else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))`
330	109	mohor	`fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;`
331	16	mohor	`else if (reset_mode)`
332	109	mohor	`fifo_cnt <=#Tp 7'h0;`
333	16	mohor	`end`
334
335	109	mohor	`assign fifo_full = fifo_cnt == 7'd64;`
336			`assign fifo_empty = fifo_cnt == 7'd0;`
337	16	mohor
338
339	48	mohor	`// Counting data in length_fifo and overrun_info fifo`
340	24	mohor	`always @ (posedge clk or posedge rst)`
341			`begin`
342			`if (rst)`
343	109	mohor	`info_cnt <=#Tp 7'h0;`
344			`else if (reset_mode)`
345			`info_cnt <=#Tp 7'h0;`
346	24	mohor	`else if (write_length_info ^ release_buffer)`
347			`begin`
348			`if (release_buffer & (~info_empty))`
349			`info_cnt <=#Tp info_cnt - 1'b1;`
350			`else if (write_length_info & (~info_full))`
351			`info_cnt <=#Tp info_cnt + 1'b1;`
352			`end`
353			`end`
354
355	109	mohor	`assign info_full = info_cnt == 7'd64;`
356			`assign info_empty = info_cnt == 7'd0;`
357	16	mohor
358	24	mohor
359	14	mohor	`// Selecting which address will be used for reading data from rx fifo`
360			`always @ (extended_mode or rd_pointer or addr)`
361			`begin`
362			`if (extended_mode) // extended mode`
363	109	mohor	`read_address = rd_pointer + (addr - 6'd16);`
364	14	mohor	`else // normal mode`
365	109	mohor	`read_address = rd_pointer + (addr - 6'd20);`
366	14	mohor	`end`
367	11	mohor
368
369	73	mohor	`always @ (posedge clk or posedge rst)`
370			`begin`
371			`if (rst)`
372	109	mohor	`initialize_memories <= 1'b1;`
373	73	mohor	`else if (&wr_info_pointer)`
374			`initialize_memories <=#Tp 1'b0;`
375			`end`
376	14	mohor
377	73	mohor
378	124	mohor	`ifdef ALTERA_RAM
379			`// altera_ram_64x8_sync fifo`
380			`lpm_ram_dp fifo`
381			`(`
382			`.q (data_out),`
383			`.rdclock (clk),`
384			`.wrclock (clk),`
385			`.data (data_in),`
386	134	mohor	`.wren (wr & (~fifo_full)),`
387			`.rden (fifo_selected),`
388	124	mohor	`.wraddress (wr_pointer),`
389			`.rdaddress (read_address)`
390			`);`
391			`defparam fifo.lpm_width = 8;`
392			`defparam fifo.lpm_widthad = 6;`
393	134	mohor	`defparam fifo.lpm_numwords = 64;`
394	124	mohor
395
396			`// altera_ram_64x4_sync info_fifo`
397			`lpm_ram_dp info_fifo`
398			`(`
399			`.q (length_info),`
400			`.rdclock (clk),`
401			`.wrclock (clk),`
402			`.data (len_cnt & {4{~initialize_memories}}),`
403	134	mohor	`.wren (write_length_info & (~info_full) \| initialize_memories),`
404	124	mohor	`.wraddress (wr_info_pointer),`
405			`.rdaddress (rd_info_pointer)`
406			`);`
407			`defparam info_fifo.lpm_width = 4;`
408			`defparam info_fifo.lpm_widthad = 6;`
409	134	mohor	`defparam info_fifo.lpm_numwords = 64;`
410	124	mohor
411
412			`// altera_ram_64x1_sync overrun_fifo`
413			`lpm_ram_dp overrun_fifo`
414			`(`
415			`.q (overrun),`
416			`.rdclock (clk),`
417			`.wrclock (clk),`
418			`.data ((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
419	134	mohor	`.wren (write_length_info & (~info_full) \| initialize_memories),`
420	124	mohor	`.wraddress (wr_info_pointer),`
421			`.rdaddress (rd_info_pointer)`
422			`);`
423			`defparam overrun_fifo.lpm_width = 1;`
424			`defparam overrun_fifo.lpm_widthad = 6;`
425	134	mohor	`defparam overrun_fifo.lpm_numwords = 64;`
426	124	mohor
427			`else
428	48	mohor	`ifdef ACTEL_APA_RAM
429			`actel_ram_64x8_sync fifo`
430			`(`
431			`.DO (data_out),`
432			`.RCLOCK (clk),`
433			`.WCLOCK (clk),`
434			`.DI (data_in),`
435			`.PO (), // parity not used`
436			`.WRB (~(wr & (~fifo_full))),`
437			`.RDB (~fifo_selected),`
438			`.WADDR (wr_pointer),`
439			`.RADDR (read_address)`
440			`);`
441	14	mohor
442
443	48	mohor	`actel_ram_64x4_sync info_fifo`
444			`(`
445			`.DO (length_info),`
446			`.RCLOCK (clk),`
447			`.WCLOCK (clk),`
448	73	mohor	`.DI (len_cnt & {4{~initialize_memories}}),`
449	48	mohor	`.PO (), // parity not used`
450	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
451	48	mohor	`.RDB (1'b0), // always enabled`
452			`.WADDR (wr_info_pointer),`
453			`.RADDR (rd_info_pointer)`
454			`);`
455	14	mohor
456
457	48	mohor	`actel_ram_64x1_sync overrun_fifo`
458			`(`
459			`.DO (overrun),`
460			`.RCLOCK (clk),`
461			`.WCLOCK (clk),`
462	73	mohor	`.DI ((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
463	48	mohor	`.PO (), // parity not used`
464	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
465	48	mohor	`.RDB (1'b0), // always enabled`
466			`.WADDR (wr_info_pointer),`
467			`.RADDR (rd_info_pointer)`
468			`);`
469			`else
470	51	mohor	`ifdef XILINX_RAM
471
472			`RAMB4_S8_S8 fifo`
473			`(`
474			`.DOA(),`
475			`.DOB(data_out),`
476			`.ADDRA({3'h0, wr_pointer}),`
477			`.CLKA(clk),`
478			`.DIA(data_in),`
479			`.ENA(1'b1),`
480			`.RSTA(1'b0),`
481			`.WEA(wr & (~fifo_full)),`
482			`.ADDRB({3'h0, read_address}),`
483			`.CLKB(clk),`
484			`.DIB(8'h0),`
485			`.ENB(1'b1),`
486			`.RSTB(1'b0),`
487			`.WEB(1'b0)`
488			`);`
489
490
491			`RAMB4_S4_S4 info_fifo`
492			`(`
493			`.DOA(),`
494			`.DOB(length_info),`
495			`.ADDRA({4'h0, wr_info_pointer}),`
496			`.CLKA(clk),`
497	73	mohor	`.DIA(len_cnt & {4{~initialize_memories}}),`
498	51	mohor	`.ENA(1'b1),`
499			`.RSTA(1'b0),`
500	73	mohor	`.WEA(write_length_info & (~info_full) \| initialize_memories),`

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