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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_fifo.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003, 2004 Authors                       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.26  2004/02/08 14:30:57  mohor
// Header changed.
//
// Revision 1.25  2003/10/23 16:52:17  mohor
// Active high/low problem when Altera devices are used. Bug fixed by
// Rojhalat Ibrahim.
//
// Revision 1.24  2003/10/17 05:55:20  markom
// mbist signals updated according to newest convention
//
// Revision 1.23  2003/09/05 12:46:41  mohor
// ALTERA_RAM supported.
//
// Revision 1.22  2003/08/20 09:59:16  mohor
// Artisan RAM fixed (when not using BIST).
//
// Revision 1.21  2003/08/14 16:04:52  simons
// Artisan ram instances added.
//
// Revision 1.20  2003/07/16 14:00:45  mohor
// Fixed according to the linter.
//
// Revision 1.19  2003/07/03 09:30:44  mohor
// PCI_BIST replaced with CAN_BIST.
//
// Revision 1.18  2003/06/27 22:14:23  simons
// Overrun fifo implemented with FFs, because it is not possible to create such a memory.
//
// Revision 1.17  2003/06/27 20:56:15  simons
// Virtual silicon ram instances added.
//
// Revision 1.16  2003/06/18 23:03:44  mohor
// Typo fixed.
//
// Revision 1.15  2003/06/11 09:37:05  mohor
// overrun and length_info fifos are initialized at the end of reset.
//
// Revision 1.14  2003/03/05 15:02:30  mohor
// Xilinx RAM added.
//
// Revision 1.13  2003/03/01 22:53:33  mohor
// Actel APA ram supported.
//
// Revision 1.12  2003/02/19 14:44:03  mohor
// CAN core finished. Host interface added. Registers finished.
// Synchronization to the wishbone finished.
//
// Revision 1.11  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.10  2003/02/11 00:56:06  mohor
// Wishbone interface added.
//
// Revision 1.9  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.8  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.7  2003/01/17 17:44:31  mohor
// Fifo corrected to be synthesizable.
//
// Revision 1.6  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored
// to fifo, just the frame information (identifier, ...). Data length
// that is stored is the received data length and not the actual data
// length that is stored to fifo.
//
// Revision 1.5  2003/01/14 17:25:09  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.4  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.3  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.2  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.1  2003/01/08 02:10:55  mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_fifo
(
  clk,
  rst,
 
  wr,
 
  data_in,
  addr,
  data_out,
  fifo_selected,
 
  reset_mode,
  release_buffer,
  extended_mode,
  overrun,
  info_empty,
  info_cnt
 
`ifdef CAN_BIST
  ,
  mbist_si_i,
  mbist_so_o,
  mbist_ctrl_i
`endif
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         wr;
input   [7:0] data_in;
input   [5:0] addr;
input         reset_mode;
input         release_buffer;
input         extended_mode;
input         fifo_selected;
 
output  [7:0] data_out;
output        overrun;
output        info_empty;
output  [6:0] info_cnt;
 
`ifdef CAN_BIST
input         mbist_si_i;
output        mbist_so_o;
input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
wire          mbist_s_0;
`endif
 
`ifdef ALTERA_RAM
`else
`ifdef ACTEL_APA_RAM
`else
`ifdef XILINX_RAM
`else
`ifdef ARTISAN_RAM
  reg           overrun_info[0:63];
`else
`ifdef VIRTUALSILICON_RAM
  reg           overrun_info[0:63];
`else
  reg     [7:0] fifo [0:63];
  reg     [3:0] length_fifo[0:63];
  reg           overrun_info[0:63];
`endif
`endif
`endif
`endif
`endif
 
reg     [5:0] rd_pointer;
reg     [5:0] wr_pointer;
reg     [5:0] read_address;
reg     [5:0] wr_info_pointer;
reg     [5:0] rd_info_pointer;
reg           wr_q;
reg     [3:0] len_cnt;
reg     [6:0] fifo_cnt;
reg     [6:0] info_cnt;
reg           latch_overrun;
reg           initialize_memories;
 
wire    [3:0] length_info;
wire          write_length_info;
wire          fifo_empty;
wire          fifo_full;
wire          info_full;
 
assign write_length_info = (~wr) & wr_q;
 
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_q <=#Tp 1'b0;
  else if (reset_mode)
    wr_q <=#Tp 1'b0;
  else
    wr_q <=#Tp wr;
end
 
 
// length counter
always @ (posedge clk or posedge rst)
begin
  if (rst)
    len_cnt <= 4'h0;
  else if (reset_mode | write_length_info)
    len_cnt <=#Tp 4'h0;
  else if (wr & (~fifo_full))
    len_cnt <=#Tp len_cnt + 1'b1;
end
 
 
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_info_pointer <= 6'h0;
  else if (write_length_info & (~info_full) | initialize_memories)
    wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
  else if (reset_mode)
    wr_info_pointer <=#Tp rd_info_pointer;
end
 
 
 
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_info_pointer <= 6'h0;
  else if (release_buffer & (~fifo_empty))
    rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
 
 
// rd_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_pointer <= 5'h0;
  else if (release_buffer & (~fifo_empty))
    rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
end
 
 
// wr_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_pointer <= 5'h0;
  else if (reset_mode)
    wr_pointer <=#Tp rd_pointer;
  else if (wr & (~fifo_full))
    wr_pointer <=#Tp wr_pointer + 1'b1;
end
 
 
// latch_overrun
always @ (posedge clk or posedge rst)
begin
  if (rst)
    latch_overrun <= 1'b0;
  else if (reset_mode | write_length_info)
    latch_overrun <=#Tp 1'b0;
  else if (wr & fifo_full)
    latch_overrun <=#Tp 1'b1;
end
 
 
// Counting data in fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    fifo_cnt <= 7'h0;
  else if (reset_mode)
    fifo_cnt <=#Tp 7'h0;
  else if (wr & (~release_buffer) & (~fifo_full))
    fifo_cnt <=#Tp fifo_cnt + 1'b1;
  else if ((~wr) & release_buffer & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
  else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
end
 
assign fifo_full = fifo_cnt == 7'd64;
assign fifo_empty = fifo_cnt == 7'd0;
 
 
// Counting data in length_fifo and overrun_info fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    info_cnt <=#Tp 7'h0;
  else if (reset_mode)
    info_cnt <=#Tp 7'h0;
  else if (write_length_info ^ release_buffer)
    begin
      if (release_buffer & (~info_empty))
        info_cnt <=#Tp info_cnt - 1'b1;
      else if (write_length_info & (~info_full))
        info_cnt <=#Tp info_cnt + 1'b1;
    end
end
 
assign info_full = info_cnt == 7'd64;
assign info_empty = info_cnt == 7'd0;
 
 
// Selecting which address will be used for reading data from rx fifo
always @ (extended_mode or rd_pointer or addr)
begin
  if (extended_mode)      // extended mode
    read_address = rd_pointer + (addr - 6'd16);
  else                    // normal mode
    read_address = rd_pointer + (addr - 6'd20);
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    initialize_memories <= 1'b1;
  else if (&wr_info_pointer)
    initialize_memories <=#Tp 1'b0;
end
 
 
`ifdef ALTERA_RAM
//  altera_ram_64x8_sync fifo
  lpm_ram_dp fifo
  (
    .q         (data_out),
    .rdclock   (clk),
    .wrclock   (clk),
    .data      (data_in),
    .wren      (wr & (~fifo_full)),
    .rden      (fifo_selected),
    .wraddress (wr_pointer),
    .rdaddress (read_address)
  );
  defparam fifo.lpm_width = 8;
  defparam fifo.lpm_widthad = 6;
  defparam fifo.lpm_numwords = 64;
 
 
//  altera_ram_64x4_sync info_fifo
  lpm_ram_dp info_fifo
  (
    .q         (length_info),
    .rdclock   (clk),
    .wrclock   (clk),
    .data      (len_cnt & {4{~initialize_memories}}),
    .wren      (write_length_info & (~info_full) | initialize_memories),
    .wraddress (wr_info_pointer),
    .rdaddress (rd_info_pointer)
  );
  defparam info_fifo.lpm_width = 4;
  defparam info_fifo.lpm_widthad = 6;
  defparam info_fifo.lpm_numwords = 64;
 
 
//  altera_ram_64x1_sync overrun_fifo
  lpm_ram_dp overrun_fifo
  (
    .q         (overrun),
    .rdclock   (clk),
    .wrclock   (clk),
    .data      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .wren      (write_length_info & (~info_full) | initialize_memories),
    .wraddress (wr_info_pointer),
    .rdaddress (rd_info_pointer)
  );
  defparam overrun_fifo.lpm_width = 1;
  defparam overrun_fifo.lpm_widthad = 6;
  defparam overrun_fifo.lpm_numwords = 64;
 
`else
`ifdef ACTEL_APA_RAM
  actel_ram_64x8_sync fifo
  (
    .DO      (data_out),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (data_in),
    .PO      (),                       // parity not used
    .WRB     (~(wr & (~fifo_full))),
    .RDB     (~fifo_selected),
    .WADDR   (wr_pointer),
    .RADDR   (read_address)
  );
 
 
  actel_ram_64x4_sync info_fifo
  (
    .DO      (length_info),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (len_cnt & {4{~initialize_memories}}),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
 
 
  actel_ram_64x1_sync overrun_fifo
  (
    .DO      (overrun),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
`else
`ifdef XILINX_RAM
 
  RAMB4_S8_S8 fifo
  (
    .DOA(),
    .DOB(data_out),
    .ADDRA({3'h0, wr_pointer}),
    .CLKA(clk),
    .DIA(data_in),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(wr & (~fifo_full)),
    .ADDRB({3'h0, read_address}),
    .CLKB(clk),
    .DIB(8'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
  RAMB4_S4_S4 info_fifo
  (
    .DOA(),
    .DOB(length_info),
    .ADDRA({4'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA(len_cnt & {4{~initialize_memories}}),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({4'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(4'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
  RAMB4_S1_S1 overrun_fifo
  (
    .DOA(),
    .DOB(overrun),
    .ADDRA({6'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({6'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(1'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
`else
`ifdef VIRTUALSILICON_RAM
 
`ifdef CAN_BIST
    vs_hdtp_64x8_bist fifo
`else
    vs_hdtp_64x8 fifo
`endif
    (
        .RCK        (clk),
        .WCK        (clk),
        .RADR       (read_address),
        .WADR       (wr_pointer),
        .DI         (data_in),
        .DOUT       (data_out),
        .REN        (~fifo_selected),
        .WEN        (~(wr & (~fifo_full)))
    `ifdef CAN_BIST
        ,
        // debug chain signals
        .mbist_si_i   (mbist_si_i),
        .mbist_so_o   (mbist_s_0),
        .mbist_ctrl_i   (mbist_ctrl_i)
    `endif
    );
 
`ifdef CAN_BIST
    vs_hdtp_64x4_bist info_fifo
`else
    vs_hdtp_64x4 info_fifo
`endif
    (
        .RCK        (clk),
        .WCK        (clk),
        .RADR       (rd_info_pointer),
        .WADR       (wr_info_pointer),
        .DI         (len_cnt & {4{~initialize_memories}}),
        .DOUT       (length_info),
        .REN        (1'b0),
        .WEN        (~(write_length_info & (~info_full) | initialize_memories))
    `ifdef CAN_BIST
        ,
        // debug chain signals
        .mbist_si_i   (mbist_s_0),
        .mbist_so_o   (mbist_so_o),
        .mbist_ctrl_i   (mbist_ctrl_i)
    `endif
    );
 
    // overrun_info
    always @ (posedge clk)
    begin
      if (write_length_info & (~info_full) | initialize_memories)
        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
    end
 
 
    // reading overrun
    assign overrun = overrun_info[rd_info_pointer];
 
`else
`ifdef ARTISAN_RAM
 
`ifdef CAN_BIST
    art_hstp_64x8_bist fifo
    (
        .CLKR       (clk),
        .CLKW       (clk),
        .AR         (read_address),
        .AW         (wr_pointer),
        .D          (data_in),
        .Q          (data_out),
        .REN        (~fifo_selected),
        .WEN        (~(wr & (~fifo_full))),
        .mbist_si_i   (mbist_si_i),
        .mbist_so_o   (mbist_s_0),
        .mbist_ctrl_i   (mbist_ctrl_i)
    );
    art_hstp_64x4_bist info_fifo
    (
        .CLKR       (clk),
        .CLKW       (clk),
        .AR         (rd_info_pointer),
        .AW         (wr_info_pointer),
        .D          (len_cnt & {4{~initialize_memories}}),
        .Q          (length_info),
        .REN        (1'b0),
        .WEN        (~(write_length_info & (~info_full) | initialize_memories)),
        .mbist_si_i   (mbist_s_0),
        .mbist_so_o   (mbist_so_o),
        .mbist_ctrl_i   (mbist_ctrl_i)
    );
`else
    art_hsdp_64x8 fifo
    (
        .CENA       (1'b0),
        .CENB       (1'b0),
        .CLKA       (clk),
        .CLKB       (clk),
        .AA         (read_address),
        .AB         (wr_pointer),
        .DA         (8'h00),
        .DB         (data_in),
        .QA         (data_out),
        .QB         (),
        .OENA       (~fifo_selected),
        .OENB       (1'b1),
        .WENA       (1'b1),
        .WENB       (~(wr & (~fifo_full)))
    );
    art_hsdp_64x4 info_fifo
    (
        .CENA       (1'b0),
        .CENB       (1'b0),
        .CLKA       (clk),
        .CLKB       (clk),
        .AA         (rd_info_pointer),
        .AB         (wr_info_pointer),
        .DA         (4'h0),
        .DB         (len_cnt & {4{~initialize_memories}}),
        .QA         (length_info),
        .QB         (),
        .OENA       (1'b0),
        .OENB       (1'b1),
        .WENA       (1'b1),
        .WENB       (~(write_length_info & (~info_full) | initialize_memories))
    );
`endif
 
    // overrun_info
    always @ (posedge clk)
    begin
      if (write_length_info & (~info_full) | initialize_memories)
        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
    end
 
 
    // reading overrun
    assign overrun = overrun_info[rd_info_pointer];
 
`else
  // writing data to fifo
  always @ (posedge clk)
  begin
    if (wr & (~fifo_full))
      fifo[wr_pointer] <=#Tp data_in;
  end
 
  // reading from fifo
  assign data_out = fifo[read_address];
 
 
  // writing length_fifo
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
  end
 
 
  // reading length_fifo
  assign length_info = length_fifo[rd_info_pointer];
 
  // overrun_info
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
  end
 
 
  // reading overrun
  assign overrun = overrun_info[rd_info_pointer];
 
 
`endif
`endif
`endif
`endif
`endif
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	11	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_fifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20	137	mohor	`//// Copyright (C) 2002, 2003, 2004 Authors ////`
21	11	mohor	`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	11	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	152	igorm	`// Revision 1.26 2004/02/08 14:30:57 mohor`
54			`// Header changed.`
55			`//`
56	137	mohor	`// Revision 1.25 2003/10/23 16:52:17 mohor`
57			`// Active high/low problem when Altera devices are used. Bug fixed by`
58			`// Rojhalat Ibrahim.`
59			`//`
60	134	mohor	`// Revision 1.24 2003/10/17 05:55:20 markom`
61			`// mbist signals updated according to newest convention`
62			`//`
63	130	markom	`// Revision 1.23 2003/09/05 12:46:41 mohor`
64			`// ALTERA_RAM supported.`
65			`//`
66	124	mohor	`// Revision 1.22 2003/08/20 09:59:16 mohor`
67			`// Artisan RAM fixed (when not using BIST).`
68			`//`
69	118	mohor	`// Revision 1.21 2003/08/14 16:04:52 simons`
70			`// Artisan ram instances added.`
71			`//`
72	115	simons	`// Revision 1.20 2003/07/16 14:00:45 mohor`
73			`// Fixed according to the linter.`
74			`//`
75	109	mohor	`// Revision 1.19 2003/07/03 09:30:44 mohor`
76			`// PCI_BIST replaced with CAN_BIST.`
77			`//`
78	99	mohor	`// Revision 1.18 2003/06/27 22:14:23 simons`
79			`// Overrun fifo implemented with FFs, because it is not possible to create such a memory.`
80			`//`
81	97	simons	`// Revision 1.17 2003/06/27 20:56:15 simons`
82			`// Virtual silicon ram instances added.`
83			`//`
84	95	simons	`// Revision 1.16 2003/06/18 23:03:44 mohor`
85			`// Typo fixed.`
86			`//`
87	85	mohor	`// Revision 1.15 2003/06/11 09:37:05 mohor`
88			`// overrun and length_info fifos are initialized at the end of reset.`
89			`//`
90	73	mohor	`// Revision 1.14 2003/03/05 15:02:30 mohor`
91			`// Xilinx RAM added.`
92			`//`
93	51	mohor	`// Revision 1.13 2003/03/01 22:53:33 mohor`
94			`// Actel APA ram supported.`
95			`//`
96	48	mohor	`// Revision 1.12 2003/02/19 14:44:03 mohor`
97			`// CAN core finished. Host interface added. Registers finished.`
98			`// Synchronization to the wishbone finished.`
99			`//`
100	39	mohor	`// Revision 1.11 2003/02/14 20:17:01 mohor`
101			`// Several registers added. Not finished, yet.`
102			`//`
103	35	mohor	`// Revision 1.10 2003/02/11 00:56:06 mohor`
104			`// Wishbone interface added.`
105			`//`
106	31	mohor	`// Revision 1.9 2003/02/09 02:24:33 mohor`
107			`// Bosch license warning added. Error counters finished. Overload frames`
108			`// still need to be fixed.`
109			`//`
110	28	mohor	`// Revision 1.8 2003/01/31 01:13:38 mohor`
111			`// backup.`
112			`//`
113	24	mohor	`// Revision 1.7 2003/01/17 17:44:31 mohor`
114			`// Fifo corrected to be synthesizable.`
115			`//`
116	23	mohor	`// Revision 1.6 2003/01/15 13:16:47 mohor`
117	31	mohor	`// When a frame with "remote request" is received, no data is stored`
118			`// to fifo, just the frame information (identifier, ...). Data length`
119			`// that is stored is the received data length and not the actual data`
120			`// length that is stored to fifo.`
121	23	mohor	`//`
122	18	mohor	`// Revision 1.5 2003/01/14 17:25:09 mohor`
123			`// Addresses corrected to decimal values (previously hex).`
124			`//`
125	17	mohor	`// Revision 1.4 2003/01/14 12:19:35 mohor`
126			`// rx_fifo is now working.`
127			`//`
128	16	mohor	`// Revision 1.3 2003/01/09 21:54:45 mohor`
129			`// rx fifo added. Not 100 % verified, yet.`
130			`//`
131	14	mohor	`// Revision 1.2 2003/01/09 14:46:58 mohor`
132			`// Temporary files (backup).`
133			`//`
134	13	mohor	`// Revision 1.1 2003/01/08 02:10:55 mohor`
135			`// Acceptance filter added.`
136	11	mohor	`//`
137			`//`
138			`//`
139	13	mohor	`//`
140	11	mohor
141			`// synopsys translate_off`
142			`include "timescale.v"
143			`// synopsys translate_on`
144			`include "can_defines.v"
145
146			`module can_fifo`
147			`(`
148			`clk,`
149			`rst,`
150
151			`wr,`
152
153			`data_in,`
154	14	mohor	`addr,`
155	11	mohor	`data_out,`
156	48	mohor	`fifo_selected,`
157	11	mohor
158			`reset_mode,`
159	14	mohor	`release_buffer,`
160	35	mohor	`extended_mode,`
161			`overrun,`
162	39	mohor	`info_empty,`
163			`info_cnt`
164	13	mohor
165	95	simons	`ifdef CAN_BIST
166			`,`
167	130	markom	`mbist_si_i,`
168			`mbist_so_o,`
169			`mbist_ctrl_i`
170	95	simons	`endif
171	11	mohor	`);`
172
173			`parameter Tp = 1;`
174
175			`input clk;`
176			`input rst;`
177			`input wr;`
178			`input [7:0] data_in;`
179	109	mohor	`input [5:0] addr;`
180	11	mohor	`input reset_mode;`
181			`input release_buffer;`
182	14	mohor	`input extended_mode;`
183	48	mohor	`input fifo_selected;`
184	11	mohor
185	13	mohor	`output [7:0] data_out;`
186	35	mohor	`output overrun;`
187			`output info_empty;`
188	39	mohor	`output [6:0] info_cnt;`
189	11	mohor
190	95	simons	`ifdef CAN_BIST
191	130	markom	`input mbist_si_i;`
192			`output mbist_so_o;`
193			input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
194			`wire mbist_s_0;`
195	95	simons	`endif
196
197	124	mohor	`ifdef ALTERA_RAM
198			`else
199	48	mohor	`ifdef ACTEL_APA_RAM
200			`else
201	51	mohor	`ifdef XILINX_RAM
202			`else
203	115	simons	`ifdef ARTISAN_RAM
204			`reg overrun_info[0:63];`
205			`else
206	95	simons	`ifdef VIRTUALSILICON_RAM
207	97	simons	`reg overrun_info[0:63];`
208	95	simons	`else
209	48	mohor	`reg [7:0] fifo [0:63];`
210			`reg [3:0] length_fifo[0:63];`
211			`reg overrun_info[0:63];`
212			`endif
213	51	mohor	`endif
214	95	simons	`endif
215	115	simons	`endif
216	124	mohor	`endif
217	11	mohor
218			`reg [5:0] rd_pointer;`
219			`reg [5:0] wr_pointer;`
220	14	mohor	`reg [5:0] read_address;`
221	16	mohor	`reg [5:0] wr_info_pointer;`
222			`reg [5:0] rd_info_pointer;`
223	13	mohor	`reg wr_q;`
224			`reg [3:0] len_cnt;`
225	16	mohor	`reg [6:0] fifo_cnt;`
226	24	mohor	`reg [6:0] info_cnt;`
227	16	mohor	`reg latch_overrun;`
228	73	mohor	`reg initialize_memories;`
229	11	mohor
230	48	mohor	`wire [3:0] length_info;`
231	13	mohor	`wire write_length_info;`
232	16	mohor	`wire fifo_empty;`
233			`wire fifo_full;`
234	24	mohor	`wire info_full;`
235	11	mohor
236	13	mohor	`assign write_length_info = (~wr) & wr_q;`
237
238			`// Delayed write signal`
239			`always @ (posedge clk or posedge rst)`
240			`begin`
241			`if (rst)`
242	109	mohor	`wr_q <=#Tp 1'b0;`
243	13	mohor	`else if (reset_mode)`
244	109	mohor	`wr_q <=#Tp 1'b0;`
245	13	mohor	`else`
246			`wr_q <=#Tp wr;`
247			`end`
248
249
250			`// length counter`
251			`always @ (posedge clk or posedge rst)`
252			`begin`
253			`if (rst)`
254	109	mohor	`len_cnt <= 4'h0;`
255	13	mohor	`else if (reset_mode \| write_length_info)`
256	109	mohor	`len_cnt <=#Tp 4'h0;`
257	16	mohor	`else if (wr & (~fifo_full))`
258	13	mohor	`len_cnt <=#Tp len_cnt + 1'b1;`
259			`end`
260
261
262			`// wr_info_pointer`
263			`always @ (posedge clk or posedge rst)`
264			`begin`
265			`if (rst)`
266	109	mohor	`wr_info_pointer <= 6'h0;`
267	73	mohor	`else if (write_length_info & (~info_full) \| initialize_memories)`
268			`wr_info_pointer <=#Tp wr_info_pointer + 1'b1;`
269	13	mohor	`else if (reset_mode)`
270	152	igorm	`wr_info_pointer <=#Tp rd_info_pointer;`
271	13	mohor	`end`
272
273
274
275			`// rd_info_pointer`
276	11	mohor	`always @ (posedge clk or posedge rst)`
277			`begin`
278			`if (rst)`
279	109	mohor	`rd_info_pointer <= 6'h0;`
280	16	mohor	`else if (release_buffer & (~fifo_empty))`
281	13	mohor	`rd_info_pointer <=#Tp rd_info_pointer + 1'b1;`
282	11	mohor	`end`
283
284
285			`// rd_pointer`
286			`always @ (posedge clk or posedge rst)`
287			`begin`
288			`if (rst)`
289	109	mohor	`rd_pointer <= 5'h0;`
290	16	mohor	`else if (release_buffer & (~fifo_empty))`
291	109	mohor	`rd_pointer <=#Tp rd_pointer + {2'h0, length_info};`
292	11	mohor	`end`
293
294
295			`// wr_pointer`
296			`always @ (posedge clk or posedge rst)`
297			`begin`
298			`if (rst)`
299	109	mohor	`wr_pointer <= 5'h0;`
300	152	igorm	`else if (reset_mode)`
301			`wr_pointer <=#Tp rd_pointer;`
302	16	mohor	`else if (wr & (~fifo_full))`
303	13	mohor	`wr_pointer <=#Tp wr_pointer + 1'b1;`
304	11	mohor	`end`
305
306
307	16	mohor	`// latch_overrun`
308			`always @ (posedge clk or posedge rst)`
309			`begin`
310			`if (rst)`
311	109	mohor	`latch_overrun <= 1'b0;`
312	16	mohor	`else if (reset_mode \| write_length_info)`
313	109	mohor	`latch_overrun <=#Tp 1'b0;`
314	16	mohor	`else if (wr & fifo_full)`
315			`latch_overrun <=#Tp 1'b1;`
316			`end`
317
318
319			`// Counting data in fifo`
320			`always @ (posedge clk or posedge rst)`
321			`begin`
322			`if (rst)`
323	109	mohor	`fifo_cnt <= 7'h0;`
324	152	igorm	`else if (reset_mode)`
325			`fifo_cnt <=#Tp 7'h0;`
326	16	mohor	`else if (wr & (~release_buffer) & (~fifo_full))`
327			`fifo_cnt <=#Tp fifo_cnt + 1'b1;`
328			`else if ((~wr) & release_buffer & (~fifo_empty))`
329	109	mohor	`fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};`
330	16	mohor	`else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))`
331	109	mohor	`fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;`
332	16	mohor	`end`
333
334	109	mohor	`assign fifo_full = fifo_cnt == 7'd64;`
335			`assign fifo_empty = fifo_cnt == 7'd0;`
336	16	mohor
337
338	48	mohor	`// Counting data in length_fifo and overrun_info fifo`
339	24	mohor	`always @ (posedge clk or posedge rst)`
340			`begin`
341			`if (rst)`
342	109	mohor	`info_cnt <=#Tp 7'h0;`
343			`else if (reset_mode)`
344			`info_cnt <=#Tp 7'h0;`
345	24	mohor	`else if (write_length_info ^ release_buffer)`
346			`begin`
347			`if (release_buffer & (~info_empty))`
348			`info_cnt <=#Tp info_cnt - 1'b1;`
349			`else if (write_length_info & (~info_full))`
350			`info_cnt <=#Tp info_cnt + 1'b1;`
351			`end`
352			`end`
353
354	109	mohor	`assign info_full = info_cnt == 7'd64;`
355			`assign info_empty = info_cnt == 7'd0;`
356	16	mohor
357	24	mohor
358	14	mohor	`// Selecting which address will be used for reading data from rx fifo`
359			`always @ (extended_mode or rd_pointer or addr)`
360			`begin`
361			`if (extended_mode) // extended mode`
362	109	mohor	`read_address = rd_pointer + (addr - 6'd16);`
363	14	mohor	`else // normal mode`
364	109	mohor	`read_address = rd_pointer + (addr - 6'd20);`
365	14	mohor	`end`
366	11	mohor
367
368	73	mohor	`always @ (posedge clk or posedge rst)`
369			`begin`
370			`if (rst)`
371	109	mohor	`initialize_memories <= 1'b1;`
372	73	mohor	`else if (&wr_info_pointer)`
373			`initialize_memories <=#Tp 1'b0;`
374			`end`
375	14	mohor
376	73	mohor
377	124	mohor	`ifdef ALTERA_RAM
378			`// altera_ram_64x8_sync fifo`
379			`lpm_ram_dp fifo`
380			`(`
381			`.q (data_out),`
382			`.rdclock (clk),`
383			`.wrclock (clk),`
384			`.data (data_in),`
385	134	mohor	`.wren (wr & (~fifo_full)),`
386			`.rden (fifo_selected),`
387	124	mohor	`.wraddress (wr_pointer),`
388			`.rdaddress (read_address)`
389			`);`
390			`defparam fifo.lpm_width = 8;`
391			`defparam fifo.lpm_widthad = 6;`
392	134	mohor	`defparam fifo.lpm_numwords = 64;`
393	124	mohor
394
395			`// altera_ram_64x4_sync info_fifo`
396			`lpm_ram_dp info_fifo`
397			`(`
398			`.q (length_info),`
399			`.rdclock (clk),`
400			`.wrclock (clk),`
401			`.data (len_cnt & {4{~initialize_memories}}),`
402	134	mohor	`.wren (write_length_info & (~info_full) \| initialize_memories),`
403	124	mohor	`.wraddress (wr_info_pointer),`
404			`.rdaddress (rd_info_pointer)`
405			`);`
406			`defparam info_fifo.lpm_width = 4;`
407			`defparam info_fifo.lpm_widthad = 6;`
408	134	mohor	`defparam info_fifo.lpm_numwords = 64;`
409	124	mohor
410
411			`// altera_ram_64x1_sync overrun_fifo`
412			`lpm_ram_dp overrun_fifo`
413			`(`
414			`.q (overrun),`
415			`.rdclock (clk),`
416			`.wrclock (clk),`
417			`.data ((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
418	134	mohor	`.wren (write_length_info & (~info_full) \| initialize_memories),`
419	124	mohor	`.wraddress (wr_info_pointer),`
420			`.rdaddress (rd_info_pointer)`
421			`);`
422			`defparam overrun_fifo.lpm_width = 1;`
423			`defparam overrun_fifo.lpm_widthad = 6;`
424	134	mohor	`defparam overrun_fifo.lpm_numwords = 64;`
425	124	mohor
426			`else
427	48	mohor	`ifdef ACTEL_APA_RAM
428			`actel_ram_64x8_sync fifo`
429			`(`
430			`.DO (data_out),`
431			`.RCLOCK (clk),`
432			`.WCLOCK (clk),`
433			`.DI (data_in),`
434			`.PO (), // parity not used`
435			`.WRB (~(wr & (~fifo_full))),`
436			`.RDB (~fifo_selected),`
437			`.WADDR (wr_pointer),`
438			`.RADDR (read_address)`
439			`);`
440	14	mohor
441
442	48	mohor	`actel_ram_64x4_sync info_fifo`
443			`(`
444			`.DO (length_info),`
445			`.RCLOCK (clk),`
446			`.WCLOCK (clk),`
447	73	mohor	`.DI (len_cnt & {4{~initialize_memories}}),`
448	48	mohor	`.PO (), // parity not used`
449	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
450	48	mohor	`.RDB (1'b0), // always enabled`
451			`.WADDR (wr_info_pointer),`
452			`.RADDR (rd_info_pointer)`
453			`);`
454	14	mohor
455
456	48	mohor	`actel_ram_64x1_sync overrun_fifo`
457			`(`
458			`.DO (overrun),`
459			`.RCLOCK (clk),`
460			`.WCLOCK (clk),`
461	73	mohor	`.DI ((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
462	48	mohor	`.PO (), // parity not used`
463	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
464	48	mohor	`.RDB (1'b0), // always enabled`
465			`.WADDR (wr_info_pointer),`
466			`.RADDR (rd_info_pointer)`
467			`);`
468			`else
469	51	mohor	`ifdef XILINX_RAM
470
471			`RAMB4_S8_S8 fifo`
472			`(`
473			`.DOA(),`
474			`.DOB(data_out),`
475			`.ADDRA({3'h0, wr_pointer}),`
476			`.CLKA(clk),`
477			`.DIA(data_in),`
478			`.ENA(1'b1),`
479			`.RSTA(1'b0),`
480			`.WEA(wr & (~fifo_full)),`
481			`.ADDRB({3'h0, read_address}),`
482			`.CLKB(clk),`
483			`.DIB(8'h0),`
484			`.ENB(1'b1),`
485			`.RSTB(1'b0),`
486			`.WEB(1'b0)`
487			`);`
488
489
490			`RAMB4_S4_S4 info_fifo`
491			`(`
492			`.DOA(),`
493			`.DOB(length_info),`
494			`.ADDRA({4'h0, wr_info_pointer}),`
495			`.CLKA(clk),`
496	73	mohor	`.DIA(len_cnt & {4{~initialize_memories}}),`
497	51	mohor	`.ENA(1'b1),`
498			`.RSTA(1'b0),`
499	73	mohor	`.WEA(write_length_info & (~info_full) \| initialize_memories),`
500	51	mohor	`.ADDRB({4'h0, rd_info_pointer}),`

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