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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_fifo.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.10  2003/02/11 00:56:06  mohor
// Wishbone interface added.
//
// Revision 1.9  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.8  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.7  2003/01/17 17:44:31  mohor
// Fifo corrected to be synthesizable.
//
// Revision 1.6  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored
// to fifo, just the frame information (identifier, ...). Data length
// that is stored is the received data length and not the actual data
// length that is stored to fifo.
//
// Revision 1.5  2003/01/14 17:25:09  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.4  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.3  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.2  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.1  2003/01/08 02:10:55  mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_fifo
(
  clk,
  rst,
 
  wr,
 
  data_in,
  addr,
  data_out,
 
  reset_mode,
  release_buffer,
  extended_mode,
  overrun,
  info_empty,
  info_cnt
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         wr;
input   [7:0] data_in;
input   [7:0] addr;
input         reset_mode;
input         release_buffer;
input         extended_mode;
 
output  [7:0] data_out;
output        overrun;
output        info_empty;
output  [6:0] info_cnt;
 
 
reg     [7:0] fifo [0:63];
reg     [5:0] rd_pointer;
reg     [5:0] wr_pointer;
reg     [5:0] read_address;
reg     [3:0] length_info[0:63];
reg     [5:0] wr_info_pointer;
reg     [5:0] rd_info_pointer;
reg           overrun_info[0:63];
reg           wr_q;
reg     [3:0] len_cnt;
reg     [6:0] fifo_cnt;
reg     [6:0] info_cnt;
reg           latch_overrun;
 
wire          write_length_info;
wire          fifo_empty;
wire          fifo_full;
wire          info_full;
 
assign write_length_info = (~wr) & wr_q;
 
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_q <= 0;
  else if (reset_mode)
    wr_q <=#Tp 0;
  else
    wr_q <=#Tp wr;
end
 
 
// length counter
always @ (posedge clk or posedge rst)
begin
  if (rst)
    len_cnt <= 0;
  else if (reset_mode | write_length_info)
    len_cnt <=#Tp 1'b0;
  else if (wr & (~fifo_full))
    len_cnt <=#Tp len_cnt + 1'b1;
end
 
 
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_info_pointer <= 0;
  else if (reset_mode)
    wr_info_pointer <=#Tp 0;
  else if (write_length_info & (~info_full))
    wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
end
 
 
// length_info
always @ (posedge clk)
begin
  if (write_length_info & (~info_full))
    length_info[wr_info_pointer] <=#Tp len_cnt;
end
 
 
// overrun_info
always @ (posedge clk)
begin
  if (write_length_info & (~info_full))
    overrun_info[wr_info_pointer] <=#Tp latch_overrun | (wr & fifo_full);
end
 
 
// reading overrun
assign overrun = overrun_info[rd_info_pointer];
 
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_info_pointer <= 0;
  else if (reset_mode)
    rd_info_pointer <=#Tp 0;
  else if (release_buffer & (~fifo_empty))
    rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
 
 
// rd_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_pointer <= 0;
  else if (release_buffer & (~fifo_empty))
    rd_pointer <=#Tp rd_pointer + length_info[rd_info_pointer];
  else if (reset_mode)
    rd_pointer <=#Tp 0;
end
 
 
// wr_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_pointer <= 0;
  else if (wr & (~fifo_full))
    wr_pointer <=#Tp wr_pointer + 1'b1;
  else if (reset_mode)
    wr_pointer <=#Tp 0;
end
 
 
// latch_overrun
always @ (posedge clk or posedge rst)
begin
  if (rst)
    latch_overrun <= 0;
  else if (reset_mode | write_length_info)
    latch_overrun <=#Tp 0;
  else if (wr & fifo_full)
    latch_overrun <=#Tp 1'b1;
end
 
 
// Counting data in fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    fifo_cnt <= 0;
  else if (wr & (~release_buffer) & (~fifo_full))
    fifo_cnt <=#Tp fifo_cnt + 1'b1;
  else if ((~wr) & release_buffer & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer];
  else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer] + 1'b1;
  else if (reset_mode)
    fifo_cnt <=#Tp 0;
end
 
assign fifo_full = fifo_cnt == 64;
assign fifo_empty = fifo_cnt == 0;
 
 
// Counting data in length_info and overrun_info fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    info_cnt <= 0;
  else if (write_length_info ^ release_buffer)
    begin
      if (release_buffer & (~info_empty))
        info_cnt <=#Tp info_cnt - 1'b1;
      else if (write_length_info & (~info_full))
        info_cnt <=#Tp info_cnt + 1'b1;
    end
end
 
assign info_full = info_cnt == 64;
assign info_empty = info_cnt == 0;
 
 
// writing data to fifo
always @ (posedge clk)
begin
  if (wr & (~fifo_full))
    fifo[wr_pointer] <=#Tp data_in;
end
 
 
 
// Selecting which address will be used for reading data from rx fifo
always @ (extended_mode or rd_pointer or addr)
begin
  if (extended_mode)      // extended mode
    begin
      read_address <= rd_pointer + (addr - 8'd16);
    end
  else                    // normal mode
    begin
      read_address <= rd_pointer + (addr - 8'd20);
    end
end
 
 
 
assign data_out = fifo[read_address];
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	11	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_fifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002, 2003 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	11	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	39	mohor	`// Revision 1.11 2003/02/14 20:17:01 mohor`
54			`// Several registers added. Not finished, yet.`
55			`//`
56	35	mohor	`// Revision 1.10 2003/02/11 00:56:06 mohor`
57			`// Wishbone interface added.`
58			`//`
59	31	mohor	`// Revision 1.9 2003/02/09 02:24:33 mohor`
60			`// Bosch license warning added. Error counters finished. Overload frames`
61			`// still need to be fixed.`
62			`//`
63	28	mohor	`// Revision 1.8 2003/01/31 01:13:38 mohor`
64			`// backup.`
65			`//`
66	24	mohor	`// Revision 1.7 2003/01/17 17:44:31 mohor`
67			`// Fifo corrected to be synthesizable.`
68			`//`
69	23	mohor	`// Revision 1.6 2003/01/15 13:16:47 mohor`
70	31	mohor	`// When a frame with "remote request" is received, no data is stored`
71			`// to fifo, just the frame information (identifier, ...). Data length`
72			`// that is stored is the received data length and not the actual data`
73			`// length that is stored to fifo.`
74	23	mohor	`//`
75	18	mohor	`// Revision 1.5 2003/01/14 17:25:09 mohor`
76			`// Addresses corrected to decimal values (previously hex).`
77			`//`
78	17	mohor	`// Revision 1.4 2003/01/14 12:19:35 mohor`
79			`// rx_fifo is now working.`
80			`//`
81	16	mohor	`// Revision 1.3 2003/01/09 21:54:45 mohor`
82			`// rx fifo added. Not 100 % verified, yet.`
83			`//`
84	14	mohor	`// Revision 1.2 2003/01/09 14:46:58 mohor`
85			`// Temporary files (backup).`
86			`//`
87	13	mohor	`// Revision 1.1 2003/01/08 02:10:55 mohor`
88			`// Acceptance filter added.`
89	11	mohor	`//`
90			`//`
91			`//`
92	13	mohor	`//`
93	11	mohor
94			`// synopsys translate_off`
95			`include "timescale.v"
96			`// synopsys translate_on`
97			`include "can_defines.v"
98
99			`module can_fifo`
100			`(`
101			`clk,`
102			`rst,`
103
104			`wr,`
105
106			`data_in,`
107	14	mohor	`addr,`
108	11	mohor	`data_out,`
109
110			`reset_mode,`
111	14	mohor	`release_buffer,`
112	35	mohor	`extended_mode,`
113			`overrun,`
114	39	mohor	`info_empty,`
115			`info_cnt`
116	13	mohor
117	11	mohor	`);`
118
119			`parameter Tp = 1;`
120
121			`input clk;`
122			`input rst;`
123			`input wr;`
124			`input [7:0] data_in;`
125	14	mohor	`input [7:0] addr;`
126	11	mohor	`input reset_mode;`
127			`input release_buffer;`
128	14	mohor	`input extended_mode;`
129	11	mohor
130	13	mohor	`output [7:0] data_out;`
131	35	mohor	`output overrun;`
132			`output info_empty;`
133	39	mohor	`output [6:0] info_cnt;`
134	11	mohor
135
136			`reg [7:0] fifo [0:63];`
137			`reg [5:0] rd_pointer;`
138			`reg [5:0] wr_pointer;`
139	14	mohor	`reg [5:0] read_address;`
140	16	mohor	`reg [3:0] length_info[0:63];`
141			`reg [5:0] wr_info_pointer;`
142			`reg [5:0] rd_info_pointer;`
143			`reg overrun_info[0:63];`
144	13	mohor	`reg wr_q;`
145			`reg [3:0] len_cnt;`
146	16	mohor	`reg [6:0] fifo_cnt;`
147	24	mohor	`reg [6:0] info_cnt;`
148	16	mohor	`reg latch_overrun;`
149	11	mohor
150	13	mohor	`wire write_length_info;`
151	16	mohor	`wire fifo_empty;`
152			`wire fifo_full;`
153	24	mohor	`wire info_full;`
154	11	mohor
155	13	mohor	`assign write_length_info = (~wr) & wr_q;`
156
157			`// Delayed write signal`
158			`always @ (posedge clk or posedge rst)`
159			`begin`
160			`if (rst)`
161			`wr_q <= 0;`
162			`else if (reset_mode)`
163			`wr_q <=#Tp 0;`
164			`else`
165			`wr_q <=#Tp wr;`
166			`end`
167
168
169			`// length counter`
170			`always @ (posedge clk or posedge rst)`
171			`begin`
172			`if (rst)`
173			`len_cnt <= 0;`
174			`else if (reset_mode \| write_length_info)`
175			`len_cnt <=#Tp 1'b0;`
176	16	mohor	`else if (wr & (~fifo_full))`
177	13	mohor	`len_cnt <=#Tp len_cnt + 1'b1;`
178			`end`
179
180
181			`// wr_info_pointer`
182			`always @ (posedge clk or posedge rst)`
183			`begin`
184			`if (rst)`
185			`wr_info_pointer <= 0;`
186			`else if (reset_mode)`
187			`wr_info_pointer <=#Tp 0;`
188	24	mohor	`else if (write_length_info & (~info_full))`
189	13	mohor	`wr_info_pointer <=#Tp wr_info_pointer + 1'b1;`
190			`end`
191
192
193	11	mohor	`// length_info`
194	13	mohor	`always @ (posedge clk)`
195			`begin`
196	24	mohor	`if (write_length_info & (~info_full))`
197	13	mohor	`length_info[wr_info_pointer] <=#Tp len_cnt;`
198			`end`
199
200
201	16	mohor	`// overrun_info`
202			`always @ (posedge clk)`
203			`begin`
204	24	mohor	`if (write_length_info & (~info_full))`
205	16	mohor	`overrun_info[wr_info_pointer] <=#Tp latch_overrun \| (wr & fifo_full);`
206			`end`
207
208
209	35	mohor	`// reading overrun`
210			`assign overrun = overrun_info[rd_info_pointer];`
211	16	mohor
212	13	mohor	`// rd_info_pointer`
213	11	mohor	`always @ (posedge clk or posedge rst)`
214			`begin`
215			`if (rst)`
216	13	mohor	`rd_info_pointer <= 0;`
217	11	mohor	`else if (reset_mode)`
218	13	mohor	`rd_info_pointer <=#Tp 0;`
219	16	mohor	`else if (release_buffer & (~fifo_empty))`
220	13	mohor	`rd_info_pointer <=#Tp rd_info_pointer + 1'b1;`
221	11	mohor	`end`
222
223
224			`// rd_pointer`
225			`always @ (posedge clk or posedge rst)`
226			`begin`
227			`if (rst)`
228			`rd_pointer <= 0;`
229	16	mohor	`else if (release_buffer & (~fifo_empty))`
230	13	mohor	`rd_pointer <=#Tp rd_pointer + length_info[rd_info_pointer];`
231	11	mohor	`else if (reset_mode)`
232			`rd_pointer <=#Tp 0;`
233			`end`
234
235
236			`// wr_pointer`
237			`always @ (posedge clk or posedge rst)`
238			`begin`
239			`if (rst)`
240			`wr_pointer <= 0;`
241	16	mohor	`else if (wr & (~fifo_full))`
242	13	mohor	`wr_pointer <=#Tp wr_pointer + 1'b1;`
243	11	mohor	`else if (reset_mode)`
244			`wr_pointer <=#Tp 0;`
245			`end`
246
247
248	16	mohor	`// latch_overrun`
249			`always @ (posedge clk or posedge rst)`
250			`begin`
251			`if (rst)`
252			`latch_overrun <= 0;`
253			`else if (reset_mode \| write_length_info)`
254			`latch_overrun <=#Tp 0;`
255			`else if (wr & fifo_full)`
256			`latch_overrun <=#Tp 1'b1;`
257			`end`
258
259
260			`// Counting data in fifo`
261			`always @ (posedge clk or posedge rst)`
262			`begin`
263			`if (rst)`
264			`fifo_cnt <= 0;`
265			`else if (wr & (~release_buffer) & (~fifo_full))`
266			`fifo_cnt <=#Tp fifo_cnt + 1'b1;`
267			`else if ((~wr) & release_buffer & (~fifo_empty))`
268			`fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer];`
269			`else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))`
270			`fifo_cnt <=#Tp fifo_cnt - length_info[rd_info_pointer] + 1'b1;`
271			`else if (reset_mode)`
272			`fifo_cnt <=#Tp 0;`
273			`end`
274
275			`assign fifo_full = fifo_cnt == 64;`
276			`assign fifo_empty = fifo_cnt == 0;`
277
278
279	24	mohor	`// Counting data in length_info and overrun_info fifo`
280			`always @ (posedge clk or posedge rst)`
281			`begin`
282			`if (rst)`
283			`info_cnt <= 0;`
284			`else if (write_length_info ^ release_buffer)`
285			`begin`
286			`if (release_buffer & (~info_empty))`
287			`info_cnt <=#Tp info_cnt - 1'b1;`
288			`else if (write_length_info & (~info_full))`
289			`info_cnt <=#Tp info_cnt + 1'b1;`
290			`end`
291			`end`
292
293			`assign info_full = info_cnt == 64;`
294			`assign info_empty = info_cnt == 0;`
295	16	mohor
296	24	mohor
297	11	mohor	`// writing data to fifo`
298	23	mohor	`always @ (posedge clk)`
299	11	mohor	`begin`
300	16	mohor	`if (wr & (~fifo_full))`
301	11	mohor	`fifo[wr_pointer] <=#Tp data_in;`
302			`end`
303
304
305
306	14	mohor	`// Selecting which address will be used for reading data from rx fifo`
307			`always @ (extended_mode or rd_pointer or addr)`
308			`begin`
309			`if (extended_mode) // extended mode`
310			`begin`
311	17	mohor	`read_address <= rd_pointer + (addr - 8'd16);`
312	14	mohor	`end`
313			`else // normal mode`
314			`begin`
315	17	mohor	`read_address <= rd_pointer + (addr - 8'd20);`
316	14	mohor	`end`
317			`end`
318	11	mohor
319
320	14	mohor
321			`assign data_out = fifo[read_address];`
322
323
324
325
326	11	mohor	`endmodule`

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[/] [can/] [trunk/] [rtl/] [verilog/] [can_fifo.v] - Blame information for rev 39