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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_fifo.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12  2003/02/19 14:44:03  mohor
// CAN core finished. Host interface added. Registers finished.
// Synchronization to the wishbone finished.
//
// Revision 1.11  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.10  2003/02/11 00:56:06  mohor
// Wishbone interface added.
//
// Revision 1.9  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.8  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.7  2003/01/17 17:44:31  mohor
// Fifo corrected to be synthesizable.
//
// Revision 1.6  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored
// to fifo, just the frame information (identifier, ...). Data length
// that is stored is the received data length and not the actual data
// length that is stored to fifo.
//
// Revision 1.5  2003/01/14 17:25:09  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.4  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.3  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.2  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.1  2003/01/08 02:10:55  mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_fifo
(
  clk,
  rst,
 
  wr,
 
  data_in,
  addr,
  data_out,
  fifo_selected,
 
  reset_mode,
  release_buffer,
  extended_mode,
  overrun,
  info_empty,
  info_cnt
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         wr;
input   [7:0] data_in;
input   [7:0] addr;
input         reset_mode;
input         release_buffer;
input         extended_mode;
input         fifo_selected;
 
output  [7:0] data_out;
output        overrun;
output        info_empty;
output  [6:0] info_cnt;
 
`ifdef ACTEL_APA_RAM
`else
  reg     [7:0] fifo [0:63];
  reg     [3:0] length_fifo[0:63];
  reg           overrun_info[0:63];
`endif
 
reg     [5:0] rd_pointer;
reg     [5:0] wr_pointer;
reg     [5:0] read_address;
reg     [5:0] wr_info_pointer;
reg     [5:0] rd_info_pointer;
reg           wr_q;
reg     [3:0] len_cnt;
reg     [6:0] fifo_cnt;
reg     [6:0] info_cnt;
reg           latch_overrun;
 
wire    [3:0] length_info;
wire          write_length_info;
wire          fifo_empty;
wire          fifo_full;
wire          info_full;
 
assign write_length_info = (~wr) & wr_q;
 
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_q <= 0;
  else if (reset_mode)
    wr_q <=#Tp 0;
  else
    wr_q <=#Tp wr;
end
 
 
// length counter
always @ (posedge clk or posedge rst)
begin
  if (rst)
    len_cnt <= 0;
  else if (reset_mode | write_length_info)
    len_cnt <=#Tp 1'b0;
  else if (wr & (~fifo_full))
    len_cnt <=#Tp len_cnt + 1'b1;
end
 
 
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_info_pointer <= 0;
  else if (reset_mode)
    wr_info_pointer <=#Tp 0;
  else if (write_length_info & (~info_full))
    wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
end
 
 
 
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_info_pointer <= 0;
  else if (reset_mode)
    rd_info_pointer <=#Tp 0;
  else if (release_buffer & (~fifo_empty))
    rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
 
 
// rd_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_pointer <= 0;
  else if (release_buffer & (~fifo_empty))
    rd_pointer <=#Tp rd_pointer + length_info;
  else if (reset_mode)
    rd_pointer <=#Tp 0;
end
 
 
// wr_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_pointer <= 0;
  else if (wr & (~fifo_full))
    wr_pointer <=#Tp wr_pointer + 1'b1;
  else if (reset_mode)
    wr_pointer <=#Tp 0;
end
 
 
// latch_overrun
always @ (posedge clk or posedge rst)
begin
  if (rst)
    latch_overrun <= 0;
  else if (reset_mode | write_length_info)
    latch_overrun <=#Tp 0;
  else if (wr & fifo_full)
    latch_overrun <=#Tp 1'b1;
end
 
 
// Counting data in fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    fifo_cnt <= 0;
  else if (wr & (~release_buffer) & (~fifo_full))
    fifo_cnt <=#Tp fifo_cnt + 1'b1;
  else if ((~wr) & release_buffer & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - length_info;
  else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - length_info + 1'b1;
  else if (reset_mode)
    fifo_cnt <=#Tp 0;
end
 
assign fifo_full = fifo_cnt == 64;
assign fifo_empty = fifo_cnt == 0;
 
 
// Counting data in length_fifo and overrun_info fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    info_cnt <= 0;
  else if (write_length_info ^ release_buffer)
    begin
      if (release_buffer & (~info_empty))
        info_cnt <=#Tp info_cnt - 1'b1;
      else if (write_length_info & (~info_full))
        info_cnt <=#Tp info_cnt + 1'b1;
    end
end
 
assign info_full = info_cnt == 64;
assign info_empty = info_cnt == 0;
 
 
// Selecting which address will be used for reading data from rx fifo
always @ (extended_mode or rd_pointer or addr)
begin
  if (extended_mode)      // extended mode
    begin
      read_address <= rd_pointer + (addr - 8'd16);
    end
  else                    // normal mode
    begin
      read_address <= rd_pointer + (addr - 8'd20);
    end
end
 
 
 
`ifdef ACTEL_APA_RAM
  actel_ram_64x8_sync fifo
  (
    .DO      (data_out),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (data_in),
    .PO      (),                       // parity not used
    .WRB     (~(wr & (~fifo_full))),
    .RDB     (~fifo_selected),
    .WADDR   (wr_pointer),
    .RADDR   (read_address)
  );
 
 
  actel_ram_64x4_sync info_fifo
  (
    .DO      (length_info),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (len_cnt),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full))),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
 
 
  actel_ram_64x1_sync overrun_fifo
  (
    .DO      (overrun),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (latch_overrun | (wr & fifo_full)),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full))),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
`else
  // writing data to fifo
  always @ (posedge clk)
  begin
    if (wr & (~fifo_full))
      fifo[wr_pointer] <=#Tp data_in;
  end
 
  // reading from fifo
  assign data_out = fifo[read_address];
 
 
  // writing length_fifo
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full))
      length_fifo[wr_info_pointer] <=#Tp len_cnt;
  end
 
  // reading length_fifo
  assign length_info = length_fifo[rd_info_pointer];
 
  // overrun_info
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full))
      overrun_info[wr_info_pointer] <=#Tp latch_overrun | (wr & fifo_full);
  end
 
 
  // reading overrun
  assign overrun = overrun_info[rd_info_pointer];
 
 
`endif
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	11	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_fifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002, 2003 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	11	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	48	mohor	`// Revision 1.12 2003/02/19 14:44:03 mohor`
54			`// CAN core finished. Host interface added. Registers finished.`
55			`// Synchronization to the wishbone finished.`
56			`//`
57	39	mohor	`// Revision 1.11 2003/02/14 20:17:01 mohor`
58			`// Several registers added. Not finished, yet.`
59			`//`
60	35	mohor	`// Revision 1.10 2003/02/11 00:56:06 mohor`
61			`// Wishbone interface added.`
62			`//`
63	31	mohor	`// Revision 1.9 2003/02/09 02:24:33 mohor`
64			`// Bosch license warning added. Error counters finished. Overload frames`
65			`// still need to be fixed.`
66			`//`
67	28	mohor	`// Revision 1.8 2003/01/31 01:13:38 mohor`
68			`// backup.`
69			`//`
70	24	mohor	`// Revision 1.7 2003/01/17 17:44:31 mohor`
71			`// Fifo corrected to be synthesizable.`
72			`//`
73	23	mohor	`// Revision 1.6 2003/01/15 13:16:47 mohor`
74	31	mohor	`// When a frame with "remote request" is received, no data is stored`
75			`// to fifo, just the frame information (identifier, ...). Data length`
76			`// that is stored is the received data length and not the actual data`
77			`// length that is stored to fifo.`
78	23	mohor	`//`
79	18	mohor	`// Revision 1.5 2003/01/14 17:25:09 mohor`
80			`// Addresses corrected to decimal values (previously hex).`
81			`//`
82	17	mohor	`// Revision 1.4 2003/01/14 12:19:35 mohor`
83			`// rx_fifo is now working.`
84			`//`
85	16	mohor	`// Revision 1.3 2003/01/09 21:54:45 mohor`
86			`// rx fifo added. Not 100 % verified, yet.`
87			`//`
88	14	mohor	`// Revision 1.2 2003/01/09 14:46:58 mohor`
89			`// Temporary files (backup).`
90			`//`
91	13	mohor	`// Revision 1.1 2003/01/08 02:10:55 mohor`
92			`// Acceptance filter added.`
93	11	mohor	`//`
94			`//`
95			`//`
96	13	mohor	`//`
97	11	mohor
98			`// synopsys translate_off`
99			`include "timescale.v"
100			`// synopsys translate_on`
101			`include "can_defines.v"
102
103			`module can_fifo`
104			`(`
105			`clk,`
106			`rst,`
107
108			`wr,`
109
110			`data_in,`
111	14	mohor	`addr,`
112	11	mohor	`data_out,`
113	48	mohor	`fifo_selected,`
114	11	mohor
115			`reset_mode,`
116	14	mohor	`release_buffer,`
117	35	mohor	`extended_mode,`
118			`overrun,`
119	39	mohor	`info_empty,`
120			`info_cnt`
121	13	mohor
122	11	mohor	`);`
123
124			`parameter Tp = 1;`
125
126			`input clk;`
127			`input rst;`
128			`input wr;`
129			`input [7:0] data_in;`
130	14	mohor	`input [7:0] addr;`
131	11	mohor	`input reset_mode;`
132			`input release_buffer;`
133	14	mohor	`input extended_mode;`
134	48	mohor	`input fifo_selected;`
135	11	mohor
136	13	mohor	`output [7:0] data_out;`
137	35	mohor	`output overrun;`
138			`output info_empty;`
139	39	mohor	`output [6:0] info_cnt;`
140	11	mohor
141	48	mohor	`ifdef ACTEL_APA_RAM
142			`else
143			`reg [7:0] fifo [0:63];`
144			`reg [3:0] length_fifo[0:63];`
145			`reg overrun_info[0:63];`
146			`endif
147	11	mohor
148			`reg [5:0] rd_pointer;`
149			`reg [5:0] wr_pointer;`
150	14	mohor	`reg [5:0] read_address;`
151	16	mohor	`reg [5:0] wr_info_pointer;`
152			`reg [5:0] rd_info_pointer;`
153	13	mohor	`reg wr_q;`
154			`reg [3:0] len_cnt;`
155	16	mohor	`reg [6:0] fifo_cnt;`
156	24	mohor	`reg [6:0] info_cnt;`
157	16	mohor	`reg latch_overrun;`
158	11	mohor
159	48	mohor	`wire [3:0] length_info;`
160	13	mohor	`wire write_length_info;`
161	16	mohor	`wire fifo_empty;`
162			`wire fifo_full;`
163	24	mohor	`wire info_full;`
164	11	mohor
165	13	mohor	`assign write_length_info = (~wr) & wr_q;`
166
167			`// Delayed write signal`
168			`always @ (posedge clk or posedge rst)`
169			`begin`
170			`if (rst)`
171			`wr_q <= 0;`
172			`else if (reset_mode)`
173			`wr_q <=#Tp 0;`
174			`else`
175			`wr_q <=#Tp wr;`
176			`end`
177
178
179			`// length counter`
180			`always @ (posedge clk or posedge rst)`
181			`begin`
182			`if (rst)`
183			`len_cnt <= 0;`
184			`else if (reset_mode \| write_length_info)`
185			`len_cnt <=#Tp 1'b0;`
186	16	mohor	`else if (wr & (~fifo_full))`
187	13	mohor	`len_cnt <=#Tp len_cnt + 1'b1;`
188			`end`
189
190
191			`// wr_info_pointer`
192			`always @ (posedge clk or posedge rst)`
193			`begin`
194			`if (rst)`
195			`wr_info_pointer <= 0;`
196			`else if (reset_mode)`
197			`wr_info_pointer <=#Tp 0;`
198	24	mohor	`else if (write_length_info & (~info_full))`
199	13	mohor	`wr_info_pointer <=#Tp wr_info_pointer + 1'b1;`
200			`end`
201
202
203
204			`// rd_info_pointer`
205	11	mohor	`always @ (posedge clk or posedge rst)`
206			`begin`
207			`if (rst)`
208	13	mohor	`rd_info_pointer <= 0;`
209	11	mohor	`else if (reset_mode)`
210	13	mohor	`rd_info_pointer <=#Tp 0;`
211	16	mohor	`else if (release_buffer & (~fifo_empty))`
212	13	mohor	`rd_info_pointer <=#Tp rd_info_pointer + 1'b1;`
213	11	mohor	`end`
214
215
216			`// rd_pointer`
217			`always @ (posedge clk or posedge rst)`
218			`begin`
219			`if (rst)`
220			`rd_pointer <= 0;`
221	16	mohor	`else if (release_buffer & (~fifo_empty))`
222	48	mohor	`rd_pointer <=#Tp rd_pointer + length_info;`
223	11	mohor	`else if (reset_mode)`
224			`rd_pointer <=#Tp 0;`
225			`end`
226
227
228			`// wr_pointer`
229			`always @ (posedge clk or posedge rst)`
230			`begin`
231			`if (rst)`
232			`wr_pointer <= 0;`
233	16	mohor	`else if (wr & (~fifo_full))`
234	13	mohor	`wr_pointer <=#Tp wr_pointer + 1'b1;`
235	11	mohor	`else if (reset_mode)`
236			`wr_pointer <=#Tp 0;`
237			`end`
238
239
240	16	mohor	`// latch_overrun`
241			`always @ (posedge clk or posedge rst)`
242			`begin`
243			`if (rst)`
244			`latch_overrun <= 0;`
245			`else if (reset_mode \| write_length_info)`
246			`latch_overrun <=#Tp 0;`
247			`else if (wr & fifo_full)`
248			`latch_overrun <=#Tp 1'b1;`
249			`end`
250
251
252			`// Counting data in fifo`
253			`always @ (posedge clk or posedge rst)`
254			`begin`
255			`if (rst)`
256			`fifo_cnt <= 0;`
257			`else if (wr & (~release_buffer) & (~fifo_full))`
258			`fifo_cnt <=#Tp fifo_cnt + 1'b1;`
259			`else if ((~wr) & release_buffer & (~fifo_empty))`
260	48	mohor	`fifo_cnt <=#Tp fifo_cnt - length_info;`
261	16	mohor	`else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))`
262	48	mohor	`fifo_cnt <=#Tp fifo_cnt - length_info + 1'b1;`
263	16	mohor	`else if (reset_mode)`
264			`fifo_cnt <=#Tp 0;`
265			`end`
266
267			`assign fifo_full = fifo_cnt == 64;`
268			`assign fifo_empty = fifo_cnt == 0;`
269
270
271	48	mohor	`// Counting data in length_fifo and overrun_info fifo`
272	24	mohor	`always @ (posedge clk or posedge rst)`
273			`begin`
274			`if (rst)`
275			`info_cnt <= 0;`
276			`else if (write_length_info ^ release_buffer)`
277			`begin`
278			`if (release_buffer & (~info_empty))`
279			`info_cnt <=#Tp info_cnt - 1'b1;`
280			`else if (write_length_info & (~info_full))`
281			`info_cnt <=#Tp info_cnt + 1'b1;`
282			`end`
283			`end`
284
285			`assign info_full = info_cnt == 64;`
286			`assign info_empty = info_cnt == 0;`
287	16	mohor
288	24	mohor
289	14	mohor	`// Selecting which address will be used for reading data from rx fifo`
290			`always @ (extended_mode or rd_pointer or addr)`
291			`begin`
292			`if (extended_mode) // extended mode`
293			`begin`
294	17	mohor	`read_address <= rd_pointer + (addr - 8'd16);`
295	14	mohor	`end`
296			`else // normal mode`
297			`begin`
298	17	mohor	`read_address <= rd_pointer + (addr - 8'd20);`
299	14	mohor	`end`
300			`end`
301	11	mohor
302
303	14	mohor
304	48	mohor	`ifdef ACTEL_APA_RAM
305			`actel_ram_64x8_sync fifo`
306			`(`
307			`.DO (data_out),`
308			`.RCLOCK (clk),`
309			`.WCLOCK (clk),`
310			`.DI (data_in),`
311			`.PO (), // parity not used`
312			`.WRB (~(wr & (~fifo_full))),`
313			`.RDB (~fifo_selected),`
314			`.WADDR (wr_pointer),`
315			`.RADDR (read_address)`
316			`);`
317	14	mohor
318
319	48	mohor	`actel_ram_64x4_sync info_fifo`
320			`(`
321			`.DO (length_info),`
322			`.RCLOCK (clk),`
323			`.WCLOCK (clk),`
324			`.DI (len_cnt),`
325			`.PO (), // parity not used`
326			`.WRB (~(write_length_info & (~info_full))),`
327			`.RDB (1'b0), // always enabled`
328			`.WADDR (wr_info_pointer),`
329			`.RADDR (rd_info_pointer)`
330			`);`
331	14	mohor
332
333	48	mohor	`actel_ram_64x1_sync overrun_fifo`
334			`(`
335			`.DO (overrun),`
336			`.RCLOCK (clk),`
337			`.WCLOCK (clk),`
338			`.DI (latch_overrun \| (wr & fifo_full)),`
339			`.PO (), // parity not used`
340			`.WRB (~(write_length_info & (~info_full))),`
341			`.RDB (1'b0), // always enabled`
342			`.WADDR (wr_info_pointer),`
343			`.RADDR (rd_info_pointer)`
344			`);`
345			`else
346			`// writing data to fifo`
347			`always @ (posedge clk)`
348			`begin`
349			`if (wr & (~fifo_full))`
350			`fifo[wr_pointer] <=#Tp data_in;`
351			`end`
352
353			`// reading from fifo`
354			`assign data_out = fifo[read_address];`
355
356
357			`// writing length_fifo`
358			`always @ (posedge clk)`
359			`begin`
360			`if (write_length_info & (~info_full))`
361			`length_fifo[wr_info_pointer] <=#Tp len_cnt;`
362			`end`
363
364			`// reading length_fifo`
365			`assign length_info = length_fifo[rd_info_pointer];`
366
367			`// overrun_info`
368			`always @ (posedge clk)`
369			`begin`
370			`if (write_length_info & (~info_full))`
371			`overrun_info[wr_info_pointer] <=#Tp latch_overrun \| (wr & fifo_full);`
372			`end`
373
374
375			`// reading overrun`
376			`assign overrun = overrun_info[rd_info_pointer];`
377
378
379			`endif
380
381
382
383
384
385	11	mohor	`endmodule`

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