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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  can_fifo.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the CAN Protocol Controller            ////
////  http://www.opencores.org/projects/can/                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002, 2003 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The CAN protocol is developed by Robert Bosch GmbH and       ////
//// protected by patents. Anybody who wants to implement this    ////
//// CAN IP core on silicon has to obtain a CAN protocol license  ////
//// from Bosch.                                                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2003/03/05 15:02:30  mohor
// Xilinx RAM added.
//
// Revision 1.13  2003/03/01 22:53:33  mohor
// Actel APA ram supported.
//
// Revision 1.12  2003/02/19 14:44:03  mohor
// CAN core finished. Host interface added. Registers finished.
// Synchronization to the wishbone finished.
//
// Revision 1.11  2003/02/14 20:17:01  mohor
// Several registers added. Not finished, yet.
//
// Revision 1.10  2003/02/11 00:56:06  mohor
// Wishbone interface added.
//
// Revision 1.9  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.8  2003/01/31 01:13:38  mohor
// backup.
//
// Revision 1.7  2003/01/17 17:44:31  mohor
// Fifo corrected to be synthesizable.
//
// Revision 1.6  2003/01/15 13:16:47  mohor
// When a frame with "remote request" is received, no data is stored
// to fifo, just the frame information (identifier, ...). Data length
// that is stored is the received data length and not the actual data
// length that is stored to fifo.
//
// Revision 1.5  2003/01/14 17:25:09  mohor
// Addresses corrected to decimal values (previously hex).
//
// Revision 1.4  2003/01/14 12:19:35  mohor
// rx_fifo is now working.
//
// Revision 1.3  2003/01/09 21:54:45  mohor
// rx fifo added. Not 100 % verified, yet.
//
// Revision 1.2  2003/01/09 14:46:58  mohor
// Temporary files (backup).
//
// Revision 1.1  2003/01/08 02:10:55  mohor
// Acceptance filter added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "can_defines.v"
 
module can_fifo
(
  clk,
  rst,
 
  wr,
 
  data_in,
  addr,
  data_out,
  fifo_selected,
 
  reset_mode,
  release_buffer,
  extended_mode,
  overrun,
  info_empty,
  info_cnt
 
);
 
parameter Tp = 1;
 
input         clk;
input         rst;
input         wr;
input   [7:0] data_in;
input   [7:0] addr;
input         reset_mode;
input         release_buffer;
input         extended_mode;
input         fifo_selected;
 
output  [7:0] data_out;
output        overrun;
output        info_empty;
output  [6:0] info_cnt;
 
`ifdef ACTEL_APA_RAM
`else
`ifdef XILINX_RAM
`else
  reg     [7:0] fifo [0:63];
  reg     [3:0] length_fifo[0:63];
  reg           overrun_info[0:63];
`endif
`endif
 
reg     [5:0] rd_pointer;
reg     [5:0] wr_pointer;
reg     [5:0] read_address;
reg     [5:0] wr_info_pointer;
reg     [5:0] rd_info_pointer;
reg           wr_q;
reg     [3:0] len_cnt;
reg     [6:0] fifo_cnt;
reg     [6:0] info_cnt;
reg           latch_overrun;
reg           initialize_memories;
 
wire    [3:0] length_info;
wire          write_length_info;
wire          fifo_empty;
wire          fifo_full;
wire          info_full;
 
assign write_length_info = (~wr) & wr_q;
 
// Delayed write signal
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_q <= 0;
  else if (reset_mode)
    wr_q <=#Tp 0;
  else
    wr_q <=#Tp wr;
end
 
 
// length counter
always @ (posedge clk or posedge rst)
begin
  if (rst)
    len_cnt <= 0;
  else if (reset_mode | write_length_info)
    len_cnt <=#Tp 1'b0;
  else if (wr & (~fifo_full))
    len_cnt <=#Tp len_cnt + 1'b1;
end
 
 
// wr_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_info_pointer <= 0;
  else if (write_length_info & (~info_full) | initialize_memories)
    wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
  else if (reset_mode)
    wr_info_pointer <=#Tp 0;
end
 
 
 
// rd_info_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_info_pointer <= 0;
  else if (reset_mode)
    rd_info_pointer <=#Tp 0;
  else if (release_buffer & (~fifo_empty))
    rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
 
 
// rd_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    rd_pointer <= 0;
  else if (release_buffer & (~fifo_empty))
    rd_pointer <=#Tp rd_pointer + length_info;
  else if (reset_mode)
    rd_pointer <=#Tp 0;
end
 
 
// wr_pointer
always @ (posedge clk or posedge rst)
begin
  if (rst)
    wr_pointer <= 0;
  else if (wr & (~fifo_full))
    wr_pointer <=#Tp wr_pointer + 1'b1;
  else if (reset_mode)
    wr_pointer <=#Tp 0;
end
 
 
// latch_overrun
always @ (posedge clk or posedge rst)
begin
  if (rst)
    latch_overrun <= 0;
  else if (reset_mode | write_length_info)
    latch_overrun <=#Tp 0;
  else if (wr & fifo_full)
    latch_overrun <=#Tp 1'b1;
end
 
 
// Counting data in fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    fifo_cnt <= 0;
  else if (wr & (~release_buffer) & (~fifo_full))
    fifo_cnt <=#Tp fifo_cnt + 1'b1;
  else if ((~wr) & release_buffer & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - length_info;
  else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
    fifo_cnt <=#Tp fifo_cnt - length_info + 1'b1;
  else if (reset_mode)
    fifo_cnt <=#Tp 0;
end
 
assign fifo_full = fifo_cnt == 64;
assign fifo_empty = fifo_cnt == 0;
 
 
// Counting data in length_fifo and overrun_info fifo
always @ (posedge clk or posedge rst)
begin
  if (rst)
    info_cnt <= 0;
  else if (write_length_info ^ release_buffer)
    begin
      if (release_buffer & (~info_empty))
        info_cnt <=#Tp info_cnt - 1'b1;
      else if (write_length_info & (~info_full))
        info_cnt <=#Tp info_cnt + 1'b1;
    end
end
 
assign info_full = info_cnt == 64;
assign info_empty = info_cnt == 0;
 
 
// Selecting which address will be used for reading data from rx fifo
always @ (extended_mode or rd_pointer or addr)
begin
  if (extended_mode)      // extended mode
    begin
      read_address <= rd_pointer + (addr - 8'd16);
    end
  else                    // normal mode
    begin
      read_address <= rd_pointer + (addr - 8'd20);
    end
end
 
 
always @ (posedge clk or posedge rst)
begin
  if (rst)
    initialize_memories <= 1;
  else if (&wr_info_pointer)
    initialize_memories <=#Tp 1'b0;
end
 
 
`ifdef ACTEL_APA_RAM
  actel_ram_64x8_sync fifo
  (
    .DO      (data_out),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (data_in),
    .PO      (),                       // parity not used
    .WRB     (~(wr & (~fifo_full))),
    .RDB     (~fifo_selected),
    .WADDR   (wr_pointer),
    .RADDR   (read_address)
  );
 
 
  actel_ram_64x4_sync info_fifo
  (
    .DO      (length_info),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      (len_cnt & {4{~initialize_memories}}),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
 
 
  actel_ram_64x1_sync overrun_fifo
  (
    .DO      (overrun),
    .RCLOCK  (clk),
    .WCLOCK  (clk),
    .DI      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .PO      (),                       // parity not used
    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
    .RDB     (1'b0),                   // always enabled
    .WADDR   (wr_info_pointer),
    .RADDR   (rd_info_pointer)
  );
`else
`ifdef XILINX_RAM
 
/*
  ram_64x8_sync fifo
  (
    .addra(wr_pointer),
    .addrb(read_address),
    .clka(clk),
    .clkb(clk),
    .dina(data_in),
    .doutb(data_out),
    .wea(wr & (~fifo_full))
  );
*/
 
  RAMB4_S8_S8 fifo
  (
    .DOA(),
    .DOB(data_out),
    .ADDRA({3'h0, wr_pointer}),
    .CLKA(clk),
    .DIA(data_in),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(wr & (~fifo_full)),
    .ADDRB({3'h0, read_address}),
    .CLKB(clk),
    .DIB(8'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
 
/*
  ram_64x4_sync info_fifo
  (
    .addra(wr_info_pointer),
    .addrb(rd_info_pointer),
    .clka(clk),
    .clkb(clk),
    .dina(len_cnt),
    .doutb(length_info),
    .wea(write_length_info & (~info_full))
  );
*/
  RAMB4_S4_S4 info_fifo
  (
    .DOA(),
    .DOB(length_info),
    .ADDRA({4'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA(len_cnt & {4{~initialize_memories}}),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({4'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(4'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
/*
  ram_64x1_sync overrun_fifo
  (
    .addra(wr_info_pointer),
    .addrb(rd_info_pointer),
    .clka(clk),
    .clkb(clk),
    .dina(latch_overrun | (wr & fifo_full)),
    .doutb(overrun),
    .wea(write_length_info & (~info_full))
  );
*/
 
 
  RAMB4_S1_S1 overrun_fifo
  (
    .DOA(),
    .DOB(overrun),
    .ADDRA({6'h0, wr_info_pointer}),
    .CLKA(clk),
    .DIA((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
    .ENA(1'b1),
    .RSTA(1'b0),
    .WEA(write_length_info & (~info_full) | initialize_memories),
    .ADDRB({6'h0, rd_info_pointer}),
    .CLKB(clk),
    .DIB(1'h0),
    .ENB(1'b1),
    .RSTB(1'b0),
    .WEB(1'b0)
  );
 
 
`else
  // writing data to fifo
  always @ (posedge clk)
  begin
    if (wr & (~fifo_full))
      fifo[wr_pointer] <=#Tp data_in;
  end
 
  // reading from fifo
  assign data_out = fifo[read_address];
 
 
  // writing length_fifo
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories))
      length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
  end
 
 
  // reading length_fifo
  assign length_info = length_fifo[rd_info_pointer];
 
  // overrun_info
  always @ (posedge clk)
  begin
    if (write_length_info & (~info_full) | initialize_memories)
      overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
  end
 
 
  // reading overrun
  assign overrun = overrun_info[rd_info_pointer];
 
 
`endif
`endif
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	11	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// can_fifo.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the CAN Protocol Controller ////`
7			`//// http://www.opencores.org/projects/can/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002, 2003 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43	28	mohor	`//// The CAN protocol is developed by Robert Bosch GmbH and ////`
44			`//// protected by patents. Anybody who wants to implement this ////`
45			`//// CAN IP core on silicon has to obtain a CAN protocol license ////`
46			`//// from Bosch. ////`
47			`//// ////`
48	11	mohor	`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53	73	mohor	`// Revision 1.14 2003/03/05 15:02:30 mohor`
54			`// Xilinx RAM added.`
55			`//`
56	51	mohor	`// Revision 1.13 2003/03/01 22:53:33 mohor`
57			`// Actel APA ram supported.`
58			`//`
59	48	mohor	`// Revision 1.12 2003/02/19 14:44:03 mohor`
60			`// CAN core finished. Host interface added. Registers finished.`
61			`// Synchronization to the wishbone finished.`
62			`//`
63	39	mohor	`// Revision 1.11 2003/02/14 20:17:01 mohor`
64			`// Several registers added. Not finished, yet.`
65			`//`
66	35	mohor	`// Revision 1.10 2003/02/11 00:56:06 mohor`
67			`// Wishbone interface added.`
68			`//`
69	31	mohor	`// Revision 1.9 2003/02/09 02:24:33 mohor`
70			`// Bosch license warning added. Error counters finished. Overload frames`
71			`// still need to be fixed.`
72			`//`
73	28	mohor	`// Revision 1.8 2003/01/31 01:13:38 mohor`
74			`// backup.`
75			`//`
76	24	mohor	`// Revision 1.7 2003/01/17 17:44:31 mohor`
77			`// Fifo corrected to be synthesizable.`
78			`//`
79	23	mohor	`// Revision 1.6 2003/01/15 13:16:47 mohor`
80	31	mohor	`// When a frame with "remote request" is received, no data is stored`
81			`// to fifo, just the frame information (identifier, ...). Data length`
82			`// that is stored is the received data length and not the actual data`
83			`// length that is stored to fifo.`
84	23	mohor	`//`
85	18	mohor	`// Revision 1.5 2003/01/14 17:25:09 mohor`
86			`// Addresses corrected to decimal values (previously hex).`
87			`//`
88	17	mohor	`// Revision 1.4 2003/01/14 12:19:35 mohor`
89			`// rx_fifo is now working.`
90			`//`
91	16	mohor	`// Revision 1.3 2003/01/09 21:54:45 mohor`
92			`// rx fifo added. Not 100 % verified, yet.`
93			`//`
94	14	mohor	`// Revision 1.2 2003/01/09 14:46:58 mohor`
95			`// Temporary files (backup).`
96			`//`
97	13	mohor	`// Revision 1.1 2003/01/08 02:10:55 mohor`
98			`// Acceptance filter added.`
99	11	mohor	`//`
100			`//`
101			`//`
102	13	mohor	`//`
103	11	mohor
104			`// synopsys translate_off`
105			`include "timescale.v"
106			`// synopsys translate_on`
107			`include "can_defines.v"
108
109			`module can_fifo`
110			`(`
111			`clk,`
112			`rst,`
113
114			`wr,`
115
116			`data_in,`
117	14	mohor	`addr,`
118	11	mohor	`data_out,`
119	48	mohor	`fifo_selected,`
120	11	mohor
121			`reset_mode,`
122	14	mohor	`release_buffer,`
123	35	mohor	`extended_mode,`
124			`overrun,`
125	39	mohor	`info_empty,`
126			`info_cnt`
127	13	mohor
128	11	mohor	`);`
129
130			`parameter Tp = 1;`
131
132			`input clk;`
133			`input rst;`
134			`input wr;`
135			`input [7:0] data_in;`
136	14	mohor	`input [7:0] addr;`
137	11	mohor	`input reset_mode;`
138			`input release_buffer;`
139	14	mohor	`input extended_mode;`
140	48	mohor	`input fifo_selected;`
141	11	mohor
142	13	mohor	`output [7:0] data_out;`
143	35	mohor	`output overrun;`
144			`output info_empty;`
145	39	mohor	`output [6:0] info_cnt;`
146	11	mohor
147	48	mohor	`ifdef ACTEL_APA_RAM
148			`else
149	51	mohor	`ifdef XILINX_RAM
150			`else
151	48	mohor	`reg [7:0] fifo [0:63];`
152			`reg [3:0] length_fifo[0:63];`
153			`reg overrun_info[0:63];`
154			`endif
155	51	mohor	`endif
156	11	mohor
157			`reg [5:0] rd_pointer;`
158			`reg [5:0] wr_pointer;`
159	14	mohor	`reg [5:0] read_address;`
160	16	mohor	`reg [5:0] wr_info_pointer;`
161			`reg [5:0] rd_info_pointer;`
162	13	mohor	`reg wr_q;`
163			`reg [3:0] len_cnt;`
164	16	mohor	`reg [6:0] fifo_cnt;`
165	24	mohor	`reg [6:0] info_cnt;`
166	16	mohor	`reg latch_overrun;`
167	73	mohor	`reg initialize_memories;`
168	11	mohor
169	48	mohor	`wire [3:0] length_info;`
170	13	mohor	`wire write_length_info;`
171	16	mohor	`wire fifo_empty;`
172			`wire fifo_full;`
173	24	mohor	`wire info_full;`
174	11	mohor
175	13	mohor	`assign write_length_info = (~wr) & wr_q;`
176
177			`// Delayed write signal`
178			`always @ (posedge clk or posedge rst)`
179			`begin`
180			`if (rst)`
181			`wr_q <= 0;`
182			`else if (reset_mode)`
183			`wr_q <=#Tp 0;`
184			`else`
185			`wr_q <=#Tp wr;`
186			`end`
187
188
189			`// length counter`
190			`always @ (posedge clk or posedge rst)`
191			`begin`
192			`if (rst)`
193			`len_cnt <= 0;`
194			`else if (reset_mode \| write_length_info)`
195			`len_cnt <=#Tp 1'b0;`
196	16	mohor	`else if (wr & (~fifo_full))`
197	13	mohor	`len_cnt <=#Tp len_cnt + 1'b1;`
198			`end`
199
200
201			`// wr_info_pointer`
202			`always @ (posedge clk or posedge rst)`
203			`begin`
204			`if (rst)`
205			`wr_info_pointer <= 0;`
206	73	mohor	`else if (write_length_info & (~info_full) \| initialize_memories)`
207			`wr_info_pointer <=#Tp wr_info_pointer + 1'b1;`
208	13	mohor	`else if (reset_mode)`
209			`wr_info_pointer <=#Tp 0;`
210			`end`
211
212
213
214			`// rd_info_pointer`
215	11	mohor	`always @ (posedge clk or posedge rst)`
216			`begin`
217			`if (rst)`
218	13	mohor	`rd_info_pointer <= 0;`
219	11	mohor	`else if (reset_mode)`
220	13	mohor	`rd_info_pointer <=#Tp 0;`
221	16	mohor	`else if (release_buffer & (~fifo_empty))`
222	13	mohor	`rd_info_pointer <=#Tp rd_info_pointer + 1'b1;`
223	11	mohor	`end`
224
225
226			`// rd_pointer`
227			`always @ (posedge clk or posedge rst)`
228			`begin`
229			`if (rst)`
230			`rd_pointer <= 0;`
231	16	mohor	`else if (release_buffer & (~fifo_empty))`
232	48	mohor	`rd_pointer <=#Tp rd_pointer + length_info;`
233	11	mohor	`else if (reset_mode)`
234			`rd_pointer <=#Tp 0;`
235			`end`
236
237
238			`// wr_pointer`
239			`always @ (posedge clk or posedge rst)`
240			`begin`
241			`if (rst)`
242			`wr_pointer <= 0;`
243	16	mohor	`else if (wr & (~fifo_full))`
244	13	mohor	`wr_pointer <=#Tp wr_pointer + 1'b1;`
245	11	mohor	`else if (reset_mode)`
246			`wr_pointer <=#Tp 0;`
247			`end`
248
249
250	16	mohor	`// latch_overrun`
251			`always @ (posedge clk or posedge rst)`
252			`begin`
253			`if (rst)`
254			`latch_overrun <= 0;`
255			`else if (reset_mode \| write_length_info)`
256			`latch_overrun <=#Tp 0;`
257			`else if (wr & fifo_full)`
258			`latch_overrun <=#Tp 1'b1;`
259			`end`
260
261
262			`// Counting data in fifo`
263			`always @ (posedge clk or posedge rst)`
264			`begin`
265			`if (rst)`
266			`fifo_cnt <= 0;`
267			`else if (wr & (~release_buffer) & (~fifo_full))`
268			`fifo_cnt <=#Tp fifo_cnt + 1'b1;`
269			`else if ((~wr) & release_buffer & (~fifo_empty))`
270	48	mohor	`fifo_cnt <=#Tp fifo_cnt - length_info;`
271	16	mohor	`else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))`
272	48	mohor	`fifo_cnt <=#Tp fifo_cnt - length_info + 1'b1;`
273	16	mohor	`else if (reset_mode)`
274			`fifo_cnt <=#Tp 0;`
275			`end`
276
277			`assign fifo_full = fifo_cnt == 64;`
278			`assign fifo_empty = fifo_cnt == 0;`
279
280
281	48	mohor	`// Counting data in length_fifo and overrun_info fifo`
282	24	mohor	`always @ (posedge clk or posedge rst)`
283			`begin`
284			`if (rst)`
285			`info_cnt <= 0;`
286			`else if (write_length_info ^ release_buffer)`
287			`begin`
288			`if (release_buffer & (~info_empty))`
289			`info_cnt <=#Tp info_cnt - 1'b1;`
290			`else if (write_length_info & (~info_full))`
291			`info_cnt <=#Tp info_cnt + 1'b1;`
292			`end`
293			`end`
294
295			`assign info_full = info_cnt == 64;`
296			`assign info_empty = info_cnt == 0;`
297	16	mohor
298	24	mohor
299	14	mohor	`// Selecting which address will be used for reading data from rx fifo`
300			`always @ (extended_mode or rd_pointer or addr)`
301			`begin`
302			`if (extended_mode) // extended mode`
303			`begin`
304	17	mohor	`read_address <= rd_pointer + (addr - 8'd16);`
305	14	mohor	`end`
306			`else // normal mode`
307			`begin`
308	17	mohor	`read_address <= rd_pointer + (addr - 8'd20);`
309	14	mohor	`end`
310			`end`
311	11	mohor
312
313	73	mohor	`always @ (posedge clk or posedge rst)`
314			`begin`
315			`if (rst)`
316			`initialize_memories <= 1;`
317			`else if (&wr_info_pointer)`
318			`initialize_memories <=#Tp 1'b0;`
319			`end`
320	14	mohor
321	73	mohor
322	48	mohor	`ifdef ACTEL_APA_RAM
323			`actel_ram_64x8_sync fifo`
324			`(`
325			`.DO (data_out),`
326			`.RCLOCK (clk),`
327			`.WCLOCK (clk),`
328			`.DI (data_in),`
329			`.PO (), // parity not used`
330			`.WRB (~(wr & (~fifo_full))),`
331			`.RDB (~fifo_selected),`
332			`.WADDR (wr_pointer),`
333			`.RADDR (read_address)`
334			`);`
335	14	mohor
336
337	48	mohor	`actel_ram_64x4_sync info_fifo`
338			`(`
339			`.DO (length_info),`
340			`.RCLOCK (clk),`
341			`.WCLOCK (clk),`
342	73	mohor	`.DI (len_cnt & {4{~initialize_memories}}),`
343	48	mohor	`.PO (), // parity not used`
344	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
345	48	mohor	`.RDB (1'b0), // always enabled`
346			`.WADDR (wr_info_pointer),`
347			`.RADDR (rd_info_pointer)`
348			`);`
349	14	mohor
350
351	48	mohor	`actel_ram_64x1_sync overrun_fifo`
352			`(`
353			`.DO (overrun),`
354			`.RCLOCK (clk),`
355			`.WCLOCK (clk),`
356	73	mohor	`.DI ((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
357	48	mohor	`.PO (), // parity not used`
358	73	mohor	`.WRB (~(write_length_info & (~info_full) \| initialize_memories)),`
359	48	mohor	`.RDB (1'b0), // always enabled`
360			`.WADDR (wr_info_pointer),`
361			`.RADDR (rd_info_pointer)`
362			`);`
363			`else
364	51	mohor	`ifdef XILINX_RAM
365
366			`/*`
367			`ram_64x8_sync fifo`
368			`(`
369			`.addra(wr_pointer),`
370			`.addrb(read_address),`
371			`.clka(clk),`
372			`.clkb(clk),`
373			`.dina(data_in),`
374			`.doutb(data_out),`
375			`.wea(wr & (~fifo_full))`
376			`);`
377			`*/`
378
379			`RAMB4_S8_S8 fifo`
380			`(`
381			`.DOA(),`
382			`.DOB(data_out),`
383			`.ADDRA({3'h0, wr_pointer}),`
384			`.CLKA(clk),`
385			`.DIA(data_in),`
386			`.ENA(1'b1),`
387			`.RSTA(1'b0),`
388			`.WEA(wr & (~fifo_full)),`
389			`.ADDRB({3'h0, read_address}),`
390			`.CLKB(clk),`
391			`.DIB(8'h0),`
392			`.ENB(1'b1),`
393			`.RSTB(1'b0),`
394			`.WEB(1'b0)`
395			`);`
396
397
398
399			`/*`
400			`ram_64x4_sync info_fifo`
401			`(`
402			`.addra(wr_info_pointer),`
403			`.addrb(rd_info_pointer),`
404			`.clka(clk),`
405			`.clkb(clk),`
406			`.dina(len_cnt),`
407			`.doutb(length_info),`
408			`.wea(write_length_info & (~info_full))`
409			`);`
410			`*/`
411			`RAMB4_S4_S4 info_fifo`
412			`(`
413			`.DOA(),`
414			`.DOB(length_info),`
415			`.ADDRA({4'h0, wr_info_pointer}),`
416			`.CLKA(clk),`
417	73	mohor	`.DIA(len_cnt & {4{~initialize_memories}}),`
418	51	mohor	`.ENA(1'b1),`
419			`.RSTA(1'b0),`
420	73	mohor	`.WEA(write_length_info & (~info_full) \| initialize_memories),`
421	51	mohor	`.ADDRB({4'h0, rd_info_pointer}),`
422			`.CLKB(clk),`
423			`.DIB(4'h0),`
424			`.ENB(1'b1),`
425			`.RSTB(1'b0),`
426			`.WEB(1'b0)`
427			`);`
428
429			`/*`
430			`ram_64x1_sync overrun_fifo`
431			`(`
432			`.addra(wr_info_pointer),`
433			`.addrb(rd_info_pointer),`
434			`.clka(clk),`
435			`.clkb(clk),`
436			`.dina(latch_overrun \| (wr & fifo_full)),`
437			`.doutb(overrun),`
438			`.wea(write_length_info & (~info_full))`
439			`);`
440			`*/`
441
442
443			`RAMB4_S1_S1 overrun_fifo`
444			`(`
445			`.DOA(),`
446			`.DOB(overrun),`
447			`.ADDRA({6'h0, wr_info_pointer}),`
448			`.CLKA(clk),`
449	73	mohor	`.DIA((latch_overrun \| (wr & fifo_full)) & (~initialize_memories)),`
450	51	mohor	`.ENA(1'b1),`
451			`.RSTA(1'b0),`
452	73	mohor	`.WEA(write_length_info & (~info_full) \| initialize_memories),`
453	51	mohor	`.ADDRB({6'h0, rd_info_pointer}),`
454			`.CLKB(clk),`
455			`.DIB(1'h0),`
456			`.ENB(1'b1),`
457			`.RSTB(1'b0),`
458			`.WEB(1'b0)`
459			`);`
460
461
462			`else
463	48	mohor	`// writing data to fifo`
464			`always @ (posedge clk)`
465			`begin`
466			`if (wr & (~fifo_full))`
467			`fifo[wr_pointer] <=#Tp data_in;`
468			`end`
469
470			`// reading from fifo`
471			`assign data_out = fifo[read_address];`
472
473
474			`// writing length_fifo`
475			`always @ (posedge clk)`
476			`begin`
477	73	mohor	`if (write_length_info & (~info_full) \| initialize_memories))`
478			`length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};`
479	48	mohor	`end`
480
481	73	mohor
482	48	mohor	`// reading length_fifo`
483			`assign length_info = length_fifo[rd_info_pointer];`
484
485			`// overrun_info`
486			`always @ (posedge clk)`
487			`begin`
488	73	mohor	`if (write_length_info & (~info_full) \| initialize_memories)`
489			`overrun_info[wr_info_pointer] <=#Tp (latch_overrun \| (wr & fifo_full)) & (~initialize_memories);`
490	48	mohor	`end`
491
492
493			`// reading overrun`
494			`assign overrun = overrun_info[rd_info_pointer];`
495
496
497			`endif
498	51	mohor	`endif
499	48	mohor
500

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