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//////////////////////////////////////////////////////////////////////
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//// ////
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//// can_register_asyn_syn.v ////
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//// ////
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//// ////
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//// This file is part of the CAN Protocol Controller ////
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//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002, 2003, 2004 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// The CAN protocol is developed by Robert Bosch GmbH and ////
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//// protected by patents. Anybody who wants to implement this ////
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//// CAN IP core on silicon has to obtain a CAN protocol license ////
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//// from Bosch. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2003/03/20 16:52:43 mohor
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// unix.
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//
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// Revision 1.4 2003/03/11 16:32:34 mohor
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// timescale.v is used for simulation only.
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//
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// Revision 1.3 2003/02/09 02:24:33 mohor
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// Bosch license warning added. Error counters finished. Overload frames
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// still need to be fixed.
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//
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// Revision 1.2 2002/12/27 00:12:52 mohor
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// Header changed, testbench improved to send a frame (crc still missing).
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//
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// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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// Initial
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module can_register_asyn_syn
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( data_in,
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data_out,
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we,
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clk,
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rst,
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rst_sync
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);
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parameter WIDTH = 8; // default parameter of the register width
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parameter RESET_VALUE = 0;
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input [WIDTH-1:0] data_in;
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input we;
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input clk;
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input rst;
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input rst_sync;
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output [WIDTH-1:0] data_out;
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reg [WIDTH-1:0] data_out;
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always @ (posedge clk or posedge rst)
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begin
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if(rst)
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data_out<=#1 RESET_VALUE;
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else if (rst_sync) // synchronous reset
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data_out<=#1 RESET_VALUE;
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else if (we) // write
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data_out<=#1 data_in;
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end
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endmodule
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